aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-ixp4xx/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-ixp4xx/include')
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/avila.h39
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/coyote.h33
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/cpu.h46
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/debug-macro.S24
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/dma.h21
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/dsmg600.h52
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/entry-macro.S47
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/fsg.h50
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/gpio.h73
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/gtwx5715.h116
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/hardware.h50
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/io.h569
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/irqs.h138
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/ixdp425.h39
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h638
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/memory.h40
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/nas100d.h52
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/npe.h39
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/nslu2.h55
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/platform.h173
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/prpmc1100.h33
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/qmgr.h126
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/system.h42
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/timex.h15
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/udc.h8
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/uncompress.h57
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/vmalloc.h5
27 files changed, 2580 insertions, 0 deletions
diff --git a/arch/arm/mach-ixp4xx/include/mach/avila.h b/arch/arm/mach-ixp4xx/include/mach/avila.h
new file mode 100644
index 000000000000..1640cb61972b
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/avila.h
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/avila.h
3 *
4 * Gateworks Avila platform specific definitions
5 *
6 * Author: Michael-Luke Jones <mlj28@cam.ac.uk>
7 *
8 * Based on ixdp425.h
9 * Author: Deepak Saxena <dsaxena@plexity.net>
10 *
11 * Copyright 2004 (c) MontaVista, Software, Inc.
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <mach/hardware.h>"
20#endif
21
22#define AVILA_SDA_PIN 7
23#define AVILA_SCL_PIN 6
24
25/*
26 * AVILA PCI IRQs
27 */
28#define AVILA_PCI_MAX_DEV 4
29#define LOFT_PCI_MAX_DEV 6
30#define AVILA_PCI_IRQ_LINES 4
31
32
33/* PCI controller GPIO to IRQ pin mappings */
34#define AVILA_PCI_INTA_PIN 11
35#define AVILA_PCI_INTB_PIN 10
36#define AVILA_PCI_INTC_PIN 9
37#define AVILA_PCI_INTD_PIN 8
38
39
diff --git a/arch/arm/mach-ixp4xx/include/mach/coyote.h b/arch/arm/mach-ixp4xx/include/mach/coyote.h
new file mode 100644
index 000000000000..717ac6d16f55
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/coyote.h
@@ -0,0 +1,33 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/coyote.h
3 *
4 * ADI Engineering platform specific definitions
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <mach/hardware.h>"
17#endif
18
19/* PCI controller GPIO to IRQ pin mappings */
20#define COYOTE_PCI_SLOT0_PIN 6
21#define COYOTE_PCI_SLOT1_PIN 11
22
23#define COYOTE_PCI_SLOT0_DEVID 14
24#define COYOTE_PCI_SLOT1_DEVID 15
25
26#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
27#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
28#define COYOTE_IDE_REGION_SIZE 0x1000
29
30#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
31#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
32#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
33
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
new file mode 100644
index 000000000000..ff8aa2393bf9
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/cpu.h
3 *
4 * IXP4XX cpu type detection
5 *
6 * Copyright (C) 2007 MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef __ASM_ARCH_CPU_H__
15#define __ASM_ARCH_CPU_H__
16
17extern unsigned int processor_id;
18/* Processor id value in CP15 Register 0 */
19#define IXP425_PROCESSOR_ID_VALUE 0x690541c0
20#define IXP435_PROCESSOR_ID_VALUE 0x69054040
21#define IXP465_PROCESSOR_ID_VALUE 0x69054200
22#define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0
23
24#define cpu_is_ixp42x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
25 IXP425_PROCESSOR_ID_VALUE)
26#define cpu_is_ixp43x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
27 IXP435_PROCESSOR_ID_VALUE)
28#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
29 IXP465_PROCESSOR_ID_VALUE)
30
31static inline u32 ixp4xx_read_feature_bits(void)
32{
33 unsigned int val = ~*IXP4XX_EXP_CFG2;
34 val &= ~IXP4XX_FEATURE_RESERVED;
35 if (!cpu_is_ixp46x())
36 val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
37
38 return val;
39}
40
41static inline void ixp4xx_write_feature_bits(u32 value)
42{
43 *IXP4XX_EXP_CFG2 = ~value;
44}
45
46#endif /* _ASM_ARCH_CPU_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..7c6a6912acde
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
@@ -0,0 +1,24 @@
1/* arch/arm/mach-ixp4xx/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13 .macro addruart,rx
14 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled?
16 moveq \rx, #0xc8000000
17 movne \rx, #0xff000000
18 orrne \rx, \rx, #0x00b00000
19 add \rx,\rx,#3 @ Uart regs are at off set of 3 if
20 @ byte writes used - Big Endian.
21 .endm
22
23#define UART_SHIFT 2
24#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp4xx/include/mach/dma.h b/arch/arm/mach-ixp4xx/include/mach/dma.h
new file mode 100644
index 000000000000..00c5070c0201
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/dma.h
@@ -0,0 +1,21 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/dma.h
3 *
4 * Copyright (C) 2001-2004 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H
13
14#include <linux/device.h>
15#include <asm/page.h>
16#include <asm/sizes.h>
17#include <mach/hardware.h>
18
19#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
20
21#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/dsmg600.h b/arch/arm/mach-ixp4xx/include/mach/dsmg600.h
new file mode 100644
index 000000000000..dc087a34a268
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/dsmg600.h
@@ -0,0 +1,52 @@
1/*
2 * DSM-G600 platform specific definitions
3 *
4 * Copyright (C) 2006 Tower Technologies
5 * Author: Alessandro Zummo <a.zummo@towertech.it>
6 *
7 * based on ixdp425.h:
8 * Copyright 2004 (C) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <mach/hardware.h>"
17#endif
18
19#define DSMG600_SDA_PIN 5
20#define DSMG600_SCL_PIN 4
21
22/*
23 * DSMG600 PCI IRQs
24 */
25#define DSMG600_PCI_MAX_DEV 4
26#define DSMG600_PCI_IRQ_LINES 3
27
28
29/* PCI controller GPIO to IRQ pin mappings */
30#define DSMG600_PCI_INTA_PIN 11
31#define DSMG600_PCI_INTB_PIN 10
32#define DSMG600_PCI_INTC_PIN 9
33#define DSMG600_PCI_INTD_PIN 8
34#define DSMG600_PCI_INTE_PIN 7
35#define DSMG600_PCI_INTF_PIN 6
36
37/* DSM-G600 Timer Setting */
38#define DSMG600_FREQ 66000000
39
40/* Buttons */
41
42#define DSMG600_PB_GPIO 15 /* power button */
43#define DSMG600_RB_GPIO 3 /* reset button */
44
45/* Power control */
46
47#define DSMG600_PO_GPIO 2 /* power off */
48
49/* LEDs */
50
51#define DSMG600_LED_PWR_GPIO 0
52#define DSMG600_LED_WLAN_GPIO 14
diff --git a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..f2e14e94ed15
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
@@ -0,0 +1,47 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IXP4xx-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/hardware.h>
11
12 .macro disable_fiq
13 .endm
14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro arch_ret_to_user, tmp1, tmp2
19 .endm
20
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
22 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
23 ldr \irqstat, [\irqstat] @ get interrupts
24 cmp \irqstat, #0
25 beq 1001f @ upper IRQ?
26 clz \irqnr, \irqstat
27 mov \base, #31
28 sub \irqnr, \base, \irqnr
29 b 1002f @ lower IRQ being
30 @ handled
31
321001:
33 /*
34 * IXP465/IXP435 has an upper IRQ status register
35 */
36#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
37 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
38 ldr \irqstat, [\irqstat] @ get upper interrupts
39 mov \irqnr, #63
40 clz \irqstat, \irqstat
41 cmp \irqstat, #32
42 subne \irqnr, \irqnr, \irqstat
43#endif
441002:
45 .endm
46
47
diff --git a/arch/arm/mach-ixp4xx/include/mach/fsg.h b/arch/arm/mach-ixp4xx/include/mach/fsg.h
new file mode 100644
index 000000000000..1f02b7e22a13
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/fsg.h
@@ -0,0 +1,50 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/fsg.h
3 *
4 * Freecom FSG-3 platform specific definitions
5 *
6 * Author: Rod Whitby <rod@whitby.id.au>
7 * Author: Tomasz Chmielewski <mangoo@wpkg.org>
8 * Maintainers: http://www.nslu2-linux.org
9 *
10 * Based on coyote.h by
11 * Copyright 2004 (c) MontaVista, Software, Inc.
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <mach/hardware.h>"
20#endif
21
22#define FSG_SDA_PIN 12
23#define FSG_SCL_PIN 13
24
25/*
26 * FSG PCI IRQs
27 */
28#define FSG_PCI_MAX_DEV 3
29#define FSG_PCI_IRQ_LINES 3
30
31
32/* PCI controller GPIO to IRQ pin mappings */
33#define FSG_PCI_INTA_PIN 6
34#define FSG_PCI_INTB_PIN 7
35#define FSG_PCI_INTC_PIN 5
36
37/* Buttons */
38
39#define FSG_SB_GPIO 4 /* sync button */
40#define FSG_RB_GPIO 9 /* reset button */
41#define FSG_UB_GPIO 10 /* usb button */
42
43/* LEDs */
44
45#define FSG_LED_WLAN_BIT 0
46#define FSG_LED_WAN_BIT 1
47#define FSG_LED_SATA_BIT 2
48#define FSG_LED_USB_BIT 4
49#define FSG_LED_RING_BIT 5
50#define FSG_LED_SYNC_BIT 7
diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h
new file mode 100644
index 000000000000..9fbde177920f
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h
@@ -0,0 +1,73 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/gpio.h
3 *
4 * IXP4XX GPIO wrappers for arch-neutral GPIO calls
5 *
6 * Written by Milan Svoboda <msvoboda@ra.rockwell.com>
7 * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#ifndef __ASM_ARCH_IXP4XX_GPIO_H
26#define __ASM_ARCH_IXP4XX_GPIO_H
27
28#include <mach/hardware.h>
29
30static inline int gpio_request(unsigned gpio, const char *label)
31{
32 return 0;
33}
34
35static inline void gpio_free(unsigned gpio)
36{
37 return;
38}
39
40static inline int gpio_direction_input(unsigned gpio)
41{
42 gpio_line_config(gpio, IXP4XX_GPIO_IN);
43 return 0;
44}
45
46static inline int gpio_direction_output(unsigned gpio, int level)
47{
48 gpio_line_set(gpio, level);
49 gpio_line_config(gpio, IXP4XX_GPIO_OUT);
50 return 0;
51}
52
53static inline int gpio_get_value(unsigned gpio)
54{
55 int value;
56
57 gpio_line_get(gpio, &value);
58
59 return value;
60}
61
62static inline void gpio_set_value(unsigned gpio, int value)
63{
64 gpio_line_set(gpio, value);
65}
66
67#include <asm-generic/gpio.h> /* cansleep wrappers */
68
69extern int gpio_to_irq(int gpio);
70extern int irq_to_gpio(int gpio);
71
72#endif
73
diff --git a/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h b/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
new file mode 100644
index 000000000000..5d5e201cac7e
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
@@ -0,0 +1,116 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/gtwx5715.h
3 *
4 * Gemtek GTWX5715 Gateway (Linksys WRV54G)
5 *
6 * Copyright 2004 (c) George T. Joseph
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#ifndef __ASM_ARCH_HARDWARE_H__
24#error "Do not include this directly, instead #include <mach/hardware.h>"
25#endif
26#include "irqs.h"
27
28#define GTWX5715_GPIO0 0
29#define GTWX5715_GPIO1 1
30#define GTWX5715_GPIO2 2
31#define GTWX5715_GPIO3 3
32#define GTWX5715_GPIO4 4
33#define GTWX5715_GPIO5 5
34#define GTWX5715_GPIO6 6
35#define GTWX5715_GPIO7 7
36#define GTWX5715_GPIO8 8
37#define GTWX5715_GPIO9 9
38#define GTWX5715_GPIO10 10
39#define GTWX5715_GPIO11 11
40#define GTWX5715_GPIO12 12
41#define GTWX5715_GPIO13 13
42#define GTWX5715_GPIO14 14
43
44#define GTWX5715_GPIO0_IRQ IRQ_IXP4XX_GPIO0
45#define GTWX5715_GPIO1_IRQ IRQ_IXP4XX_GPIO1
46#define GTWX5715_GPIO2_IRQ IRQ_IXP4XX_GPIO2
47#define GTWX5715_GPIO3_IRQ IRQ_IXP4XX_GPIO3
48#define GTWX5715_GPIO4_IRQ IRQ_IXP4XX_GPIO4
49#define GTWX5715_GPIO5_IRQ IRQ_IXP4XX_GPIO5
50#define GTWX5715_GPIO6_IRQ IRQ_IXP4XX_GPIO6
51#define GTWX5715_GPIO7_IRQ IRQ_IXP4XX_GPIO7
52#define GTWX5715_GPIO8_IRQ IRQ_IXP4XX_GPIO8
53#define GTWX5715_GPIO9_IRQ IRQ_IXP4XX_GPIO9
54#define GTWX5715_GPIO10_IRQ IRQ_IXP4XX_GPIO10
55#define GTWX5715_GPIO11_IRQ IRQ_IXP4XX_GPIO11
56#define GTWX5715_GPIO12_IRQ IRQ_IXP4XX_GPIO12
57#define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1
58#define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2
59
60/* PCI controller GPIO to IRQ pin mappings
61
62 INTA INTB
63SLOT 0 10 11
64SLOT 1 11 10
65
66*/
67
68#define GTWX5715_PCI_SLOT0_DEVID 0
69#define GTWX5715_PCI_SLOT0_INTA_GPIO GTWX5715_GPIO10
70#define GTWX5715_PCI_SLOT0_INTB_GPIO GTWX5715_GPIO11
71#define GTWX5715_PCI_SLOT0_INTA_IRQ GTWX5715_GPIO10_IRQ
72#define GTWX5715_PCI_SLOT0_INTB_IRQ GTWX5715_GPIO11_IRQ
73
74#define GTWX5715_PCI_SLOT1_DEVID 1
75#define GTWX5715_PCI_SLOT1_INTA_GPIO GTWX5715_GPIO11
76#define GTWX5715_PCI_SLOT1_INTB_GPIO GTWX5715_GPIO10
77#define GTWX5715_PCI_SLOT1_INTA_IRQ GTWX5715_GPIO11_IRQ
78#define GTWX5715_PCI_SLOT1_INTB_IRQ GTWX5715_GPIO10_IRQ
79
80#define GTWX5715_PCI_SLOT_COUNT 2
81#define GTWX5715_PCI_INT_PIN_COUNT 2
82
83/*
84 * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch
85 * and operate as an SPI type interface. The details of the interface
86 * are available on Kendin/Micrel's web site.
87 */
88
89#define GTWX5715_KSSPI_SELECT GTWX5715_GPIO5
90#define GTWX5715_KSSPI_TXD GTWX5715_GPIO6
91#define GTWX5715_KSSPI_CLOCK GTWX5715_GPIO7
92#define GTWX5715_KSSPI_RXD GTWX5715_GPIO12
93
94/*
95 * The "reset" button is wired to GPIO 3.
96 * The GPIO is brought "low" when the button is pushed.
97 */
98
99#define GTWX5715_BUTTON_GPIO GTWX5715_GPIO3
100#define GTWX5715_BUTTON_IRQ GTWX5715_GPIO3_IRQ
101
102/*
103 * Board Label Front Label
104 * LED1 Power
105 * LED2 Wireless-G
106 * LED3 not populated but could be
107 * LED4 Internet
108 * LED5 - LED8 Controlled by KS8995M Switch
109 * LED9 DMZ
110 */
111
112#define GTWX5715_LED1_GPIO GTWX5715_GPIO2
113#define GTWX5715_LED2_GPIO GTWX5715_GPIO9
114#define GTWX5715_LED3_GPIO GTWX5715_GPIO8
115#define GTWX5715_LED4_GPIO GTWX5715_GPIO1
116#define GTWX5715_LED9_GPIO GTWX5715_GPIO4
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
new file mode 100644
index 000000000000..f58a43a23966
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -0,0 +1,50 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/hardware.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 * Copyright (C) 2003-2004 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13/*
14 * Hardware definitions for IXP4xx based systems
15 */
16
17#ifndef __ASM_ARCH_HARDWARE_H__
18#define __ASM_ARCH_HARDWARE_H__
19
20#define PCIBIOS_MIN_IO 0x00001000
21#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
22
23/*
24 * We override the standard dma-mask routines for bouncing.
25 */
26#define HAVE_ARCH_PCI_SET_DMA_MASK
27
28#define pcibios_assign_all_busses() 1
29
30/* Register locations and bits */
31#include "ixp4xx-regs.h"
32
33#ifndef __ASSEMBLER__
34#include <mach/cpu.h>
35#endif
36
37/* Platform helper functions and definitions */
38#include "platform.h"
39
40/* Platform specific details */
41#include "ixdp425.h"
42#include "avila.h"
43#include "coyote.h"
44#include "prpmc1100.h"
45#include "nslu2.h"
46#include "nas100d.h"
47#include "dsmg600.h"
48#include "fsg.h"
49
50#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
new file mode 100644
index 000000000000..319948e31bec
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -0,0 +1,569 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/io.h
3 *
4 * Author: Deepak Saxena <dsaxena@plexity.net>
5 *
6 * Copyright (C) 2002-2005 MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARM_ARCH_IO_H
14#define __ASM_ARM_ARCH_IO_H
15
16#include <linux/bitops.h>
17
18#include <mach/hardware.h>
19
20#define IO_SPACE_LIMIT 0xffff0000
21
22extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
23extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
24
25
26/*
27 * IXP4xx provides two methods of accessing PCI memory space:
28 *
29 * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
30 * To access PCI via this space, we simply ioremap() the BAR
31 * into the kernel and we can use the standard read[bwl]/write[bwl]
32 * macros. This is the preffered method due to speed but it
33 * limits the system to just 64MB of PCI memory. This can be
34 * problamatic if using video cards and other memory-heavy
35 * targets.
36 *
37 * 2) If > 64MB of memory space is required, the IXP4xx can be configured
38 * to use indirect registers to access PCI (as we do below for I/O
39 * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
40 * of memory on the bus. The disadvantage of this is that every
41 * PCI access requires three local register accesses plus a spinlock,
42 * but in some cases the performance hit is acceptable. In addition,
43 * you cannot mmap() PCI devices in this case.
44 *
45 */
46#ifndef CONFIG_IXP4XX_INDIRECT_PCI
47
48#define __mem_pci(a) (a)
49
50#else
51
52#include <linux/mm.h>
53
54/*
55 * In the case of using indirect PCI, we simply return the actual PCI
56 * address and our read/write implementation use that to drive the
57 * access registers. If something outside of PCI is ioremap'd, we
58 * fallback to the default.
59 */
60static inline void __iomem *
61__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
62{
63 if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
64 return __arm_ioremap(addr, size, mtype);
65
66 return (void __iomem *)addr;
67}
68
69static inline void
70__ixp4xx_iounmap(void __iomem *addr)
71{
72 if ((__force u32)addr >= VMALLOC_START)
73 __iounmap(addr);
74}
75
76#define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f)
77#define __arch_iounmap(a) __ixp4xx_iounmap(a)
78
79#define writeb(v, p) __ixp4xx_writeb(v, p)
80#define writew(v, p) __ixp4xx_writew(v, p)
81#define writel(v, p) __ixp4xx_writel(v, p)
82
83#define writesb(p, v, l) __ixp4xx_writesb(p, v, l)
84#define writesw(p, v, l) __ixp4xx_writesw(p, v, l)
85#define writesl(p, v, l) __ixp4xx_writesl(p, v, l)
86
87#define readb(p) __ixp4xx_readb(p)
88#define readw(p) __ixp4xx_readw(p)
89#define readl(p) __ixp4xx_readl(p)
90
91#define readsb(p, v, l) __ixp4xx_readsb(p, v, l)
92#define readsw(p, v, l) __ixp4xx_readsw(p, v, l)
93#define readsl(p, v, l) __ixp4xx_readsl(p, v, l)
94
95static inline void
96__ixp4xx_writeb(u8 value, volatile void __iomem *p)
97{
98 u32 addr = (u32)p;
99 u32 n, byte_enables, data;
100
101 if (addr >= VMALLOC_START) {
102 __raw_writeb(value, addr);
103 return;
104 }
105
106 n = addr % 4;
107 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
108 data = value << (8*n);
109 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
110}
111
112static inline void
113__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
114{
115 while (count--)
116 writeb(*vaddr++, bus_addr);
117}
118
119static inline void
120__ixp4xx_writew(u16 value, volatile void __iomem *p)
121{
122 u32 addr = (u32)p;
123 u32 n, byte_enables, data;
124
125 if (addr >= VMALLOC_START) {
126 __raw_writew(value, addr);
127 return;
128 }
129
130 n = addr % 4;
131 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
132 data = value << (8*n);
133 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
134}
135
136static inline void
137__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
138{
139 while (count--)
140 writew(*vaddr++, bus_addr);
141}
142
143static inline void
144__ixp4xx_writel(u32 value, volatile void __iomem *p)
145{
146 u32 addr = (__force u32)p;
147 if (addr >= VMALLOC_START) {
148 __raw_writel(value, p);
149 return;
150 }
151
152 ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
153}
154
155static inline void
156__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
157{
158 while (count--)
159 writel(*vaddr++, bus_addr);
160}
161
162static inline unsigned char
163__ixp4xx_readb(const volatile void __iomem *p)
164{
165 u32 addr = (u32)p;
166 u32 n, byte_enables, data;
167
168 if (addr >= VMALLOC_START)
169 return __raw_readb(addr);
170
171 n = addr % 4;
172 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
173 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
174 return 0xff;
175
176 return data >> (8*n);
177}
178
179static inline void
180__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
181{
182 while (count--)
183 *vaddr++ = readb(bus_addr);
184}
185
186static inline unsigned short
187__ixp4xx_readw(const volatile void __iomem *p)
188{
189 u32 addr = (u32)p;
190 u32 n, byte_enables, data;
191
192 if (addr >= VMALLOC_START)
193 return __raw_readw(addr);
194
195 n = addr % 4;
196 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
197 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
198 return 0xffff;
199
200 return data>>(8*n);
201}
202
203static inline void
204__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
205{
206 while (count--)
207 *vaddr++ = readw(bus_addr);
208}
209
210static inline unsigned long
211__ixp4xx_readl(const volatile void __iomem *p)
212{
213 u32 addr = (__force u32)p;
214 u32 data;
215
216 if (addr >= VMALLOC_START)
217 return __raw_readl(p);
218
219 if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
220 return 0xffffffff;
221
222 return data;
223}
224
225static inline void
226__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
227{
228 while (count--)
229 *vaddr++ = readl(bus_addr);
230}
231
232
233/*
234 * We can use the built-in functions b/c they end up calling writeb/readb
235 */
236#define memset_io(c,v,l) _memset_io((c),(v),(l))
237#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
238#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
239
240#endif
241
242#ifndef CONFIG_PCI
243
244#define __io(v) v
245
246#else
247
248/*
249 * IXP4xx does not have a transparent cpu -> PCI I/O translation
250 * window. Instead, it has a set of registers that must be tweaked
251 * with the proper byte lanes, command types, and address for the
252 * transaction. This means that we need to override the default
253 * I/O functions.
254 */
255#define outb(p, v) __ixp4xx_outb(p, v)
256#define outw(p, v) __ixp4xx_outw(p, v)
257#define outl(p, v) __ixp4xx_outl(p, v)
258
259#define outsb(p, v, l) __ixp4xx_outsb(p, v, l)
260#define outsw(p, v, l) __ixp4xx_outsw(p, v, l)
261#define outsl(p, v, l) __ixp4xx_outsl(p, v, l)
262
263#define inb(p) __ixp4xx_inb(p)
264#define inw(p) __ixp4xx_inw(p)
265#define inl(p) __ixp4xx_inl(p)
266
267#define insb(p, v, l) __ixp4xx_insb(p, v, l)
268#define insw(p, v, l) __ixp4xx_insw(p, v, l)
269#define insl(p, v, l) __ixp4xx_insl(p, v, l)
270
271
272static inline void
273__ixp4xx_outb(u8 value, u32 addr)
274{
275 u32 n, byte_enables, data;
276 n = addr % 4;
277 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
278 data = value << (8*n);
279 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
280}
281
282static inline void
283__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
284{
285 while (count--)
286 outb(*vaddr++, io_addr);
287}
288
289static inline void
290__ixp4xx_outw(u16 value, u32 addr)
291{
292 u32 n, byte_enables, data;
293 n = addr % 4;
294 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
295 data = value << (8*n);
296 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
297}
298
299static inline void
300__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
301{
302 while (count--)
303 outw(cpu_to_le16(*vaddr++), io_addr);
304}
305
306static inline void
307__ixp4xx_outl(u32 value, u32 addr)
308{
309 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
310}
311
312static inline void
313__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
314{
315 while (count--)
316 outl(*vaddr++, io_addr);
317}
318
319static inline u8
320__ixp4xx_inb(u32 addr)
321{
322 u32 n, byte_enables, data;
323 n = addr % 4;
324 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
325 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
326 return 0xff;
327
328 return data >> (8*n);
329}
330
331static inline void
332__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
333{
334 while (count--)
335 *vaddr++ = inb(io_addr);
336}
337
338static inline u16
339__ixp4xx_inw(u32 addr)
340{
341 u32 n, byte_enables, data;
342 n = addr % 4;
343 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
344 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
345 return 0xffff;
346
347 return data>>(8*n);
348}
349
350static inline void
351__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
352{
353 while (count--)
354 *vaddr++ = le16_to_cpu(inw(io_addr));
355}
356
357static inline u32
358__ixp4xx_inl(u32 addr)
359{
360 u32 data;
361 if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
362 return 0xffffffff;
363
364 return data;
365}
366
367static inline void
368__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
369{
370 while (count--)
371 *vaddr++ = inl(io_addr);
372}
373
374#define PIO_OFFSET 0x10000UL
375#define PIO_MASK 0x0ffffUL
376
377#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
378 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
379static inline unsigned int
380__ixp4xx_ioread8(const void __iomem *addr)
381{
382 unsigned long port = (unsigned long __force)addr;
383 if (__is_io_address(port))
384 return (unsigned int)__ixp4xx_inb(port & PIO_MASK);
385 else
386#ifndef CONFIG_IXP4XX_INDIRECT_PCI
387 return (unsigned int)__raw_readb(port);
388#else
389 return (unsigned int)__ixp4xx_readb(addr);
390#endif
391}
392
393static inline void
394__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
395{
396 unsigned long port = (unsigned long __force)addr;
397 if (__is_io_address(port))
398 __ixp4xx_insb(port & PIO_MASK, vaddr, count);
399 else
400#ifndef CONFIG_IXP4XX_INDIRECT_PCI
401 __raw_readsb(addr, vaddr, count);
402#else
403 __ixp4xx_readsb(addr, vaddr, count);
404#endif
405}
406
407static inline unsigned int
408__ixp4xx_ioread16(const void __iomem *addr)
409{
410 unsigned long port = (unsigned long __force)addr;
411 if (__is_io_address(port))
412 return (unsigned int)__ixp4xx_inw(port & PIO_MASK);
413 else
414#ifndef CONFIG_IXP4XX_INDIRECT_PCI
415 return le16_to_cpu(__raw_readw((u32)port));
416#else
417 return (unsigned int)__ixp4xx_readw(addr);
418#endif
419}
420
421static inline void
422__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
423{
424 unsigned long port = (unsigned long __force)addr;
425 if (__is_io_address(port))
426 __ixp4xx_insw(port & PIO_MASK, vaddr, count);
427 else
428#ifndef CONFIG_IXP4XX_INDIRECT_PCI
429 __raw_readsw(addr, vaddr, count);
430#else
431 __ixp4xx_readsw(addr, vaddr, count);
432#endif
433}
434
435static inline unsigned int
436__ixp4xx_ioread32(const void __iomem *addr)
437{
438 unsigned long port = (unsigned long __force)addr;
439 if (__is_io_address(port))
440 return (unsigned int)__ixp4xx_inl(port & PIO_MASK);
441 else {
442#ifndef CONFIG_IXP4XX_INDIRECT_PCI
443 return le32_to_cpu((__force __le32)__raw_readl(addr));
444#else
445 return (unsigned int)__ixp4xx_readl(addr);
446#endif
447 }
448}
449
450static inline void
451__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
452{
453 unsigned long port = (unsigned long __force)addr;
454 if (__is_io_address(port))
455 __ixp4xx_insl(port & PIO_MASK, vaddr, count);
456 else
457#ifndef CONFIG_IXP4XX_INDIRECT_PCI
458 __raw_readsl(addr, vaddr, count);
459#else
460 __ixp4xx_readsl(addr, vaddr, count);
461#endif
462}
463
464static inline void
465__ixp4xx_iowrite8(u8 value, void __iomem *addr)
466{
467 unsigned long port = (unsigned long __force)addr;
468 if (__is_io_address(port))
469 __ixp4xx_outb(value, port & PIO_MASK);
470 else
471#ifndef CONFIG_IXP4XX_INDIRECT_PCI
472 __raw_writeb(value, port);
473#else
474 __ixp4xx_writeb(value, addr);
475#endif
476}
477
478static inline void
479__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
480{
481 unsigned long port = (unsigned long __force)addr;
482 if (__is_io_address(port))
483 __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
484 else
485#ifndef CONFIG_IXP4XX_INDIRECT_PCI
486 __raw_writesb(addr, vaddr, count);
487#else
488 __ixp4xx_writesb(addr, vaddr, count);
489#endif
490}
491
492static inline void
493__ixp4xx_iowrite16(u16 value, void __iomem *addr)
494{
495 unsigned long port = (unsigned long __force)addr;
496 if (__is_io_address(port))
497 __ixp4xx_outw(value, port & PIO_MASK);
498 else
499#ifndef CONFIG_IXP4XX_INDIRECT_PCI
500 __raw_writew(cpu_to_le16(value), addr);
501#else
502 __ixp4xx_writew(value, addr);
503#endif
504}
505
506static inline void
507__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
508{
509 unsigned long port = (unsigned long __force)addr;
510 if (__is_io_address(port))
511 __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
512 else
513#ifndef CONFIG_IXP4XX_INDIRECT_PCI
514 __raw_writesw(addr, vaddr, count);
515#else
516 __ixp4xx_writesw(addr, vaddr, count);
517#endif
518}
519
520static inline void
521__ixp4xx_iowrite32(u32 value, void __iomem *addr)
522{
523 unsigned long port = (unsigned long __force)addr;
524 if (__is_io_address(port))
525 __ixp4xx_outl(value, port & PIO_MASK);
526 else
527#ifndef CONFIG_IXP4XX_INDIRECT_PCI
528 __raw_writel((u32 __force)cpu_to_le32(value), addr);
529#else
530 __ixp4xx_writel(value, addr);
531#endif
532}
533
534static inline void
535__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
536{
537 unsigned long port = (unsigned long __force)addr;
538 if (__is_io_address(port))
539 __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
540 else
541#ifndef CONFIG_IXP4XX_INDIRECT_PCI
542 __raw_writesl(addr, vaddr, count);
543#else
544 __ixp4xx_writesl(addr, vaddr, count);
545#endif
546}
547
548#define ioread8(p) __ixp4xx_ioread8(p)
549#define ioread16(p) __ixp4xx_ioread16(p)
550#define ioread32(p) __ixp4xx_ioread32(p)
551
552#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
553#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
554#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
555
556#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
557#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
558#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
559
560#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
561#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
562#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
563
564#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
565#define ioport_unmap(addr)
566#endif // !CONFIG_PCI
567
568#endif // __ASM_ARM_ARCH_IO_H
569
diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h
new file mode 100644
index 000000000000..f4d74de1566a
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/irqs.h
@@ -0,0 +1,138 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/irqs.h
3 *
4 * IRQ definitions for IXP4XX based systems
5 *
6 * Copyright (C) 2002 Intel Corporation.
7 * Copyright (C) 2003 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#ifndef _ARCH_IXP4XX_IRQS_H_
16#define _ARCH_IXP4XX_IRQS_H_
17
18
19#define IRQ_IXP4XX_NPEA 0
20#define IRQ_IXP4XX_NPEB 1
21#define IRQ_IXP4XX_NPEC 2
22#define IRQ_IXP4XX_QM1 3
23#define IRQ_IXP4XX_QM2 4
24#define IRQ_IXP4XX_TIMER1 5
25#define IRQ_IXP4XX_GPIO0 6
26#define IRQ_IXP4XX_GPIO1 7
27#define IRQ_IXP4XX_PCI_INT 8
28#define IRQ_IXP4XX_PCI_DMA1 9
29#define IRQ_IXP4XX_PCI_DMA2 10
30#define IRQ_IXP4XX_TIMER2 11
31#define IRQ_IXP4XX_USB 12
32#define IRQ_IXP4XX_UART2 13
33#define IRQ_IXP4XX_TIMESTAMP 14
34#define IRQ_IXP4XX_UART1 15
35#define IRQ_IXP4XX_WDOG 16
36#define IRQ_IXP4XX_AHB_PMU 17
37#define IRQ_IXP4XX_XSCALE_PMU 18
38#define IRQ_IXP4XX_GPIO2 19
39#define IRQ_IXP4XX_GPIO3 20
40#define IRQ_IXP4XX_GPIO4 21
41#define IRQ_IXP4XX_GPIO5 22
42#define IRQ_IXP4XX_GPIO6 23
43#define IRQ_IXP4XX_GPIO7 24
44#define IRQ_IXP4XX_GPIO8 25
45#define IRQ_IXP4XX_GPIO9 26
46#define IRQ_IXP4XX_GPIO10 27
47#define IRQ_IXP4XX_GPIO11 28
48#define IRQ_IXP4XX_GPIO12 29
49#define IRQ_IXP4XX_SW_INT1 30
50#define IRQ_IXP4XX_SW_INT2 31
51#define IRQ_IXP4XX_USB_HOST 32
52#define IRQ_IXP4XX_I2C 33
53#define IRQ_IXP4XX_SSP 34
54#define IRQ_IXP4XX_TSYNC 35
55#define IRQ_IXP4XX_EAU_DONE 36
56#define IRQ_IXP4XX_SHA_DONE 37
57#define IRQ_IXP4XX_SWCP_PE 58
58#define IRQ_IXP4XX_QM_PE 60
59#define IRQ_IXP4XX_MCU_ECC 61
60#define IRQ_IXP4XX_EXP_PE 62
61
62/*
63 * Only first 32 sources are valid if running on IXP42x systems
64 */
65#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
66#define NR_IRQS 64
67#else
68#define NR_IRQS 32
69#endif
70
71#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
72
73/*
74 * IXDP425 board IRQs
75 */
76#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11
77#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10
78#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9
79#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8
80
81/*
82 * Gateworks Avila board IRQs
83 */
84#define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11
85#define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10
86#define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9
87#define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8
88
89
90/*
91 * PrPMC1100 Board IRQs
92 */
93#define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11
94#define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10
95#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9
96#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8
97
98/*
99 * ADI Coyote Board IRQs
100 */
101#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6
102#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
103#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
104
105/*
106 * NSLU2 board IRQs
107 */
108#define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11
109#define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10
110#define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9
111
112/*
113 * NAS100D board IRQs
114 */
115#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11
116#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10
117#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9
118#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8
119#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7
120
121/*
122 * D-Link DSM-G600 RevA board IRQs
123 */
124#define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11
125#define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10
126#define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9
127#define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8
128#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
129#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
130
131/*
132 * Freecom FSG-3 Board IRQs
133 */
134#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6
135#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7
136#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5
137
138#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixdp425.h b/arch/arm/mach-ixp4xx/include/mach/ixdp425.h
new file mode 100644
index 000000000000..2cafe65ebfee
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixdp425.h
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/ixdp425.h
3 *
4 * IXDP425 platform specific definitions
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <mach/hardware.h>"
17#endif
18
19#define IXDP425_SDA_PIN 7
20#define IXDP425_SCL_PIN 6
21
22/*
23 * IXDP425 PCI IRQs
24 */
25#define IXDP425_PCI_MAX_DEV 4
26#define IXDP425_PCI_IRQ_LINES 4
27
28
29/* PCI controller GPIO to IRQ pin mappings */
30#define IXDP425_PCI_INTA_PIN 11
31#define IXDP425_PCI_INTB_PIN 10
32#define IXDP425_PCI_INTC_PIN 9
33#define IXDP425_PCI_INTD_PIN 8
34
35/* NAND Flash pins */
36#define IXDP425_NAND_NCE_PIN 12
37
38#define IXDP425_NAND_CMD_BYTE 0x01
39#define IXDP425_NAND_ADDR_BYTE 0x02
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
new file mode 100644
index 000000000000..ad9c888dd850
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -0,0 +1,638 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
3 *
4 * Register definitions for IXP4xx chipset. This file contains
5 * register location and bit definitions only. Platform specific
6 * definitions and helper function declarations are in platform.h
7 * and machine-name.h.
8 *
9 * Copyright (C) 2002 Intel Corporation.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#ifndef _ASM_ARM_IXP4XX_H_
19#define _ASM_ARM_IXP4XX_H_
20
21/*
22 * IXP4xx Linux Memory Map:
23 *
24 * Phy Size Virt Description
25 * =========================================================================
26 *
27 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
28 *
29 * 0x48000000 0x04000000 ioremap'd PCI Memory Space
30 *
31 * 0x50000000 0x10000000 ioremap'd EXP BUS
32 *
33 * 0x6000000 0x00004000 ioremap'd QMgr
34 *
35 * 0xC0000000 0x00001000 0xffbff000 PCI CFG
36 *
37 * 0xC4000000 0x00001000 0xffbfe000 EXP CFG
38 *
39 * 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals
40 */
41
42/*
43 * Queue Manager
44 */
45#define IXP4XX_QMGR_BASE_PHYS (0x60000000)
46#define IXP4XX_QMGR_REGION_SIZE (0x00004000)
47
48/*
49 * Expansion BUS Configuration registers
50 */
51#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
52#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000)
53#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
54
55/*
56 * PCI Config registers
57 */
58#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
59#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000)
60#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
61
62/*
63 * Peripheral space
64 */
65#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
66#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000)
67#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
68
69/*
70 * Debug UART
71 *
72 * This is basically a remap of UART1 into a region that is section
73 * aligned so that it * can be used with the low-level debug code.
74 */
75#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000)
76#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000)
77#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
78
79#define IXP4XX_EXP_CS0_OFFSET 0x00
80#define IXP4XX_EXP_CS1_OFFSET 0x04
81#define IXP4XX_EXP_CS2_OFFSET 0x08
82#define IXP4XX_EXP_CS3_OFFSET 0x0C
83#define IXP4XX_EXP_CS4_OFFSET 0x10
84#define IXP4XX_EXP_CS5_OFFSET 0x14
85#define IXP4XX_EXP_CS6_OFFSET 0x18
86#define IXP4XX_EXP_CS7_OFFSET 0x1C
87#define IXP4XX_EXP_CFG0_OFFSET 0x20
88#define IXP4XX_EXP_CFG1_OFFSET 0x24
89#define IXP4XX_EXP_CFG2_OFFSET 0x28
90#define IXP4XX_EXP_CFG3_OFFSET 0x2C
91
92/*
93 * Expansion Bus Controller registers.
94 */
95#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
96
97#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
98#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
99#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
100#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
101#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
102#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
103#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
104#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
105
106#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
107#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
108#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
109#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
110
111
112/*
113 * Peripheral Space Register Region Base Addresses
114 */
115#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
116#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
117#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
118#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
119#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
120#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
121#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
122#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
123#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
124#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
125#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
126#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
127/* ixp46X only */
128#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
129#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
130#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
131#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
132#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
133#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
134#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
135
136
137#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
138#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
139#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
140#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
141#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
142#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
143#define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
144#define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
145#define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
146#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
147#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
148#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
149/* ixp46X only */
150#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
151#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
152#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
153#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
154#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
155#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
156#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
157
158/*
159 * Constants to make it easy to access Interrupt Controller registers
160 */
161#define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */
162#define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */
163#define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
164#define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */
165#define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */
166#define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */
167#define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
168#define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
169
170/*
171 * IXP465-only
172 */
173#define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */
174#define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */
175#define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */
176#define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */
177#define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */
178#define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */
179
180
181/*
182 * Interrupt Controller Register Definitions.
183 */
184
185#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
186
187#define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
188#define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
189#define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
190#define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
191#define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
192#define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
193#define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
194#define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
195#define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
196#define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
197#define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
198#define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
199#define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
200#define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
201
202/*
203 * Constants to make it easy to access GPIO registers
204 */
205#define IXP4XX_GPIO_GPOUTR_OFFSET 0x00
206#define IXP4XX_GPIO_GPOER_OFFSET 0x04
207#define IXP4XX_GPIO_GPINR_OFFSET 0x08
208#define IXP4XX_GPIO_GPISR_OFFSET 0x0C
209#define IXP4XX_GPIO_GPIT1R_OFFSET 0x10
210#define IXP4XX_GPIO_GPIT2R_OFFSET 0x14
211#define IXP4XX_GPIO_GPCLKR_OFFSET 0x18
212#define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C
213
214/*
215 * GPIO Register Definitions.
216 * [Only perform 32bit reads/writes]
217 */
218#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
219
220#define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
221#define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
222#define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
223#define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
224#define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
225#define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
226#define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
227#define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
228
229/*
230 * GPIO register bit definitions
231 */
232
233/* Interrupt styles
234 */
235#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
236#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
237#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
238#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
239#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
240
241/*
242 * Mask used to clear interrupt styles
243 */
244#define IXP4XX_GPIO_STYLE_CLEAR 0x7
245#define IXP4XX_GPIO_STYLE_SIZE 3
246
247/*
248 * Constants to make it easy to access Timer Control/Status registers
249 */
250#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
251#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
252#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
253#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
254#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
255#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
256#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
257#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
258#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
259
260/*
261 * Operating System Timer Register Definitions.
262 */
263
264#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
265
266#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
267#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
268#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
269#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
270#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
271#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
272#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
273#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
274#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
275
276/*
277 * Timer register values and bit definitions
278 */
279#define IXP4XX_OST_ENABLE 0x00000001
280#define IXP4XX_OST_ONE_SHOT 0x00000002
281/* Low order bits of reload value ignored */
282#define IXP4XX_OST_RELOAD_MASK 0x00000003
283#define IXP4XX_OST_DISABLED 0x00000000
284#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
285#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
286#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
287#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
288#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
289
290#define IXP4XX_WDT_KEY 0x0000482E
291
292#define IXP4XX_WDT_RESET_ENABLE 0x00000001
293#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
294#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
295
296
297/*
298 * Constants to make it easy to access PCI Control/Status registers
299 */
300#define PCI_NP_AD_OFFSET 0x00
301#define PCI_NP_CBE_OFFSET 0x04
302#define PCI_NP_WDATA_OFFSET 0x08
303#define PCI_NP_RDATA_OFFSET 0x0c
304#define PCI_CRP_AD_CBE_OFFSET 0x10
305#define PCI_CRP_WDATA_OFFSET 0x14
306#define PCI_CRP_RDATA_OFFSET 0x18
307#define PCI_CSR_OFFSET 0x1c
308#define PCI_ISR_OFFSET 0x20
309#define PCI_INTEN_OFFSET 0x24
310#define PCI_DMACTRL_OFFSET 0x28
311#define PCI_AHBMEMBASE_OFFSET 0x2c
312#define PCI_AHBIOBASE_OFFSET 0x30
313#define PCI_PCIMEMBASE_OFFSET 0x34
314#define PCI_AHBDOORBELL_OFFSET 0x38
315#define PCI_PCIDOORBELL_OFFSET 0x3C
316#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
317#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
318#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
319#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
320#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
321#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
322
323/*
324 * PCI Control/Status Registers
325 */
326#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
327
328#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
329#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
330#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
331#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
332#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
333#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
334#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
335#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
336#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
337#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
338#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
339#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
340#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
341#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
342#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
343#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
344#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
345#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
346#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
347#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
348#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
349#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
350
351/*
352 * PCI register values and bit definitions
353 */
354
355/* CSR bit definitions */
356#define PCI_CSR_HOST 0x00000001
357#define PCI_CSR_ARBEN 0x00000002
358#define PCI_CSR_ADS 0x00000004
359#define PCI_CSR_PDS 0x00000008
360#define PCI_CSR_ABE 0x00000010
361#define PCI_CSR_DBT 0x00000020
362#define PCI_CSR_ASE 0x00000100
363#define PCI_CSR_IC 0x00008000
364
365/* ISR (Interrupt status) Register bit definitions */
366#define PCI_ISR_PSE 0x00000001
367#define PCI_ISR_PFE 0x00000002
368#define PCI_ISR_PPE 0x00000004
369#define PCI_ISR_AHBE 0x00000008
370#define PCI_ISR_APDC 0x00000010
371#define PCI_ISR_PADC 0x00000020
372#define PCI_ISR_ADB 0x00000040
373#define PCI_ISR_PDB 0x00000080
374
375/* INTEN (Interrupt Enable) Register bit definitions */
376#define PCI_INTEN_PSE 0x00000001
377#define PCI_INTEN_PFE 0x00000002
378#define PCI_INTEN_PPE 0x00000004
379#define PCI_INTEN_AHBE 0x00000008
380#define PCI_INTEN_APDC 0x00000010
381#define PCI_INTEN_PADC 0x00000020
382#define PCI_INTEN_ADB 0x00000040
383#define PCI_INTEN_PDB 0x00000080
384
385/*
386 * Shift value for byte enable on NP cmd/byte enable register
387 */
388#define IXP4XX_PCI_NP_CBE_BESL 4
389
390/*
391 * PCI commands supported by NP access unit
392 */
393#define NP_CMD_IOREAD 0x2
394#define NP_CMD_IOWRITE 0x3
395#define NP_CMD_CONFIGREAD 0xa
396#define NP_CMD_CONFIGWRITE 0xb
397#define NP_CMD_MEMREAD 0x6
398#define NP_CMD_MEMWRITE 0x7
399
400/*
401 * Constants for CRP access into local config space
402 */
403#define CRP_AD_CBE_BESL 20
404#define CRP_AD_CBE_WRITE 0x00010000
405
406
407/*
408 * USB Device Controller
409 *
410 * These are used by the USB gadget driver, so they don't follow the
411 * IXP4XX_ naming convetions.
412 *
413 */
414# define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
415
416/* UDC Undocumented - Reserved1 */
417#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
418/* UDC Undocumented - Reserved2 */
419#define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
420/* UDC Undocumented - Reserved3 */
421#define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
422/* UDC Control Register */
423#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
424/* UDC Endpoint 0 Control/Status Register */
425#define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
426/* UDC Endpoint 1 (IN) Control/Status Register */
427#define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
428/* UDC Endpoint 2 (OUT) Control/Status Register */
429#define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
430/* UDC Endpoint 3 (IN) Control/Status Register */
431#define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
432/* UDC Endpoint 4 (OUT) Control/Status Register */
433#define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
434/* UDC Endpoint 5 (Interrupt) Control/Status Register */
435#define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
436/* UDC Endpoint 6 (IN) Control/Status Register */
437#define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
438/* UDC Endpoint 7 (OUT) Control/Status Register */
439#define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
440/* UDC Endpoint 8 (IN) Control/Status Register */
441#define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
442/* UDC Endpoint 9 (OUT) Control/Status Register */
443#define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
444/* UDC Endpoint 10 (Interrupt) Control/Status Register */
445#define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
446/* UDC Endpoint 11 (IN) Control/Status Register */
447#define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
448/* UDC Endpoint 12 (OUT) Control/Status Register */
449#define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
450/* UDC Endpoint 13 (IN) Control/Status Register */
451#define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
452/* UDC Endpoint 14 (OUT) Control/Status Register */
453#define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
454/* UDC Endpoint 15 (Interrupt) Control/Status Register */
455#define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
456/* UDC Frame Number Register High */
457#define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
458/* UDC Frame Number Register Low */
459#define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
460/* UDC Byte Count Reg 2 */
461#define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
462/* UDC Byte Count Reg 4 */
463#define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
464/* UDC Byte Count Reg 7 */
465#define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
466/* UDC Byte Count Reg 9 */
467#define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
468/* UDC Byte Count Reg 12 */
469#define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
470/* UDC Byte Count Reg 14 */
471#define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
472/* UDC Endpoint 0 Data Register */
473#define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
474/* UDC Endpoint 1 Data Register */
475#define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
476/* UDC Endpoint 2 Data Register */
477#define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
478/* UDC Endpoint 3 Data Register */
479#define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
480/* UDC Endpoint 4 Data Register */
481#define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
482/* UDC Endpoint 5 Data Register */
483#define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
484/* UDC Endpoint 6 Data Register */
485#define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
486/* UDC Endpoint 7 Data Register */
487#define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
488/* UDC Endpoint 8 Data Register */
489#define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
490/* UDC Endpoint 9 Data Register */
491#define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
492/* UDC Endpoint 10 Data Register */
493#define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
494/* UDC Endpoint 11 Data Register */
495#define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
496/* UDC Endpoint 12 Data Register */
497#define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
498/* UDC Endpoint 13 Data Register */
499#define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
500/* UDC Endpoint 14 Data Register */
501#define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
502/* UDC Endpoint 15 Data Register */
503#define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
504/* UDC Interrupt Control Register 0 */
505#define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
506/* UDC Interrupt Control Register 1 */
507#define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
508/* UDC Status Interrupt Register 0 */
509#define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
510/* UDC Status Interrupt Register 1 */
511#define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
512
513#define UDCCR_UDE (1 << 0) /* UDC enable */
514#define UDCCR_UDA (1 << 1) /* UDC active */
515#define UDCCR_RSM (1 << 2) /* Device resume */
516#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
517#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
518#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
519#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
520#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
521
522#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
523#define UDCCS0_IPR (1 << 1) /* IN packet ready */
524#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
525#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
526#define UDCCS0_SST (1 << 4) /* Sent stall */
527#define UDCCS0_FST (1 << 5) /* Force stall */
528#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
529#define UDCCS0_SA (1 << 7) /* Setup active */
530
531#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
532#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
533#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
534#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
535#define UDCCS_BI_SST (1 << 4) /* Sent stall */
536#define UDCCS_BI_FST (1 << 5) /* Force stall */
537#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
538
539#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
540#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
541#define UDCCS_BO_DME (1 << 3) /* DMA enable */
542#define UDCCS_BO_SST (1 << 4) /* Sent stall */
543#define UDCCS_BO_FST (1 << 5) /* Force stall */
544#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
545#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
546
547#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
548#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
549#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
550#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
551#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
552
553#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
554#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
555#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
556#define UDCCS_IO_DME (1 << 3) /* DMA enable */
557#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
558#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
559
560#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
561#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
562#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
563#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
564#define UDCCS_INT_SST (1 << 4) /* Sent stall */
565#define UDCCS_INT_FST (1 << 5) /* Force stall */
566#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
567
568#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
569#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
570#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
571#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
572#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
573#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
574#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
575#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
576
577#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
578#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
579#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
580#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
581#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
582#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
583#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
584#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
585
586#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
587#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
588#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
589#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
590#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
591#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
592#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
593#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
594
595#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
596#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
597#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
598#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
599#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
600#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
601#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
602#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
603
604#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
605
606/* "fuse" bits of IXP_EXP_CFG2 */
607#define IXP4XX_FEATURE_RCOMP (1 << 0)
608#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
609#define IXP4XX_FEATURE_HASH (1 << 2)
610#define IXP4XX_FEATURE_AES (1 << 3)
611#define IXP4XX_FEATURE_DES (1 << 4)
612#define IXP4XX_FEATURE_HDLC (1 << 5)
613#define IXP4XX_FEATURE_AAL (1 << 6)
614#define IXP4XX_FEATURE_HSS (1 << 7)
615#define IXP4XX_FEATURE_UTOPIA (1 << 8)
616#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
617#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
618#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
619#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
620#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
621#define IXP4XX_FEATURE_PCI (1 << 14)
622#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
623#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
624#define IXP4XX_FEATURE_USB_HOST (1 << 18)
625#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
626#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
627#define IXP4XX_FEATURE_RSA (1 << 21)
628#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
629#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
630
631#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
632 IXP4XX_FEATURE_USB_HOST | \
633 IXP4XX_FEATURE_NPEA_ETH | \
634 IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
635 IXP4XX_FEATURE_RSA | \
636 IXP4XX_FEATURE_XSCALE_MAX_FREQ)
637
638#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
new file mode 100644
index 000000000000..c4d2830ac987
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/memory.h
3 *
4 * Copyright (c) 2001-2004 MontaVista Software, Inc.
5 */
6
7#ifndef __ASM_ARCH_MEMORY_H
8#define __ASM_ARCH_MEMORY_H
9
10#include <asm/sizes.h>
11
12/*
13 * Physical DRAM offset.
14 */
15#define PHYS_OFFSET UL(0x00000000)
16
17#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
18
19void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
20
21#define arch_adjust_zones(node, size, holes) \
22 ixp4xx_adjust_zones(node, size, holes)
23
24#define ISA_DMA_THRESHOLD (SZ_64M - 1)
25
26#endif
27
28/*
29 * Virtual view <-> DMA view memory address translations
30 * virt_to_bus: Used to translate the virtual address to an
31 * address suitable to be passed to set_dma_addr
32 * bus_to_virt: Used to convert an address for DMA operations
33 * to an address that the kernel can use.
34 *
35 * These are dummies for now.
36 */
37#define __virt_to_bus(x) __virt_to_phys(x)
38#define __bus_to_virt(x) __phys_to_virt(x)
39
40#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/nas100d.h b/arch/arm/mach-ixp4xx/include/mach/nas100d.h
new file mode 100644
index 000000000000..3771d62a9748
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/nas100d.h
@@ -0,0 +1,52 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/nas100d.h
3 *
4 * NAS100D platform specific definitions
5 *
6 * Copyright (c) 2005 Tower Technologies
7 *
8 * Author: Alessandro Zummo <a.zummo@towertech.it>
9 *
10 * based on ixdp425.h:
11 * Copyright 2004 (c) MontaVista, Software, Inc.
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <mach/hardware.h>"
20#endif
21
22#define NAS100D_SDA_PIN 5
23#define NAS100D_SCL_PIN 6
24
25/*
26 * NAS100D PCI IRQs
27 */
28#define NAS100D_PCI_MAX_DEV 3
29#define NAS100D_PCI_IRQ_LINES 3
30
31
32/* PCI controller GPIO to IRQ pin mappings */
33#define NAS100D_PCI_INTA_PIN 11
34#define NAS100D_PCI_INTB_PIN 10
35#define NAS100D_PCI_INTC_PIN 9
36#define NAS100D_PCI_INTD_PIN 8
37#define NAS100D_PCI_INTE_PIN 7
38
39/* Buttons */
40
41#define NAS100D_PB_GPIO 14 /* power button */
42#define NAS100D_RB_GPIO 4 /* reset button */
43
44/* Power control */
45
46#define NAS100D_PO_GPIO 12 /* power off */
47
48/* LEDs */
49
50#define NAS100D_LED_WLAN_GPIO 0
51#define NAS100D_LED_DISK_GPIO 3
52#define NAS100D_LED_PWR_GPIO 15
diff --git a/arch/arm/mach-ixp4xx/include/mach/npe.h b/arch/arm/mach-ixp4xx/include/mach/npe.h
new file mode 100644
index 000000000000..37d0511689dc
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/npe.h
@@ -0,0 +1,39 @@
1#ifndef __IXP4XX_NPE_H
2#define __IXP4XX_NPE_H
3
4#include <linux/kernel.h>
5
6extern const char *npe_names[];
7
8struct npe_regs {
9 u32 exec_addr, exec_data, exec_status_cmd, exec_count;
10 u32 action_points[4];
11 u32 watchpoint_fifo, watch_count;
12 u32 profile_count;
13 u32 messaging_status, messaging_control;
14 u32 mailbox_status, /*messaging_*/ in_out_fifo;
15};
16
17struct npe {
18 struct resource *mem_res;
19 struct npe_regs __iomem *regs;
20 u32 regs_phys;
21 int id;
22 int valid;
23};
24
25
26static inline const char *npe_name(struct npe *npe)
27{
28 return npe_names[npe->id];
29}
30
31int npe_running(struct npe *npe);
32int npe_send_message(struct npe *npe, const void *msg, const char *what);
33int npe_recv_message(struct npe *npe, void *msg, const char *what);
34int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
35int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
36struct npe *npe_request(int id);
37void npe_release(struct npe *npe);
38
39#endif /* __IXP4XX_NPE_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/nslu2.h b/arch/arm/mach-ixp4xx/include/mach/nslu2.h
new file mode 100644
index 000000000000..85d00adbfb92
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/nslu2.h
@@ -0,0 +1,55 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/nslu2.h
3 *
4 * NSLU2 platform specific definitions
5 *
6 * Author: Mark Rakes <mrakes AT mac.com>
7 * Maintainers: http://www.nslu2-linux.org
8 *
9 * based on ixdp425.h:
10 * Copyright 2004 (c) MontaVista, Software, Inc.
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#ifndef __ASM_ARCH_HARDWARE_H__
18#error "Do not include this directly, instead #include <mach/hardware.h>"
19#endif
20
21#define NSLU2_SDA_PIN 7
22#define NSLU2_SCL_PIN 6
23
24/*
25 * NSLU2 PCI IRQs
26 */
27#define NSLU2_PCI_MAX_DEV 3
28#define NSLU2_PCI_IRQ_LINES 3
29
30
31/* PCI controller GPIO to IRQ pin mappings */
32#define NSLU2_PCI_INTA_PIN 11
33#define NSLU2_PCI_INTB_PIN 10
34#define NSLU2_PCI_INTC_PIN 9
35#define NSLU2_PCI_INTD_PIN 8
36
37/* NSLU2 Timer */
38#define NSLU2_FREQ 66000000
39
40/* Buttons */
41
42#define NSLU2_PB_GPIO 5 /* power button */
43#define NSLU2_PO_GPIO 8 /* power off */
44#define NSLU2_RB_GPIO 12 /* reset button */
45
46/* Buzzer */
47
48#define NSLU2_GPIO_BUZZ 4
49
50/* LEDs */
51
52#define NSLU2_LED_RED_GPIO 0
53#define NSLU2_LED_GRN_GPIO 1
54#define NSLU2_LED_DISK1_GPIO 3
55#define NSLU2_LED_DISK2_GPIO 2
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
new file mode 100644
index 000000000000..e824c02c825a
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -0,0 +1,173 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/platform.h
3 *
4 * Constants and functions that are useful to IXP4xx platform-specific code
5 * and device drivers.
6 *
7 * Copyright (C) 2004 MontaVista Software, Inc.
8 */
9
10#ifndef __ASM_ARCH_HARDWARE_H__
11#error "Do not include this directly, instead #include <mach/hardware.h>"
12#endif
13
14#ifndef __ASSEMBLY__
15
16#include <asm/types.h>
17
18#ifndef __ARMEB__
19#define REG_OFFSET 0
20#else
21#define REG_OFFSET 3
22#endif
23
24/*
25 * Expansion bus memory regions
26 */
27#define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000)
28
29/*
30 * The expansion bus on the IXP4xx can be configured for either 16 or
31 * 32MB windows and the CS offset for each region changes based on the
32 * current configuration. This means that we cannot simply hardcode
33 * each offset. ixp4xx_sys_init() looks at the expansion bus configuration
34 * as setup by the bootloader to determine our window size.
35 */
36extern unsigned long ixp4xx_exp_bus_size;
37
38#define IXP4XX_EXP_BUS_BASE(region)\
39 (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size))
40
41#define IXP4XX_EXP_BUS_END(region)\
42 (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1)
43
44/* Those macros can be used to adjust timing and configure
45 * other features for each region.
46 */
47
48#define IXP4XX_EXP_BUS_RECOVERY_T(x) (((x) & 0x0f) << 16)
49#define IXP4XX_EXP_BUS_HOLD_T(x) (((x) & 0x03) << 20)
50#define IXP4XX_EXP_BUS_STROBE_T(x) (((x) & 0x0f) << 22)
51#define IXP4XX_EXP_BUS_SETUP_T(x) (((x) & 0x03) << 26)
52#define IXP4XX_EXP_BUS_ADDR_T(x) (((x) & 0x03) << 28)
53#define IXP4XX_EXP_BUS_SIZE(x) (((x) & 0x0f) << 10)
54#define IXP4XX_EXP_BUS_CYCLES(x) (((x) & 0x03) << 14)
55
56#define IXP4XX_EXP_BUS_CS_EN (1L << 31)
57#define IXP4XX_EXP_BUS_BYTE_RD16 (1L << 6)
58#define IXP4XX_EXP_BUS_HRDY_POL (1L << 5)
59#define IXP4XX_EXP_BUS_MUX_EN (1L << 4)
60#define IXP4XX_EXP_BUS_SPLT_EN (1L << 3)
61#define IXP4XX_EXP_BUS_WR_EN (1L << 1)
62#define IXP4XX_EXP_BUS_BYTE_EN (1L << 0)
63
64#define IXP4XX_EXP_BUS_CYCLES_INTEL 0x00
65#define IXP4XX_EXP_BUS_CYCLES_MOTOROLA 0x01
66#define IXP4XX_EXP_BUS_CYCLES_HPI 0x02
67
68#define IXP4XX_FLASH_WRITABLE (0x2)
69#define IXP4XX_FLASH_DEFAULT (0xbcd23c40)
70#define IXP4XX_FLASH_WRITE (0xbcd23c42)
71
72/*
73 * Clock Speed Definitions.
74 */
75#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
76#define IXP4XX_UART_XTAL 14745600
77
78/*
79 * This structure provide a means for the board setup code
80 * to give information to th pata_ixp4xx driver. It is
81 * passed as platform_data.
82 */
83struct ixp4xx_pata_data {
84 volatile u32 *cs0_cfg;
85 volatile u32 *cs1_cfg;
86 unsigned long cs0_bits;
87 unsigned long cs1_bits;
88 void __iomem *cs0;
89 void __iomem *cs1;
90};
91
92struct sys_timer;
93
94#define IXP4XX_ETH_NPEA 0x00
95#define IXP4XX_ETH_NPEB 0x10
96#define IXP4XX_ETH_NPEC 0x20
97
98/* Information about built-in Ethernet MAC interfaces */
99struct eth_plat_info {
100 u8 phy; /* MII PHY ID, 0 - 31 */
101 u8 rxq; /* configurable, currently 0 - 31 only */
102 u8 txreadyq;
103 u8 hwaddr[6];
104};
105
106/* Information about built-in HSS (synchronous serial) interfaces */
107struct hss_plat_info {
108 int (*set_clock)(int port, unsigned int clock_type);
109 int (*open)(int port, void *pdev,
110 void (*set_carrier_cb)(void *pdev, int carrier));
111 void (*close)(int port, void *pdev);
112 u8 txreadyq;
113};
114
115/*
116 * Frequency of clock used for primary clocksource
117 */
118extern unsigned long ixp4xx_timer_freq;
119
120/*
121 * Functions used by platform-level setup code
122 */
123extern void ixp4xx_map_io(void);
124extern void ixp4xx_init_irq(void);
125extern void ixp4xx_sys_init(void);
126extern void ixp4xx_timer_init(void);
127extern struct sys_timer ixp4xx_timer;
128extern void ixp4xx_pci_preinit(void);
129struct pci_sys_data;
130extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
131extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
132
133/*
134 * GPIO-functions
135 */
136/*
137 * The following converted to the real HW bits the gpio_line_config
138 */
139/* GPIO pin types */
140#define IXP4XX_GPIO_OUT 0x1
141#define IXP4XX_GPIO_IN 0x2
142
143/* GPIO signal types */
144#define IXP4XX_GPIO_LOW 0
145#define IXP4XX_GPIO_HIGH 1
146
147/* GPIO Clocks */
148#define IXP4XX_GPIO_CLK_0 14
149#define IXP4XX_GPIO_CLK_1 15
150
151static inline void gpio_line_config(u8 line, u32 direction)
152{
153 if (direction == IXP4XX_GPIO_IN)
154 *IXP4XX_GPIO_GPOER |= (1 << line);
155 else
156 *IXP4XX_GPIO_GPOER &= ~(1 << line);
157}
158
159static inline void gpio_line_get(u8 line, int *value)
160{
161 *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
162}
163
164static inline void gpio_line_set(u8 line, int value)
165{
166 if (value == IXP4XX_GPIO_HIGH)
167 *IXP4XX_GPIO_GPOUTR |= (1 << line);
168 else if (value == IXP4XX_GPIO_LOW)
169 *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
170}
171
172#endif // __ASSEMBLY__
173
diff --git a/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h b/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
new file mode 100644
index 000000000000..17274a2e3dec
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
@@ -0,0 +1,33 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/prpmc1100.h
3 *
4 * Motorolla PrPMC1100 platform specific definitions
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <mach/hardware.h>"
17#endif
18
19#define PRPMC1100_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
20#define PRPMC1100_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
21
22#define PRPMC1100_PCI_MIN_DEVID 10
23#define PRPMC1100_PCI_MAX_DEVID 16
24#define PRPMC1100_PCI_IRQ_LINES 4
25
26
27/* PCI controller GPIO to IRQ pin mappings */
28#define PRPMC1100_PCI_INTA_PIN 11
29#define PRPMC1100_PCI_INTB_PIN 10
30#define PRPMC1100_PCI_INTC_PIN 9
31#define PRPMC1100_PCI_INTD_PIN 8
32
33
diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
new file mode 100644
index 000000000000..1e52b95cede5
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
@@ -0,0 +1,126 @@
1/*
2 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9#ifndef IXP4XX_QMGR_H
10#define IXP4XX_QMGR_H
11
12#include <linux/io.h>
13#include <linux/kernel.h>
14
15#define HALF_QUEUES 32
16#define QUEUES 64 /* only 32 lower queues currently supported */
17#define MAX_QUEUE_LENGTH 4 /* in dwords */
18
19#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
20#define QUEUE_STAT1_NEARLY_EMPTY 2
21#define QUEUE_STAT1_NEARLY_FULL 4
22#define QUEUE_STAT1_FULL 8
23#define QUEUE_STAT2_UNDERFLOW 1
24#define QUEUE_STAT2_OVERFLOW 2
25
26#define QUEUE_WATERMARK_0_ENTRIES 0
27#define QUEUE_WATERMARK_1_ENTRY 1
28#define QUEUE_WATERMARK_2_ENTRIES 2
29#define QUEUE_WATERMARK_4_ENTRIES 3
30#define QUEUE_WATERMARK_8_ENTRIES 4
31#define QUEUE_WATERMARK_16_ENTRIES 5
32#define QUEUE_WATERMARK_32_ENTRIES 6
33#define QUEUE_WATERMARK_64_ENTRIES 7
34
35/* queue interrupt request conditions */
36#define QUEUE_IRQ_SRC_EMPTY 0
37#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
38#define QUEUE_IRQ_SRC_NEARLY_FULL 2
39#define QUEUE_IRQ_SRC_FULL 3
40#define QUEUE_IRQ_SRC_NOT_EMPTY 4
41#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
42#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
43#define QUEUE_IRQ_SRC_NOT_FULL 7
44
45struct qmgr_regs {
46 u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
47 u32 stat1[4]; /* 0x400 - 0x40F */
48 u32 stat2[2]; /* 0x410 - 0x417 */
49 u32 statne_h; /* 0x418 - queue nearly empty */
50 u32 statf_h; /* 0x41C - queue full */
51 u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
52 u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
53 u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
54 u32 reserved[1776];
55 u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
56};
57
58void qmgr_set_irq(unsigned int queue, int src,
59 void (*handler)(void *pdev), void *pdev);
60void qmgr_enable_irq(unsigned int queue);
61void qmgr_disable_irq(unsigned int queue);
62
63/* request_ and release_queue() must be called from non-IRQ context */
64int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
65 unsigned int nearly_empty_watermark,
66 unsigned int nearly_full_watermark);
67void qmgr_release_queue(unsigned int queue);
68
69
70static inline void qmgr_put_entry(unsigned int queue, u32 val)
71{
72 extern struct qmgr_regs __iomem *qmgr_regs;
73 __raw_writel(val, &qmgr_regs->acc[queue][0]);
74}
75
76static inline u32 qmgr_get_entry(unsigned int queue)
77{
78 extern struct qmgr_regs __iomem *qmgr_regs;
79 return __raw_readl(&qmgr_regs->acc[queue][0]);
80}
81
82static inline int qmgr_get_stat1(unsigned int queue)
83{
84 extern struct qmgr_regs __iomem *qmgr_regs;
85 return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
86 >> ((queue & 7) << 2)) & 0xF;
87}
88
89static inline int qmgr_get_stat2(unsigned int queue)
90{
91 extern struct qmgr_regs __iomem *qmgr_regs;
92 return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
93 >> ((queue & 0xF) << 1)) & 0x3;
94}
95
96static inline int qmgr_stat_empty(unsigned int queue)
97{
98 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
99}
100
101static inline int qmgr_stat_nearly_empty(unsigned int queue)
102{
103 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
104}
105
106static inline int qmgr_stat_nearly_full(unsigned int queue)
107{
108 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
109}
110
111static inline int qmgr_stat_full(unsigned int queue)
112{
113 return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
114}
115
116static inline int qmgr_stat_underflow(unsigned int queue)
117{
118 return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
119}
120
121static inline int qmgr_stat_overflow(unsigned int queue)
122{
123 return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
124}
125
126#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h
new file mode 100644
index 000000000000..92a7e8ddf69a
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/system.h
@@ -0,0 +1,42 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/system.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <mach/hardware.h>
13
14static inline void arch_idle(void)
15{
16#if 0
17 if (!hlt_counter)
18 cpu_do_idle(0);
19#endif
20}
21
22
23static inline void arch_reset(char mode)
24{
25 if ( 1 && mode == 's') {
26 /* Jump into ROM at address 0 */
27 cpu_reset(0);
28 } else {
29 /* Use on-chip reset capability */
30
31 /* set the "key" register to enable access to
32 * "timer" and "enable" registers
33 */
34 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
35
36 /* write 0 to the timer register for an immediate reset */
37 *IXP4XX_OSWT = 0;
38
39 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
40 }
41}
42
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
new file mode 100644
index 000000000000..89ce3ee84698
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -0,0 +1,15 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/timex.h
3 *
4 */
5
6#include <mach/hardware.h>
7
8/*
9 * We use IXP425 General purpose timer for our timer needs, it runs at
10 * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
11 * timer register ignores the bottom 2 bits of the LATCH value.
12 */
13#define FREQ 66666666
14#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
15
diff --git a/arch/arm/mach-ixp4xx/include/mach/udc.h b/arch/arm/mach-ixp4xx/include/mach/udc.h
new file mode 100644
index 000000000000..80d6da2eafac
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/udc.h
@@ -0,0 +1,8 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/udc.h
3 *
4 */
5#include <asm/mach/udc_pxa2xx.h>
6
7extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
8
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..2db0078a8cf2
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -0,0 +1,57 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/uncompress.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 * Copyright (C) 2003-2004 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#ifndef _ARCH_UNCOMPRESS_H_
14#define _ARCH_UNCOMPRESS_H_
15
16#include "ixp4xx-regs.h"
17#include <asm/mach-types.h>
18#include <linux/serial_reg.h>
19
20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
21
22static volatile u32* uart_base;
23
24static inline void putc(int c)
25{
26 /* Check THRE and TEMT bits before we transmit the character.
27 */
28 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
29 barrier();
30
31 *uart_base = c;
32}
33
34static void flush(void)
35{
36}
37
38static __inline__ void __arch_decomp_setup(unsigned long arch_id)
39{
40 /*
41 * Some boards are using UART2 as console
42 */
43 if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
44 machine_is_gateway7001() || machine_is_wg302v2())
45 uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
46 else
47 uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
48}
49
50/*
51 * arch_id is a variable in decompress_kernel()
52 */
53#define arch_decomp_setup() __arch_decomp_setup(arch_id)
54
55#define arch_decomp_wdog()
56
57#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..7b3580b53adf
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/vmalloc.h
3 */
4#define VMALLOC_END (0xFF000000)
5
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 15:09:37 -0500