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-rw-r--r--arch/arm/mach-ixp4xx/common.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6d68aed6548a..dc5d7a0e5d9c 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -23,7 +23,6 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/bitops.h> 24#include <linux/bitops.h>
25#include <linux/time.h> 25#include <linux/time.h>
26#include <linux/timex.h>
27#include <linux/clocksource.h> 26#include <linux/clocksource.h>
28#include <linux/clockchips.h> 27#include <linux/clockchips.h>
29#include <linux/io.h> 28#include <linux/io.h>
@@ -45,6 +44,17 @@
45#include <asm/mach/irq.h> 44#include <asm/mach/irq.h>
46#include <asm/mach/time.h> 45#include <asm/mach/time.h>
47 46
47#define IXP4XX_TIMER_FREQ 66666000
48
49/*
50 * The timer register doesn't allow to specify the two least significant bits of
51 * the timeout value and assumes them being zero. So make sure IXP4XX_LATCH is
52 * the best value with the two least significant bits unset.
53 */
54#define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, \
55 (IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \
56 (IXP4XX_OST_RELOAD_MASK + 1)
57
48static void __init ixp4xx_clocksource_init(void); 58static void __init ixp4xx_clocksource_init(void);
49static void __init ixp4xx_clockevent_init(void); 59static void __init ixp4xx_clockevent_init(void);
50static struct clock_event_device clockevent_ixp4xx; 60static struct clock_event_device clockevent_ixp4xx;
@@ -520,7 +530,7 @@ static void ixp4xx_set_mode(enum clock_event_mode mode,
520 530
521 switch (mode) { 531 switch (mode) {
522 case CLOCK_EVT_MODE_PERIODIC: 532 case CLOCK_EVT_MODE_PERIODIC:
523 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK; 533 osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
524 opts = IXP4XX_OST_ENABLE; 534 opts = IXP4XX_OST_ENABLE;
525 break; 535 break;
526 case CLOCK_EVT_MODE_ONESHOT: 536 case CLOCK_EVT_MODE_ONESHOT: