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-rw-r--r--arch/arm/mach-iop33x/Kconfig21
-rw-r--r--arch/arm/mach-iop33x/Makefile11
-rw-r--r--arch/arm/mach-iop33x/Makefile.boot3
-rw-r--r--arch/arm/mach-iop33x/iq80331.c148
-rw-r--r--arch/arm/mach-iop33x/iq80332.c148
-rw-r--r--arch/arm/mach-iop33x/irq.c127
-rw-r--r--arch/arm/mach-iop33x/uart.c105
7 files changed, 563 insertions, 0 deletions
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig
new file mode 100644
index 000000000000..9aa016bb18f9
--- /dev/null
+++ b/arch/arm/mach-iop33x/Kconfig
@@ -0,0 +1,21 @@
1if ARCH_IOP33X
2
3menu "IOP33x Implementation Options"
4
5comment "IOP33x Platform Types"
6
7config ARCH_IQ80331
8 bool "Enable support for IQ80331"
9 help
10 Say Y here if you want to run your kernel on the Intel IQ80331
11 evaluation kit for the IOP331 chipset.
12
13config MACH_IQ80332
14 bool "Enable support for IQ80332"
15 help
16 Say Y here if you want to run your kernel on the Intel IQ80332
17 evaluation kit for the IOP332 chipset.
18
19endmenu
20
21endif
diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile
new file mode 100644
index 000000000000..90081d8c9d16
--- /dev/null
+++ b/arch/arm/mach-iop33x/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := irq.o uart.o
6obj-m :=
7obj-n :=
8obj- :=
9
10obj-$(CONFIG_ARCH_IQ80331) += iq80331.o
11obj-$(CONFIG_MACH_IQ80332) += iq80332.o
diff --git a/arch/arm/mach-iop33x/Makefile.boot b/arch/arm/mach-iop33x/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-iop33x/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
new file mode 100644
index 000000000000..97a7b7488264
--- /dev/null
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -0,0 +1,148 @@
1/*
2 * arch/arm/mach-iop33x/iq80331.c
3 *
4 * Board support code for the Intel IQ80331 platform.
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/mm.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/string.h>
20#include <linux/slab.h>
21#include <linux/serial_core.h>
22#include <linux/serial_8250.h>
23#include <linux/mtd/physmap.h>
24#include <linux/platform_device.h>
25#include <asm/hardware.h>
26#include <asm/io.h>
27#include <asm/irq.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/pci.h>
31#include <asm/mach/time.h>
32#include <asm/mach-types.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35
36/*
37 * IQ80331 timer tick configuration.
38 */
39static void __init iq80331_timer_init(void)
40{
41 /* D-Step parts run at a higher internal bus frequency */
42 if (*IOP3XX_ATURID >= 0xa)
43 iop3xx_init_time(333000000);
44 else
45 iop3xx_init_time(266000000);
46}
47
48static struct sys_timer iq80331_timer = {
49 .init = iq80331_timer_init,
50 .offset = iop3xx_gettimeoffset,
51};
52
53
54/*
55 * IQ80331 PCI.
56 */
57static inline int __init
58iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
59{
60 int irq;
61
62 if (slot == 1 && pin == 1) {
63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP33X_XINT1;
65 } else if (slot == 1 && pin == 2) {
66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP33X_XINT2;
68 } else if (slot == 1 && pin == 3) {
69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP33X_XINT3;
71 } else if (slot == 1 && pin == 4) {
72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP33X_XINT0;
74 } else if (slot == 2) {
75 /* GigE */
76 irq = IRQ_IOP33X_XINT2;
77 } else {
78 printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number,
80 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
81 irq = -1;
82 }
83
84 return irq;
85}
86
87static struct hw_pci iq80331_pci __initdata = {
88 .swizzle = pci_std_swizzle,
89 .nr_controllers = 1,
90 .setup = iop3xx_pci_setup,
91 .preinit = iop3xx_pci_preinit,
92 .scan = iop3xx_pci_scan_bus,
93 .map_irq = iq80331_pci_map_irq,
94};
95
96static int __init iq80331_pci_init(void)
97{
98 if (machine_is_iq80331())
99 pci_common_init(&iq80331_pci);
100
101 return 0;
102}
103
104subsys_initcall(iq80331_pci_init);
105
106
107/*
108 * IQ80331 machine initialisation.
109 */
110static struct physmap_flash_data iq80331_flash_data = {
111 .width = 1,
112};
113
114static struct resource iq80331_flash_resource = {
115 .start = 0xc0000000,
116 .end = 0xc07fffff,
117 .flags = IORESOURCE_MEM,
118};
119
120static struct platform_device iq80331_flash_device = {
121 .name = "physmap-flash",
122 .id = 0,
123 .dev = {
124 .platform_data = &iq80331_flash_data,
125 },
126 .num_resources = 1,
127 .resource = &iq80331_flash_resource,
128};
129
130static void __init iq80331_init_machine(void)
131{
132 platform_device_register(&iop3xx_i2c0_device);
133 platform_device_register(&iop3xx_i2c1_device);
134 platform_device_register(&iop33x_uart0_device);
135 platform_device_register(&iop33x_uart1_device);
136 platform_device_register(&iq80331_flash_device);
137}
138
139MACHINE_START(IQ80331, "Intel IQ80331")
140 /* Maintainer: Intel Corp. */
141 .phys_io = 0xfefff000,
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io,
145 .init_irq = iop33x_init_irq,
146 .timer = &iq80331_timer,
147 .init_machine = iq80331_init_machine,
148MACHINE_END
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
new file mode 100644
index 000000000000..9887bfc1c078
--- /dev/null
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -0,0 +1,148 @@
1/*
2 * arch/arm/mach-iop33x/iq80332.c
3 *
4 * Board support code for the Intel IQ80332 platform.
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/mm.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/string.h>
20#include <linux/slab.h>
21#include <linux/serial_core.h>
22#include <linux/serial_8250.h>
23#include <linux/mtd/physmap.h>
24#include <linux/platform_device.h>
25#include <asm/hardware.h>
26#include <asm/io.h>
27#include <asm/irq.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/pci.h>
31#include <asm/mach/time.h>
32#include <asm/mach-types.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35
36/*
37 * IQ80332 timer tick configuration.
38 */
39static void __init iq80332_timer_init(void)
40{
41 /* D-Step parts and the iop333 run at a higher internal bus frequency */
42 if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374)
43 iop3xx_init_time(333000000);
44 else
45 iop3xx_init_time(266000000);
46}
47
48static struct sys_timer iq80332_timer = {
49 .init = iq80332_timer_init,
50 .offset = iop3xx_gettimeoffset,
51};
52
53
54/*
55 * IQ80332 PCI.
56 */
57static inline int __init
58iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
59{
60 int irq;
61
62 if (slot == 4 && pin == 1) {
63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP33X_XINT0;
65 } else if (slot == 4 && pin == 2) {
66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP33X_XINT1;
68 } else if (slot == 4 && pin == 3) {
69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP33X_XINT2;
71 } else if (slot == 4 && pin == 4) {
72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP33X_XINT3;
74 } else if (slot == 6) {
75 /* GigE */
76 irq = IRQ_IOP33X_XINT2;
77 } else {
78 printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number,
80 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
81 irq = -1;
82 }
83
84 return irq;
85}
86
87static struct hw_pci iq80332_pci __initdata = {
88 .swizzle = pci_std_swizzle,
89 .nr_controllers = 1,
90 .setup = iop3xx_pci_setup,
91 .preinit = iop3xx_pci_preinit,
92 .scan = iop3xx_pci_scan_bus,
93 .map_irq = iq80332_pci_map_irq,
94};
95
96static int __init iq80332_pci_init(void)
97{
98 if (machine_is_iq80332())
99 pci_common_init(&iq80332_pci);
100
101 return 0;
102}
103
104subsys_initcall(iq80332_pci_init);
105
106
107/*
108 * IQ80332 machine initialisation.
109 */
110static struct physmap_flash_data iq80332_flash_data = {
111 .width = 1,
112};
113
114static struct resource iq80332_flash_resource = {
115 .start = 0xc0000000,
116 .end = 0xc07fffff,
117 .flags = IORESOURCE_MEM,
118};
119
120static struct platform_device iq80332_flash_device = {
121 .name = "physmap-flash",
122 .id = 0,
123 .dev = {
124 .platform_data = &iq80332_flash_data,
125 },
126 .num_resources = 1,
127 .resource = &iq80332_flash_resource,
128};
129
130static void __init iq80332_init_machine(void)
131{
132 platform_device_register(&iop3xx_i2c0_device);
133 platform_device_register(&iop3xx_i2c1_device);
134 platform_device_register(&iop33x_uart0_device);
135 platform_device_register(&iop33x_uart1_device);
136 platform_device_register(&iq80332_flash_device);
137}
138
139MACHINE_START(IQ80332, "Intel IQ80332")
140 /* Maintainer: Intel Corp. */
141 .phys_io = 0xfefff000,
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io,
145 .init_irq = iop33x_init_irq,
146 .timer = &iq80332_timer,
147 .init_machine = iq80332_init_machine,
148MACHINE_END
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
new file mode 100644
index 000000000000..63304b3d0d76
--- /dev/null
+++ b/arch/arm/mach-iop33x/irq.c
@@ -0,0 +1,127 @@
1/*
2 * arch/arm/mach-iop33x/irq.c
3 *
4 * Generic IOP331 IRQ handling functionality
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <asm/mach/irq.h>
18#include <asm/irq.h>
19#include <asm/hardware.h>
20#include <asm/mach-types.h>
21
22static u32 iop33x_mask0;
23static u32 iop33x_mask1;
24
25static inline void intctl0_write(u32 val)
26{
27 iop3xx_cp6_enable();
28 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
29 iop3xx_cp6_disable();
30}
31
32static inline void intctl1_write(u32 val)
33{
34 iop3xx_cp6_enable();
35 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
36 iop3xx_cp6_disable();
37}
38
39static inline void intstr0_write(u32 val)
40{
41 iop3xx_cp6_enable();
42 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
43 iop3xx_cp6_disable();
44}
45
46static inline void intstr1_write(u32 val)
47{
48 iop3xx_cp6_enable();
49 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
50 iop3xx_cp6_disable();
51}
52
53static inline void intbase_write(u32 val)
54{
55 iop3xx_cp6_enable();
56 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
57 iop3xx_cp6_disable();
58}
59
60static inline void intsize_write(u32 val)
61{
62 iop3xx_cp6_enable();
63 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
64 iop3xx_cp6_disable();
65}
66
67static void
68iop33x_irq_mask1 (unsigned int irq)
69{
70 iop33x_mask0 &= ~(1 << irq);
71 intctl0_write(iop33x_mask0);
72}
73
74static void
75iop33x_irq_mask2 (unsigned int irq)
76{
77 iop33x_mask1 &= ~(1 << (irq - 32));
78 intctl1_write(iop33x_mask1);
79}
80
81static void
82iop33x_irq_unmask1(unsigned int irq)
83{
84 iop33x_mask0 |= 1 << irq;
85 intctl0_write(iop33x_mask0);
86}
87
88static void
89iop33x_irq_unmask2(unsigned int irq)
90{
91 iop33x_mask1 |= (1 << (irq - 32));
92 intctl1_write(iop33x_mask1);
93}
94
95struct irq_chip iop33x_irqchip1 = {
96 .name = "IOP33x-1",
97 .ack = iop33x_irq_mask1,
98 .mask = iop33x_irq_mask1,
99 .unmask = iop33x_irq_unmask1,
100};
101
102struct irq_chip iop33x_irqchip2 = {
103 .name = "IOP33x-2",
104 .ack = iop33x_irq_mask2,
105 .mask = iop33x_irq_mask2,
106 .unmask = iop33x_irq_unmask2,
107};
108
109void __init iop33x_init_irq(void)
110{
111 int i;
112
113 intctl0_write(0);
114 intctl1_write(0);
115 intstr0_write(0);
116 intstr1_write(0);
117 intbase_write(0);
118 intsize_write(1);
119 if (machine_is_iq80331())
120 *IOP3XX_PCIIRSR = 0x0f;
121
122 for (i = 0; i < NR_IRQS; i++) {
123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
124 set_irq_handler(i, do_level_IRQ);
125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126 }
127}
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
new file mode 100644
index 000000000000..ac297cd0276c
--- /dev/null
+++ b/arch/arm/mach-iop33x/uart.c
@@ -0,0 +1,105 @@
1/*
2 * arch/arm/mach-iop33x/uart.c
3 *
4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright (C) 2004 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/mm.h>
13#include <linux/init.h>
14#include <linux/major.h>
15#include <linux/fs.h>
16#include <linux/platform_device.h>
17#include <linux/serial.h>
18#include <linux/tty.h>
19#include <linux/serial_8250.h>
20#include <asm/io.h>
21#include <asm/pgtable.h>
22#include <asm/page.h>
23#include <asm/mach/map.h>
24#include <asm/setup.h>
25#include <asm/system.h>
26#include <asm/memory.h>
27#include <asm/hardware.h>
28#include <asm/hardware/iop3xx.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32#define IOP33X_UART_XTAL 33334000
33
34static struct plat_serial8250_port iop33x_uart0_data[] = {
35 {
36 .membase = (char *)IOP33X_UART0_VIRT,
37 .mapbase = IOP33X_UART0_PHYS,
38 .irq = IRQ_IOP33X_UART0,
39 .uartclk = IOP33X_UART_XTAL,
40 .regshift = 2,
41 .iotype = UPIO_MEM,
42 .flags = UPF_SKIP_TEST,
43 },
44 { },
45};
46
47static struct resource iop33x_uart0_resources[] = {
48 [0] = {
49 .start = IOP33X_UART0_PHYS,
50 .end = IOP33X_UART0_PHYS + 0x3f,
51 .flags = IORESOURCE_MEM,
52 },
53 [1] = {
54 .start = IRQ_IOP33X_UART0,
55 .end = IRQ_IOP33X_UART0,
56 .flags = IORESOURCE_IRQ,
57 },
58};
59
60struct platform_device iop33x_uart0_device = {
61 .name = "serial8250",
62 .id = PLAT8250_DEV_PLATFORM,
63 .dev = {
64 .platform_data = iop33x_uart0_data,
65 },
66 .num_resources = 2,
67 .resource = iop33x_uart0_resources,
68};
69
70
71static struct resource iop33x_uart1_resources[] = {
72 [0] = {
73 .start = IOP33X_UART1_PHYS,
74 .end = IOP33X_UART1_PHYS + 0x3f,
75 .flags = IORESOURCE_MEM,
76 },
77 [1] = {
78 .start = IRQ_IOP33X_UART1,
79 .end = IRQ_IOP33X_UART1,
80 .flags = IORESOURCE_IRQ,
81 },
82};
83
84static struct plat_serial8250_port iop33x_uart1_data[] = {
85 {
86 .membase = (char *)IOP33X_UART1_VIRT,
87 .mapbase = IOP33X_UART1_PHYS,
88 .irq = IRQ_IOP33X_UART1,
89 .uartclk = IOP33X_UART_XTAL,
90 .regshift = 2,
91 .iotype = UPIO_MEM,
92 .flags = UPF_SKIP_TEST,
93 },
94 { },
95};
96
97struct platform_device iop33x_uart1_device = {
98 .name = "serial8250",
99 .id = PLAT8250_DEV_PLATFORM1,
100 .dev = {
101 .platform_data = iop33x_uart1_data,
102 },
103 .num_resources = 2,
104 .resource = iop33x_uart1_resources,
105};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 21:08:10 -0500