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-rw-r--r--arch/arm/mach-iop33x/include/mach/adma.h5
-rw-r--r--arch/arm/mach-iop33x/include/mach/debug-macro.S24
-rw-r--r--arch/arm/mach-iop33x/include/mach/dma.h9
-rw-r--r--arch/arm/mach-iop33x/include/mach/entry-macro.S37
-rw-r--r--arch/arm/mach-iop33x/include/mach/gpio.h6
-rw-r--r--arch/arm/mach-iop33x/include/mach/hardware.h46
-rw-r--r--arch/arm/mach-iop33x/include/mach/io.h27
-rw-r--r--arch/arm/mach-iop33x/include/mach/iop33x.h43
-rw-r--r--arch/arm/mach-iop33x/include/mach/iq80331.h16
-rw-r--r--arch/arm/mach-iop33x/include/mach/iq80332.h16
-rw-r--r--arch/arm/mach-iop33x/include/mach/irqs.h60
-rw-r--r--arch/arm/mach-iop33x/include/mach/memory.h26
-rw-r--r--arch/arm/mach-iop33x/include/mach/system.h22
-rw-r--r--arch/arm/mach-iop33x/include/mach/time.h4
-rw-r--r--arch/arm/mach-iop33x/include/mach/timex.h9
-rw-r--r--arch/arm/mach-iop33x/include/mach/uncompress.h37
-rw-r--r--arch/arm/mach-iop33x/include/mach/vmalloc.h5
-rw-r--r--arch/arm/mach-iop33x/iq80331.c4
-rw-r--r--arch/arm/mach-iop33x/iq80332.c4
-rw-r--r--arch/arm/mach-iop33x/irq.c2
-rw-r--r--arch/arm/mach-iop33x/uart.c2
21 files changed, 398 insertions, 6 deletions
diff --git a/arch/arm/mach-iop33x/include/mach/adma.h b/arch/arm/mach-iop33x/include/mach/adma.h
new file mode 100644
index 000000000000..4b92f795f90e
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/adma.h
@@ -0,0 +1,5 @@
1#ifndef IOP33X_ADMA_H
2#define IOP33X_ADMA_H
3#include <asm/hardware/iop3xx-adma.h>
4#endif
5
diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S
new file mode 100644
index 000000000000..a60c9ef05cc3
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/debug-macro.S
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 .macro addruart, rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ mmu enabled?
17 moveq \rx, #0xff000000 @ physical
18 movne \rx, #0xfe000000 @ virtual
19 orr \rx, \rx, #0x00ff0000
20 orr \rx, \rx, #0x0000f700
21 .endm
22
23#define UART_SHIFT 2
24#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-iop33x/include/mach/dma.h b/arch/arm/mach-iop33x/include/mach/dma.h
new file mode 100644
index 000000000000..d8b42232931d
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/dma.h
@@ -0,0 +1,9 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/dma.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
diff --git a/arch/arm/mach-iop33x/include/mach/entry-macro.S b/arch/arm/mach-iop33x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..4e1f7282b354
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/entry-macro.S
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IOP33x-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/iop33x.h>
11
12 .macro disable_fiq
13 .endm
14
15 .macro get_irqnr_preamble, base, tmp
16 mrc p15, 0, \tmp, c15, c1, 0
17 orr \tmp, \tmp, #(1 << 6)
18 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
19 mrc p15, 0, \tmp, c15, c1, 0
20 mov \tmp, \tmp
21 sub pc, pc, #4 @ cp_wait
22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC
26 cmp \irqstat, #0
27 mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround
28 adds \irqnr, \irqstat, #1
29 movne \irqnr, \irqstat, lsr #2
30 .endm
31
32 .macro arch_ret_to_user, tmp1, tmp2
33 mrc p15, 0, \tmp1, c15, c1, 0
34 ands \tmp2, \tmp1, #(1 << 6)
35 bicne \tmp1, \tmp1, #(1 << 6)
36 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
37 .endm
diff --git a/arch/arm/mach-iop33x/include/mach/gpio.h b/arch/arm/mach-iop33x/include/mach/gpio.h
new file mode 100644
index 000000000000..ddd55bba9bb9
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/gpio.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_ARCH_IOP33X_GPIO_H
2#define __ASM_ARCH_IOP33X_GPIO_H
3
4#include <asm/hardware/iop3xx-gpio.h>
5
6#endif
diff --git a/arch/arm/mach-iop33x/include/mach/hardware.h b/arch/arm/mach-iop33x/include/mach/hardware.h
new file mode 100644
index 000000000000..8c10e430655e
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/hardware.h
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/hardware.h
3 */
4
5#ifndef __HARDWARE_H
6#define __HARDWARE_H
7
8#include <asm/types.h>
9
10/*
11 * Note about PCI IO space mappings
12 *
13 * To make IO space accesses efficient, we store virtual addresses in
14 * the IO resources.
15 *
16 * The PCI IO space is located at virtual 0xfe000000 from physical
17 * 0x90000000. The PCI BARs must be programmed with physical addresses,
18 * but when we read them, we convert them to virtual addresses. See
19 * arch/arm/mach-iop3xx/iop3xx-pci.c
20 */
21#define pcibios_assign_all_busses() 1
22#define PCIBIOS_MIN_IO 0x00000000
23#define PCIBIOS_MIN_MEM 0x00000000
24
25#ifndef __ASSEMBLY__
26void iop33x_init_irq(void);
27
28extern struct platform_device iop33x_uart0_device;
29extern struct platform_device iop33x_uart1_device;
30#endif
31
32
33/*
34 * Generic chipset bits
35 *
36 */
37#include "iop33x.h"
38
39/*
40 * Board specific bits
41 */
42#include "iq80331.h"
43#include "iq80332.h"
44
45
46#endif
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
new file mode 100644
index 000000000000..158874631217
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/io.h
@@ -0,0 +1,27 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/io.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __IO_H
12#define __IO_H
13
14#include <mach/hardware.h>
15
16extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
17 unsigned int mtype);
18extern void __iop3xx_iounmap(void __iomem *addr);
19
20#define IO_SPACE_LIMIT 0xffffffff
21#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
22#define __mem_pci(a) (a)
23
24#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
25#define __arch_iounmap(a) __iop3xx_iounmap(a)
26
27#endif
diff --git a/arch/arm/mach-iop33x/include/mach/iop33x.h b/arch/arm/mach-iop33x/include/mach/iop33x.h
new file mode 100644
index 000000000000..24567316ec88
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/iop33x.h
@@ -0,0 +1,43 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/iop33x.h
3 *
4 * Intel IOP33X Chip definitions
5 *
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __IOP33X_H
15#define __IOP33X_H
16
17/*
18 * Peripherals that are shared between the iop32x and iop33x but
19 * located at different addresses.
20 */
21#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
22#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
23
24#include <asm/hardware/iop3xx.h>
25
26/* UARTs */
27#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
28#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
29#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
30#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
31
32/* ATU Parameters
33 * set up a 1:1 bus to physical ram relationship
34 * w/ pci on top of physical ram in memory map
35 */
36#define IOP33X_MAX_RAM_SIZE 0x80000000UL
37#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE
38#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE)
39#define IOP33X_PCI_MEM_WINDOW_SIZE 0x08000000
40#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP33X_PCI_MEM_WINDOW_SIZE
41
42
43#endif
diff --git a/arch/arm/mach-iop33x/include/mach/iq80331.h b/arch/arm/mach-iop33x/include/mach/iq80331.h
new file mode 100644
index 000000000000..fe406b0127f7
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/iq80331.h
@@ -0,0 +1,16 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/iq80331.h
3 *
4 * Intel IQ80331 evaluation board registers
5 */
6
7#ifndef __IQ80331_H
8#define __IQ80331_H
9
10#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
11#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
12#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
13#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
14
15
16#endif
diff --git a/arch/arm/mach-iop33x/include/mach/iq80332.h b/arch/arm/mach-iop33x/include/mach/iq80332.h
new file mode 100644
index 000000000000..8325d71f2ed5
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/iq80332.h
@@ -0,0 +1,16 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/iq80332.h
3 *
4 * Intel IQ80332 evaluation board registers
5 */
6
7#ifndef __IQ80332_H
8#define __IQ80332_H
9
10#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
11#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
12#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
13#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
14
15
16#endif
diff --git a/arch/arm/mach-iop33x/include/mach/irqs.h b/arch/arm/mach-iop33x/include/mach/irqs.h
new file mode 100644
index 000000000000..707628a600ac
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/irqs.h
@@ -0,0 +1,60 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/irqs.h
3 *
4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright: (C) 2003 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __IRQS_H
13#define __IRQS_H
14
15/*
16 * IOP80331 chipset interrupts
17 */
18#define IRQ_IOP33X_DMA0_EOT 0
19#define IRQ_IOP33X_DMA0_EOC 1
20#define IRQ_IOP33X_DMA1_EOT 2
21#define IRQ_IOP33X_DMA1_EOC 3
22#define IRQ_IOP33X_AA_EOT 6
23#define IRQ_IOP33X_AA_EOC 7
24#define IRQ_IOP33X_TIMER0 8
25#define IRQ_IOP33X_TIMER1 9
26#define IRQ_IOP33X_I2C_0 10
27#define IRQ_IOP33X_I2C_1 11
28#define IRQ_IOP33X_MSG 12
29#define IRQ_IOP33X_MSGIBQ 13
30#define IRQ_IOP33X_ATU_BIST 14
31#define IRQ_IOP33X_PERFMON 15
32#define IRQ_IOP33X_CORE_PMU 16
33#define IRQ_IOP33X_XINT0 24
34#define IRQ_IOP33X_XINT1 25
35#define IRQ_IOP33X_XINT2 26
36#define IRQ_IOP33X_XINT3 27
37#define IRQ_IOP33X_XINT8 32
38#define IRQ_IOP33X_XINT9 33
39#define IRQ_IOP33X_XINT10 34
40#define IRQ_IOP33X_XINT11 35
41#define IRQ_IOP33X_XINT12 36
42#define IRQ_IOP33X_XINT13 37
43#define IRQ_IOP33X_XINT14 38
44#define IRQ_IOP33X_XINT15 39
45#define IRQ_IOP33X_UART0 51
46#define IRQ_IOP33X_UART1 52
47#define IRQ_IOP33X_PBIE 53
48#define IRQ_IOP33X_ATU_CRW 54
49#define IRQ_IOP33X_ATU_ERR 55
50#define IRQ_IOP33X_MCU_ERR 56
51#define IRQ_IOP33X_DMA0_ERR 57
52#define IRQ_IOP33X_DMA1_ERR 58
53#define IRQ_IOP33X_AA_ERR 60
54#define IRQ_IOP33X_MSG_ERR 62
55#define IRQ_IOP33X_HPI 63
56
57#define NR_IRQS 64
58
59
60#endif
diff --git a/arch/arm/mach-iop33x/include/mach/memory.h b/arch/arm/mach-iop33x/include/mach/memory.h
new file mode 100644
index 000000000000..2cef0bbb354f
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/memory.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/memory.h
3 */
4
5#ifndef __MEMORY_H
6#define __MEMORY_H
7
8#include <mach/hardware.h>
9
10/*
11 * Physical DRAM offset.
12 */
13#define PHYS_OFFSET UL(0x00000000)
14
15/*
16 * Virtual view <-> PCI DMA view memory address translations
17 * virt_to_bus: Used to translate the virtual address to an
18 * address suitable to be passed to set_dma_addr
19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use.
21 */
22#define __virt_to_bus(x) (__virt_to_phys(x))
23#define __bus_to_virt(x) (__phys_to_virt(x))
24
25
26#endif
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h
new file mode 100644
index 000000000000..7bf3bfb49446
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/system.h
@@ -0,0 +1,22 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/system.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
15
16static inline void arch_reset(char mode)
17{
18 *IOP3XX_PCSR = 0x30;
19
20 /* Jump into ROM at address 0 */
21 cpu_reset(0);
22}
diff --git a/arch/arm/mach-iop33x/include/mach/time.h b/arch/arm/mach-iop33x/include/mach/time.h
new file mode 100644
index 000000000000..4ac4d7664f85
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/time.h
@@ -0,0 +1,4 @@
1#ifndef _IOP33X_TIME_H_
2#define _IOP33X_TIME_H_
3#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0
4#endif
diff --git a/arch/arm/mach-iop33x/include/mach/timex.h b/arch/arm/mach-iop33x/include/mach/timex.h
new file mode 100644
index 000000000000..c75760844d49
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/timex.h
@@ -0,0 +1,9 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/timex.h
3 *
4 * IOP3xx architecture timex specifications
5 */
6
7#include <mach/hardware.h>
8
9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h
new file mode 100644
index 000000000000..b42423f63302
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/uncompress.h
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/uncompress.h
3 */
4
5#include <asm/types.h>
6#include <asm/mach-types.h>
7#include <linux/serial_reg.h>
8#include <mach/hardware.h>
9
10static volatile u32 *uart_base;
11
12#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
13
14static inline void putc(char c)
15{
16 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
17 barrier();
18 uart_base[UART_TX] = c;
19}
20
21static inline void flush(void)
22{
23}
24
25static __inline__ void __arch_decomp_setup(unsigned long arch_id)
26{
27 if (machine_is_iq80331() || machine_is_iq80332())
28 uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
29 else
30 uart_base = (volatile u32 *)0xfe800000;
31}
32
33/*
34 * nothing to do
35 */
36#define arch_decomp_setup() __arch_decomp_setup(arch_id)
37#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop33x/include/mach/vmalloc.h b/arch/arm/mach-iop33x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..f9f99dea9bc4
--- /dev/null
+++ b/arch/arm/mach-iop33x/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe000000
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index e736c50ed3dc..c7d99f9fafed 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -22,7 +22,7 @@
22#include <linux/serial_8250.h> 22#include <linux/serial_8250.h>
23#include <linux/mtd/physmap.h> 23#include <linux/mtd/physmap.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <asm/arch/hardware.h> 25#include <mach/hardware.h>
26#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/irq.h> 27#include <asm/irq.h>
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
@@ -32,7 +32,7 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33#include <asm/page.h> 33#include <asm/page.h>
34#include <asm/pgtable.h> 34#include <asm/pgtable.h>
35#include <asm/arch/time.h> 35#include <mach/time.h>
36 36
37/* 37/*
38 * IQ80331 timer tick configuration. 38 * IQ80331 timer tick configuration.
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 75347a23ceb1..af616c5f4fb2 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -22,7 +22,7 @@
22#include <linux/serial_8250.h> 22#include <linux/serial_8250.h>
23#include <linux/mtd/physmap.h> 23#include <linux/mtd/physmap.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <asm/arch/hardware.h> 25#include <mach/hardware.h>
26#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/irq.h> 27#include <asm/irq.h>
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
@@ -32,7 +32,7 @@
32#include <asm/mach-types.h> 32#include <asm/mach-types.h>
33#include <asm/page.h> 33#include <asm/page.h>
34#include <asm/pgtable.h> 34#include <asm/pgtable.h>
35#include <asm/arch/time.h> 35#include <mach/time.h>
36 36
37/* 37/*
38 * IQ80332 timer tick configuration. 38 * IQ80332 timer tick configuration.
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 6ae1fac6c61a..abb4ea2ed4fd 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -16,7 +16,7 @@
16#include <linux/list.h> 16#include <linux/list.h>
17#include <asm/mach/irq.h> 17#include <asm/mach/irq.h>
18#include <asm/irq.h> 18#include <asm/irq.h>
19#include <asm/arch/hardware.h> 19#include <mach/hardware.h>
20#include <asm/mach-types.h> 20#include <asm/mach-types.h>
21 21
22static u32 iop33x_mask0; 22static u32 iop33x_mask0;
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
index f11b86fc86c1..8c21870fa808 100644
--- a/arch/arm/mach-iop33x/uart.c
+++ b/arch/arm/mach-iop33x/uart.c
@@ -24,7 +24,7 @@
24#include <asm/setup.h> 24#include <asm/setup.h>
25#include <asm/system.h> 25#include <asm/system.h>
26#include <asm/memory.h> 26#include <asm/memory.h>
27#include <asm/arch/hardware.h> 27#include <mach/hardware.h>
28#include <asm/hardware/iop3xx.h> 28#include <asm/hardware/iop3xx.h>
29#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
30 30
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 17:01:54 -0500