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-rw-r--r--arch/arm/mach-iop33x/irq.c129
1 files changed, 129 insertions, 0 deletions
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
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1/*
2 * linux/arch/arm/mach-iop33x/irq.c
3 *
4 * Generic IOP331 IRQ handling functionality
5 *
6 * Author: Dave Jiang <dave.jiang@intel.com>
7 * Copyright (C) 2003 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 *
14 */
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18
19#include <asm/mach/irq.h>
20#include <asm/irq.h>
21#include <asm/hardware.h>
22
23#include <asm/mach-types.h>
24
25static u32 iop331_mask0 = 0;
26static u32 iop331_mask1 = 0;
27
28static inline void intctl_write0(u32 val)
29{
30 // INTCTL0
31 asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
32}
33
34static inline void intctl_write1(u32 val)
35{
36 // INTCTL1
37 asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
38}
39
40static inline void intstr_write0(u32 val)
41{
42 // INTSTR0
43 asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
44}
45
46static inline void intstr_write1(u32 val)
47{
48 // INTSTR1
49 asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
50}
51
52static void
53iop331_irq_mask1 (unsigned int irq)
54{
55 iop331_mask0 &= ~(1 << (irq - IOP331_IRQ_OFS));
56 intctl_write0(iop331_mask0);
57}
58
59static void
60iop331_irq_mask2 (unsigned int irq)
61{
62 iop331_mask1 &= ~(1 << (irq - IOP331_IRQ_OFS - 32));
63 intctl_write1(iop331_mask1);
64}
65
66static void
67iop331_irq_unmask1(unsigned int irq)
68{
69 iop331_mask0 |= (1 << (irq - IOP331_IRQ_OFS));
70 intctl_write0(iop331_mask0);
71}
72
73static void
74iop331_irq_unmask2(unsigned int irq)
75{
76 iop331_mask1 |= (1 << (irq - IOP331_IRQ_OFS - 32));
77 intctl_write1(iop331_mask1);
78}
79
80struct irq_chip iop331_irqchip1 = {
81 .name = "IOP-1",
82 .ack = iop331_irq_mask1,
83 .mask = iop331_irq_mask1,
84 .unmask = iop331_irq_unmask1,
85};
86
87struct irq_chip iop331_irqchip2 = {
88 .name = "IOP-2",
89 .ack = iop331_irq_mask2,
90 .mask = iop331_irq_mask2,
91 .unmask = iop331_irq_unmask2,
92};
93
94void __init iop331_init_irq(void)
95{
96 unsigned int i, tmp;
97
98 /* Enable access to coprocessor 6 for dealing with IRQs.
99 * From RMK:
100 * Basically, the Intel documentation here is poor. It appears that
101 * you need to set the bit to be able to access the coprocessor from
102 * SVC mode. Whether that allows access from user space or not is
103 * unclear.
104 */
105 asm volatile (
106 "mrc p15, 0, %0, c15, c1, 0\n\t"
107 "orr %0, %0, %1\n\t"
108 "mcr p15, 0, %0, c15, c1, 0\n\t"
109 /* The action is delayed, so we have to do this: */
110 "mrc p15, 0, %0, c15, c1, 0\n\t"
111 "mov %0, %0\n\t"
112 "sub pc, pc, #4"
113 : "=r" (tmp) : "i" (1 << 6) );
114
115 intctl_write0(0); // disable all interrupts
116 intctl_write1(0);
117 intstr_write0(0); // treat all as IRQ
118 intstr_write1(0);
119 if(machine_is_iq80331()) // all interrupts are inputs to chip
120 *IOP331_PCIIRSR = 0x0f;
121
122 for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++)
123 {
124 set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
125 set_irq_handler(i, do_level_IRQ);
126 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
127 }
128}
129