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-rw-r--r--arch/arm/mach-iop32x/Kconfig9
-rw-r--r--arch/arm/mach-iop32x/iq31244.c22
-rw-r--r--arch/arm/mach-iop32x/iq80321.c14
-rw-r--r--arch/arm/mach-iop32x/irq.c54
4 files changed, 45 insertions, 54 deletions
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index ff8a77a8866e..d7abfaa525c3 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -8,13 +8,14 @@ config ARCH_IQ80321
8 bool "Enable support for IQ80321" 8 bool "Enable support for IQ80321"
9 help 9 help
10 Say Y here if you want to run your kernel on the Intel IQ80321 10 Say Y here if you want to run your kernel on the Intel IQ80321
11 evaluation kit for the IOP321 chipset. 11 evaluation kit for the IOP321 processor.
12 12
13config ARCH_IQ31244 13config ARCH_IQ31244
14 bool "Enable support for IQ31244" 14 bool "Enable support for EP80219/IQ31244"
15 help 15 help
16 Say Y here if you want to run your kernel on the Intel IQ31244 16 Say Y here if you want to run your kernel on the Intel EP80219
17 evaluation kit for the IOP321 chipset. 17 evaluation kit for the Intel 80219 processor (a IOP321 variant)
18 or the IQ31244 evaluation kit for the IOP321 processor.
18 19
19endmenu 20endmenu
20 21
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 88b77d32b0ac..be4aedfa0de6 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -98,16 +98,16 @@ ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
98 98
99 if (slot == 0) { 99 if (slot == 0) {
100 /* CFlash */ 100 /* CFlash */
101 irq = IRQ_IOP321_XINT1; 101 irq = IRQ_IOP32X_XINT1;
102 } else if (slot == 1) { 102 } else if (slot == 1) {
103 /* 82551 Pro 100 */ 103 /* 82551 Pro 100 */
104 irq = IRQ_IOP321_XINT0; 104 irq = IRQ_IOP32X_XINT0;
105 } else if (slot == 2) { 105 } else if (slot == 2) {
106 /* PCI-X Slot */ 106 /* PCI-X Slot */
107 irq = IRQ_IOP321_XINT3; 107 irq = IRQ_IOP32X_XINT3;
108 } else if (slot == 3) { 108 } else if (slot == 3) {
109 /* SATA */ 109 /* SATA */
110 irq = IRQ_IOP321_XINT2; 110 irq = IRQ_IOP32X_XINT2;
111 } else { 111 } else {
112 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown " 112 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
113 "device PCI:%d:%d:%d\n", dev->bus->number, 113 "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -134,18 +134,18 @@ iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
134 134
135 if (slot == 0) { 135 if (slot == 0) {
136 /* CFlash */ 136 /* CFlash */
137 irq = IRQ_IOP321_XINT1; 137 irq = IRQ_IOP32X_XINT1;
138 } else if (slot == 1) { 138 } else if (slot == 1) {
139 /* SATA */ 139 /* SATA */
140 irq = IRQ_IOP321_XINT2; 140 irq = IRQ_IOP32X_XINT2;
141 } else if (slot == 2) { 141 } else if (slot == 2) {
142 /* PCI-X Slot */ 142 /* PCI-X Slot */
143 irq = IRQ_IOP321_XINT3; 143 irq = IRQ_IOP32X_XINT3;
144 } else if (slot == 3) { 144 } else if (slot == 3) {
145 /* 82546 GigE */ 145 /* 82546 GigE */
146 irq = IRQ_IOP321_XINT0; 146 irq = IRQ_IOP32X_XINT0;
147 } else { 147 } else {
148 printk(KERN_ERR "iq31244_pci_map_irq() called for unknown " 148 printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
149 "device PCI:%d:%d:%d\n", dev->bus->number, 149 "device PCI:%d:%d:%d\n", dev->bus->number,
150 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 150 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
151 irq = -1; 151 irq = -1;
@@ -206,7 +206,7 @@ static struct plat_serial8250_port iq31244_serial_port[] = {
206 { 206 {
207 .mapbase = IQ31244_UART, 207 .mapbase = IQ31244_UART,
208 .membase = (char *)IQ31244_UART, 208 .membase = (char *)IQ31244_UART,
209 .irq = IRQ_IOP321_XINT1, 209 .irq = IRQ_IOP32X_XINT1,
210 .flags = UPF_SKIP_TEST, 210 .flags = UPF_SKIP_TEST,
211 .iotype = UPIO_MEM, 211 .iotype = UPIO_MEM,
212 .regshift = 0, 212 .regshift = 0,
@@ -287,7 +287,7 @@ MACHINE_START(IQ31244, "Intel IQ31244")
287 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, 287 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
288 .boot_params = 0xa0000100, 288 .boot_params = 0xa0000100,
289 .map_io = iq31244_map_io, 289 .map_io = iq31244_map_io,
290 .init_irq = iop321_init_irq, 290 .init_irq = iop32x_init_irq,
291 .timer = &iq31244_timer, 291 .timer = &iq31244_timer,
292 .init_machine = iq31244_init_machine, 292 .init_machine = iq31244_init_machine,
293MACHINE_END 293MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 3c9b86271759..1f37b5501888 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -78,19 +78,19 @@ iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
78 78
79 if ((slot == 2 || slot == 6) && pin == 1) { 79 if ((slot == 2 || slot == 6) && pin == 1) {
80 /* PCI-X Slot INTA */ 80 /* PCI-X Slot INTA */
81 irq = IRQ_IOP321_XINT2; 81 irq = IRQ_IOP32X_XINT2;
82 } else if ((slot == 2 || slot == 6) && pin == 2) { 82 } else if ((slot == 2 || slot == 6) && pin == 2) {
83 /* PCI-X Slot INTA */ 83 /* PCI-X Slot INTA */
84 irq = IRQ_IOP321_XINT3; 84 irq = IRQ_IOP32X_XINT3;
85 } else if ((slot == 2 || slot == 6) && pin == 3) { 85 } else if ((slot == 2 || slot == 6) && pin == 3) {
86 /* PCI-X Slot INTA */ 86 /* PCI-X Slot INTA */
87 irq = IRQ_IOP321_XINT0; 87 irq = IRQ_IOP32X_XINT0;
88 } else if ((slot == 2 || slot == 6) && pin == 4) { 88 } else if ((slot == 2 || slot == 6) && pin == 4) {
89 /* PCI-X Slot INTA */ 89 /* PCI-X Slot INTA */
90 irq = IRQ_IOP321_XINT1; 90 irq = IRQ_IOP32X_XINT1;
91 } else if (slot == 4 || slot == 8) { 91 } else if (slot == 4 || slot == 8) {
92 /* Gig-E */ 92 /* Gig-E */
93 irq = IRQ_IOP321_XINT0; 93 irq = IRQ_IOP32X_XINT0;
94 } else { 94 } else {
95 printk(KERN_ERR "iq80321_pci_map_irq() called for unknown " 95 printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
96 "device PCI:%d:%d:%d\n", dev->bus->number, 96 "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -148,7 +148,7 @@ static struct plat_serial8250_port iq80321_serial_port[] = {
148 { 148 {
149 .mapbase = IQ80321_UART, 149 .mapbase = IQ80321_UART,
150 .membase = (char *)IQ80321_UART, 150 .membase = (char *)IQ80321_UART,
151 .irq = IRQ_IOP321_XINT1, 151 .irq = IRQ_IOP32X_XINT1,
152 .flags = UPF_SKIP_TEST, 152 .flags = UPF_SKIP_TEST,
153 .iotype = UPIO_MEM, 153 .iotype = UPIO_MEM,
154 .regshift = 0, 154 .regshift = 0,
@@ -187,7 +187,7 @@ MACHINE_START(IQ80321, "Intel IQ80321")
187 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, 187 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
188 .boot_params = 0xa0000100, 188 .boot_params = 0xa0000100,
189 .map_io = iq80321_map_io, 189 .map_io = iq80321_map_io,
190 .init_irq = iop321_init_irq, 190 .init_irq = iop32x_init_irq,
191 .timer = &iq80321_timer, 191 .timer = &iq80321_timer,
192 .init_machine = iq80321_init_machine, 192 .init_machine = iq80321_init_machine,
193MACHINE_END 193MACHINE_END
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index ff049e02f5f7..21294be5a369 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-iop32x/irq.c 2 * arch/arm/mach-iop32x/irq.c
3 * 3 *
4 * Generic IOP32X IRQ handling functionality 4 * Generic IOP32X IRQ handling functionality
5 * 5 *
@@ -9,76 +9,66 @@
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 *
13 * Added IOP3XX chipset and IQ80321 board masking code.
14 *
15 */ 12 */
13
16#include <linux/init.h> 14#include <linux/init.h>
17#include <linux/interrupt.h> 15#include <linux/interrupt.h>
18#include <linux/list.h> 16#include <linux/list.h>
19
20#include <asm/mach/irq.h> 17#include <asm/mach/irq.h>
21#include <asm/irq.h> 18#include <asm/irq.h>
22#include <asm/hardware.h> 19#include <asm/hardware.h>
23
24#include <asm/mach-types.h> 20#include <asm/mach-types.h>
25 21
26static u32 iop321_mask /* = 0 */; 22static u32 iop32x_mask;
27 23
28static inline void intctl_write(u32 val) 24static inline void intctl_write(u32 val)
29{ 25{
30 iop3xx_cp6_enable(); 26 iop3xx_cp6_enable();
31 asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); 27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
32 iop3xx_cp6_disable(); 28 iop3xx_cp6_disable();
33} 29}
34 30
35static inline void intstr_write(u32 val) 31static inline void intstr_write(u32 val)
36{ 32{
37 iop3xx_cp6_enable(); 33 iop3xx_cp6_enable();
38 asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); 34 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
39 iop3xx_cp6_disable(); 35 iop3xx_cp6_disable();
40} 36}
41 37
42static void 38static void
43iop321_irq_mask (unsigned int irq) 39iop32x_irq_mask(unsigned int irq)
44{ 40{
45 41 iop32x_mask &= ~(1 << irq);
46 iop321_mask &= ~(1 << irq); 42 intctl_write(iop32x_mask);
47
48 intctl_write(iop321_mask);
49} 43}
50 44
51static void 45static void
52iop321_irq_unmask (unsigned int irq) 46iop32x_irq_unmask(unsigned int irq)
53{ 47{
54 iop321_mask |= (1 << irq); 48 iop32x_mask |= 1 << irq;
55 49 intctl_write(iop32x_mask);
56 intctl_write(iop321_mask);
57} 50}
58 51
59struct irq_chip ext_chip = { 52struct irq_chip ext_chip = {
60 .name = "IOP", 53 .name = "IOP32x",
61 .ack = iop321_irq_mask, 54 .ack = iop32x_irq_mask,
62 .mask = iop321_irq_mask, 55 .mask = iop32x_irq_mask,
63 .unmask = iop321_irq_unmask, 56 .unmask = iop32x_irq_unmask,
64}; 57};
65 58
66void __init iop321_init_irq(void) 59void __init iop32x_init_irq(void)
67{ 60{
68 unsigned int i; 61 int i;
69 62
70 intctl_write(0); // disable all interrupts 63 intctl_write(0);
71 intstr_write(0); // treat all as IRQ 64 intstr_write(0);
72 if(machine_is_iq80321() || 65 if (machine_is_iq80321() ||
73 machine_is_iq31244()) // all interrupts are inputs to chip 66 machine_is_iq31244())
74 *IOP3XX_PCIIRSR = 0x0f; 67 *IOP3XX_PCIIRSR = 0x0f;
75 68
76 for(i = 0; i < NR_IRQS; i++) 69 for (i = 0; i < NR_IRQS; i++) {
77 {
78 set_irq_chip(i, &ext_chip); 70 set_irq_chip(i, &ext_chip);
79 set_irq_handler(i, do_level_IRQ); 71 set_irq_handler(i, do_level_IRQ);
80 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 72 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
81
82 } 73 }
83} 74}
84