7 files changed, 257 insertions, 20 deletions

diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile
index 4185e0586c33..da1609dc0dee 100644
--- a/arch/arm/mach-iop13xx/Makefile
+++ b/arch/arm/mach-iop13xx/Makefile
@@ -7,5 +7,6 @@ obj-$(CONFIG_ARCH_IOP13XX) += setup.o
 obj-$(CONFIG_ARCH_IOP13XX) += irq.o
 obj-$(CONFIG_ARCH_IOP13XX) += pci.o
 obj-$(CONFIG_ARCH_IOP13XX) += io.o
+obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o
 obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
 obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index e79a1b62600f..5b22fdeca52c 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -41,7 +41,7 @@ void * __iomem __iop13xx_io(unsigned long io_addr)
 EXPORT_SYMBOL(__iop13xx_io);
 
 void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
-        unsigned long flags)
+        unsigned int mtype)
 {
         void __iomem * retval;
 
@@ -61,9 +61,9 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
                                  (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
                 break;
         case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
-                retval = __ioremap(IOP13XX_PBI_LOWER_MEM_PA +
-                                  (cookie - IOP13XX_PBI_LOWER_MEM_RA),
-                                  size, flags);
+                retval = __arm_ioremap(IOP13XX_PBI_LOWER_MEM_PA +
+                                       (cookie - IOP13XX_PBI_LOWER_MEM_RA),
+                                       size, mtype);
                 break;
         case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
                 retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
@@ -75,7 +75,7 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
                 retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
                 break;
         default:
-                retval = __ioremap(cookie, size, flags);
+                retval = __arm_ioremap(cookie, size, mtype);
         }
 
         return retval;
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index a519d707571c..268a8d84999c 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -75,11 +75,14 @@ static void __init iq81340mc_init(void)
 {
         iop13xx_platform_init();
         iq81340mc_pci_init();
+        iop13xx_add_tpmi_devices();
 }
 
 static void __init iq81340mc_timer_init(void)
 {
-        iop_init_time(400000000);
+        unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
+        printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq);
+        iop_init_time(bus_freq);
 }
 
 static struct sys_timer iq81340mc_timer = {
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 0e71fbcabe00..a51ffd2683e5 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -77,11 +77,14 @@ static void __init iq81340sc_init(void)
 {
         iop13xx_platform_init();
         iq81340sc_pci_init();
+        iop13xx_add_tpmi_devices();
 }
 
 static void __init iq81340sc_timer_init(void)
 {
-        iop_init_time(400000000);
+        unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
+        printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq);
+        iop_init_time(bus_freq);
 }
 
 static struct sys_timer iq81340sc_timer = {
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 89ec70ea3187..d1d0d32ca77c 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -88,9 +88,9 @@ void iop13xx_map_pci_memory(void)
 
                                 if (end) {
                                         iop13xx_atux_mem_base =
-                                        (u32) __ioremap_pfn(
+                                        (u32) __arm_ioremap_pfn(
                                         __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
-                                        , 0, iop13xx_atux_mem_size, 0);
+                                        , 0, iop13xx_atux_mem_size, MT_DEVICE);
                                         if (!iop13xx_atux_mem_base) {
                                                 printk("%s: atux allocation "
                                                        "failed\n", __FUNCTION__);
@@ -114,9 +114,9 @@ void iop13xx_map_pci_memory(void)
 
                                 if (end) {
                                         iop13xx_atue_mem_base =
-                                        (u32) __ioremap_pfn(
+                                        (u32) __arm_ioremap_pfn(
                                         __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
-                                        , 0, iop13xx_atue_mem_size, 0);
+                                        , 0, iop13xx_atue_mem_size, MT_DEVICE);
                                         if (!iop13xx_atue_mem_base) {
                                                 printk("%s: atue allocation "
                                                        "failed\n", __FUNCTION__);
@@ -1023,7 +1023,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                                   << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
                 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
 
-                res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
+                res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
                 res[0].end   = IOP13XX_PCIX_UPPER_IO_PA;
                 res[0].name  = "IQ81340 ATUX PCI I/O Space";
                 res[0].flags = IORESOURCE_IO;
@@ -1033,7 +1033,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                 res[1].name  = "IQ81340 ATUX PCI Memory Space";
                 res[1].flags = IORESOURCE_MEM;
                 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
-                sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
+                sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
                 break;
         case IOP13XX_INIT_ATU_ATUE:
                 /* Note: the function number field in the PCSR is ro */
@@ -1044,7 +1044,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
 
                 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
 
-                res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
+                res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
                 res[0].end   = IOP13XX_PCIE_UPPER_IO_PA;
                 res[0].name  = "IQ81340 ATUE PCI I/O Space";
                 res[0].flags = IORESOURCE_IO;
@@ -1054,7 +1054,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                 res[1].name  = "IQ81340 ATUE PCI Memory Space";
                 res[1].flags = IORESOURCE_MEM;
                 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
-                sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
+                sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
                 sys->map_irq = iop13xx_pcie_map_irq;
                 break;
         default:
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 9a46bcd5f18e..bc4871553f6a 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -258,15 +258,11 @@ void __init iop13xx_platform_init(void)
 
         if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
                 switch (iop13xx_dev_id()) {
-                /* enable both uarts on iop341 and iop342 */
+                /* enable both uarts on iop341 */
                 case 0x3380:
                 case 0x3384:
                 case 0x3388:
                 case 0x338c:
-                case 0x3382:
-                case 0x3386:
-                case 0x338a:
-                case 0x338e:
                         init_uart |= IOP13XX_INIT_UART_0;
                         init_uart |= IOP13XX_INIT_UART_1;
                         break;
diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c
new file mode 100644
index 000000000000..d3dc278213da
--- /dev/null
+++ b/arch/arm/mach-iop13xx/tpmi.c
@@ -0,0 +1,234 @@
+/*
+ * iop13xx tpmi device resources
+ * Copyright (c) 2005-2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+
+/* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
+#define IOP13XX_TPMI_MMR(dev)   IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
+#define IOP13XX_TPMI_MEM(dev)   IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13))
+#define IOP13XX_TPMI_CTRL(dev)  IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10))
+#define IOP13XX_TPMI_MMR_SIZE       (SZ_4K - 1)
+#define IOP13XX_TPMI_MEM_SIZE       (255)
+#define IOP13XX_TPMI_MEM_CTRL       (SZ_1K - 1)
+#define IOP13XX_TPMI_RESOURCE_MMR  0
+#define IOP13XX_TPMI_RESOURCE_MEM  1
+#define IOP13XX_TPMI_RESOURCE_CTRL 2
+#define IOP13XX_TPMI_RESOURCE_IRQ  3
+
+static struct resource iop13xx_tpmi_0_resources[] = {
+        [IOP13XX_TPMI_RESOURCE_MMR] = {
+                .start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */
+                .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_MEM] = {
+                .start = IOP13XX_TPMI_MEM(0),
+                .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_CTRL] = {
+                .start = IOP13XX_TPMI_CTRL(0),
+                .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_IRQ] = {
+                .start = IRQ_IOP13XX_TPMI0_OUT,
+                .end = IRQ_IOP13XX_TPMI0_OUT,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct resource iop13xx_tpmi_1_resources[] = {
+        [IOP13XX_TPMI_RESOURCE_MMR] = {
+                .start = IOP13XX_TPMI_MMR(1),
+                .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_MEM] = {
+                .start = IOP13XX_TPMI_MEM(1),
+                .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_CTRL] = {
+                .start = IOP13XX_TPMI_CTRL(1),
+                .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_IRQ] = {
+                .start = IRQ_IOP13XX_TPMI1_OUT,
+                .end = IRQ_IOP13XX_TPMI1_OUT,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct resource iop13xx_tpmi_2_resources[] = {
+        [IOP13XX_TPMI_RESOURCE_MMR] = {
+                .start = IOP13XX_TPMI_MMR(2),
+                .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_MEM] = {
+                .start = IOP13XX_TPMI_MEM(2),
+                .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_CTRL] = {
+                .start = IOP13XX_TPMI_CTRL(2),
+                .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_IRQ] = {
+                .start = IRQ_IOP13XX_TPMI2_OUT,
+                .end = IRQ_IOP13XX_TPMI2_OUT,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+static struct resource iop13xx_tpmi_3_resources[] = {
+        [IOP13XX_TPMI_RESOURCE_MMR] = {
+                .start = IOP13XX_TPMI_MMR(3),
+                .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_MEM] = {
+                .start = IOP13XX_TPMI_MEM(3),
+                .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_CTRL] = {
+                .start = IOP13XX_TPMI_CTRL(3),
+                .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
+                .flags = IORESOURCE_MEM,
+        },
+        [IOP13XX_TPMI_RESOURCE_IRQ] = {
+                .start = IRQ_IOP13XX_TPMI3_OUT,
+                .end = IRQ_IOP13XX_TPMI3_OUT,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+u64 iop13xx_tpmi_mask = DMA_64BIT_MASK;
+static struct platform_device iop13xx_tpmi_0_device = {
+        .name = "iop-tpmi",
+        .id = 0,
+        .num_resources = 4,
+        .resource = iop13xx_tpmi_0_resources,
+        .dev = {
+                .dma_mask          = &iop13xx_tpmi_mask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+        },
+};
+
+static struct platform_device iop13xx_tpmi_1_device = {
+        .name = "iop-tpmi",
+        .id = 1,
+        .num_resources = 4,
+        .resource = iop13xx_tpmi_1_resources,
+        .dev = {
+                .dma_mask          = &iop13xx_tpmi_mask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+        },
+};
+
+static struct platform_device iop13xx_tpmi_2_device = {
+        .name = "iop-tpmi",
+        .id = 2,
+        .num_resources = 4,
+        .resource = iop13xx_tpmi_2_resources,
+        .dev = {
+                .dma_mask          = &iop13xx_tpmi_mask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+        },
+};
+
+static struct platform_device iop13xx_tpmi_3_device = {
+        .name = "iop-tpmi",
+        .id = 3,
+        .num_resources = 4,
+        .resource = iop13xx_tpmi_3_resources,
+        .dev = {
+                .dma_mask          = &iop13xx_tpmi_mask,
+                .coherent_dma_mask = DMA_64BIT_MASK,
+        },
+};
+
+__init void iop13xx_add_tpmi_devices(void)
+{
+        unsigned short device_id;
+
+        /* tpmi's not present on iop341 or iop342 */
+        if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
+                /* ATUE must be present */
+                device_id = __raw_readw(IOP13XX_ATUE_DID);
+        else
+                /* ATUX must be present */
+                device_id = __raw_readw(IOP13XX_ATUX_DID);
+
+        switch (device_id) {
+        /* iop34[1|2] 0-tpmi */
+        case 0x3380:
+        case 0x3384:
+        case 0x3388:
+        case 0x338c:
+        case 0x3382:
+        case 0x3386:
+        case 0x338a:
+        case 0x338e:
+                return;
+        /* iop348 1-tpmi */
+        case 0x3310:
+        case 0x3312:
+        case 0x3314:
+        case 0x3318:
+        case 0x331a:
+        case 0x331c:
+        case 0x33c0:
+        case 0x33c2:
+        case 0x33c4:
+        case 0x33c8:
+        case 0x33ca:
+        case 0x33cc:
+        case 0x33b0:
+        case 0x33b2:
+        case 0x33b4:
+        case 0x33b8:
+        case 0x33ba:
+        case 0x33bc:
+        case 0x3320:
+        case 0x3322:
+        case 0x3324:
+        case 0x3328:
+        case 0x332a:
+        case 0x332c:
+                platform_device_register(&iop13xx_tpmi_0_device);
+                return;
+        default:
+                platform_device_register(&iop13xx_tpmi_0_device);
+                platform_device_register(&iop13xx_tpmi_1_device);
+                platform_device_register(&iop13xx_tpmi_2_device);
+                platform_device_register(&iop13xx_tpmi_3_device);
+                return;
+        }
+}