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-rw-r--r--arch/arm/mach-iop13xx/include/mach/io.h28
-rw-r--r--arch/arm/mach-iop13xx/include/mach/iop13xx.h48
-rw-r--r--arch/arm/mach-iop13xx/include/mach/memory.h14
-rw-r--r--arch/arm/mach-iop13xx/io.c35
-rw-r--r--arch/arm/mach-iop13xx/pci.c53
-rw-r--r--arch/arm/mach-iop13xx/pci.h4
-rw-r--r--arch/arm/mach-iop13xx/setup.c20
7 files changed, 50 insertions, 152 deletions
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
deleted file mode 100644
index f13188518025..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#define IO_SPACE_LIMIT 0xffffffff
23
24#define __io(a) __iop13xx_io(a)
25
26extern void __iomem * __iop13xx_io(unsigned long io_addr);
27
28#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index e190dcd7d72d..7480f58267aa 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -69,21 +69,11 @@ extern unsigned long get_iop_tick_rate(void);
69 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window 69 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
70 * 70 *
71 * IO MAP 71 * IO MAP
72 * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window 72 * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window
73 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window 73 * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window
74 */ 74 */
75#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
76#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL 75#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
77#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
78#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ 76#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
79#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
80#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
81 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
82#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
83 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
84#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
85 (IOP13XX_PCIX_LOWER_IO_PA\
86 - IOP13XX_PCIX_LOWER_IO_VA))
87 77
88#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL 78#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
89#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL 79#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
@@ -103,20 +93,8 @@ extern unsigned long get_iop_tick_rate(void);
103 IOP13XX_PCIX_LOWER_MEM_BA) 93 IOP13XX_PCIX_LOWER_MEM_BA)
104 94
105/* PCI-E ranges */ 95/* PCI-E ranges */
106#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
107#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL 96#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
108#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL 97#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */
109#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
110#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
111#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
112 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
113#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
114 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
115#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
116 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
117#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
118 (IOP13XX_PCIE_LOWER_IO_PA\
119 - IOP13XX_PCIE_LOWER_IO_VA))
120 98
121#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL 99#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
122#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL 100#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
@@ -148,18 +126,16 @@ extern unsigned long get_iop_tick_rate(void);
148 * IOP13XX chipset registers 126 * IOP13XX chipset registers
149 */ 127 */
150#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ 128#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
151#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ 129#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */
152#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 130#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
153#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ 131#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
154 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) 132 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
155#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ 133#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
156 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) 134 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
157#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ 135#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
158 (IOP13XX_PMMR_PHYS_MEM_BASE\ 136 + IOP13XX_PMMR_PHYS_MEM_BASE)
159 - IOP13XX_PMMR_VIRT_MEM_BASE)) 137#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
160#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ 138 + IOP13XX_PMMR_VIRT_MEM_BASE)
161 (IOP13XX_PMMR_PHYS_MEM_BASE\
162 - IOP13XX_PMMR_VIRT_MEM_BASE))
163#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) 139#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
164#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) 140#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
165#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) 141#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
@@ -169,10 +145,10 @@ extern unsigned long get_iop_tick_rate(void);
169#define IOP13XX_PMMR_SIZE 0x00080000 145#define IOP13XX_PMMR_SIZE 0x00080000
170 146
171/*=================== Defines for Platform Devices =====================*/ 147/*=================== Defines for Platform Devices =====================*/
172#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) 148#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
173#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) 149#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
174#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) 150#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
175#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) 151#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
176 152
177#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) 153#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
178#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) 154#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index 1afa99ef97fa..7c032d0ab24a 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -16,12 +16,12 @@
16#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) 16#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
17#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) 17#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
18 18
19static inline dma_addr_t __virt_to_lbus(unsigned long x) 19static inline dma_addr_t __virt_to_lbus(void __iomem *x)
20{ 20{
21 return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; 21 return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
22} 22}
23 23
24static inline unsigned long __lbus_to_virt(dma_addr_t x) 24static inline void __iomem *__lbus_to_virt(dma_addr_t x)
25{ 25{
26 return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE; 26 return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
27} 27}
@@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
38 38
39#define __arch_dma_to_virt(dev, addr) \ 39#define __arch_dma_to_virt(dev, addr) \
40 ({ \ 40 ({ \
41 unsigned long __virt; \ 41 void * __virt; \
42 dma_addr_t __dma = addr; \ 42 dma_addr_t __dma = addr; \
43 if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ 43 if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \
44 __virt = __lbus_to_virt(__dma); \ 44 __virt = __lbus_to_virt(__dma); \
45 else \ 45 else \
46 __virt = __phys_to_virt(__dma); \ 46 __virt = (void *)__phys_to_virt(__dma); \
47 (void *)__virt; \ 47 __virt; \
48 }) 48 })
49 49
50#define __arch_virt_to_dma(dev, addr) \ 50#define __arch_virt_to_dma(dev, addr) \
51 ({ \ 51 ({ \
52 unsigned long __virt = (unsigned long)addr; \ 52 void * __virt = addr; \
53 dma_addr_t __dma; \ 53 dma_addr_t __dma; \
54 if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ 54 if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \
55 __dma = __virt_to_lbus(__virt); \ 55 __dma = __virt_to_lbus(__virt); \
56 else \ 56 else \
57 __dma = __virt_to_phys(__virt); \ 57 __dma = __virt_to_phys((unsigned long)__virt); \
58 __dma; \ 58 __dma; \
59 }) 59 })
60 60
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 3c364198db9c..183dc8b5511b 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,25 +23,6 @@
23 23
24#include "pci.h" 24#include "pci.h"
25 25
26void * __iomem __iop13xx_io(unsigned long io_addr)
27{
28 void __iomem * io_virt;
29
30 switch (io_addr) {
31 case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
32 io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr);
33 break;
34 case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
35 io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr);
36 break;
37 default:
38 BUG();
39 }
40
41 return io_virt;
42}
43EXPORT_SYMBOL(__iop13xx_io);
44
45static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, 26static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
46 size_t size, unsigned int mtype, void *caller) 27 size_t size, unsigned int mtype, void *caller)
47{ 28{
@@ -52,14 +33,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
52 if (unlikely(!iop13xx_atux_mem_base)) 33 if (unlikely(!iop13xx_atux_mem_base))
53 retval = NULL; 34 retval = NULL;
54 else 35 else
55 retval = (void *)(iop13xx_atux_mem_base + 36 retval = (iop13xx_atux_mem_base +
56 (cookie - IOP13XX_PCIX_LOWER_MEM_RA)); 37 (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
57 break; 38 break;
58 case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA: 39 case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
59 if (unlikely(!iop13xx_atue_mem_base)) 40 if (unlikely(!iop13xx_atue_mem_base))
60 retval = NULL; 41 retval = NULL;
61 else 42 else
62 retval = (void *)(iop13xx_atue_mem_base + 43 retval = (iop13xx_atue_mem_base +
63 (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); 44 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
64 break; 45 break;
65 case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: 46 case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
@@ -67,14 +48,8 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
67 (cookie - IOP13XX_PBI_LOWER_MEM_RA), 48 (cookie - IOP13XX_PBI_LOWER_MEM_RA),
68 size, mtype, __builtin_return_address(0)); 49 size, mtype, __builtin_return_address(0));
69 break; 50 break;
70 case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
71 retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
72 break;
73 case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
74 retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
75 break;
76 case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: 51 case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
77 retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); 52 retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
78 break; 53 break;
79 default: 54 default:
80 retval = __arm_ioremap_caller(cookie, size, mtype, 55 retval = __arm_ioremap_caller(cookie, size, mtype,
@@ -99,9 +74,7 @@ static void __iop13xx_iounmap(volatile void __iomem *addr)
99 goto skip; 74 goto skip;
100 75
101 switch ((u32) addr) { 76 switch ((u32) addr) {
102 case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA: 77 case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
103 case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
104 case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
105 goto skip; 78 goto skip;
106 } 79 }
107 __iounmap(addr); 80 __iounmap(addr);
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 9d7f4cabe58b..2f28018c4447 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
36u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ 36u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
37static struct pci_bus *pci_bus_atux = 0; 37static struct pci_bus *pci_bus_atux = 0;
38static struct pci_bus *pci_bus_atue = 0; 38static struct pci_bus *pci_bus_atue = 0;
39u32 iop13xx_atue_mem_base; 39void __iomem *iop13xx_atue_mem_base;
40u32 iop13xx_atux_mem_base; 40void __iomem *iop13xx_atux_mem_base;
41size_t iop13xx_atue_mem_size; 41size_t iop13xx_atue_mem_size;
42size_t iop13xx_atux_mem_size; 42size_t iop13xx_atux_mem_size;
43 43
@@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void)
88 } 88 }
89 89
90 if (end) { 90 if (end) {
91 iop13xx_atux_mem_base = 91 iop13xx_atux_mem_base = __arm_ioremap_pfn(
92 (u32) __arm_ioremap_pfn(
93 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) 92 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
94 , 0, iop13xx_atux_mem_size, MT_DEVICE); 93 , 0, iop13xx_atux_mem_size, MT_DEVICE);
95 if (!iop13xx_atux_mem_base) { 94 if (!iop13xx_atux_mem_base) {
@@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void)
99 } 98 }
100 } else 99 } else
101 iop13xx_atux_mem_size = 0; 100 iop13xx_atux_mem_size = 0;
102 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", 101 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
103 __func__, atu, iop13xx_atux_mem_size, 102 __func__, atu, iop13xx_atux_mem_size,
104 iop13xx_atux_mem_base); 103 iop13xx_atux_mem_base);
105 break; 104 break;
@@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void)
114 } 113 }
115 114
116 if (end) { 115 if (end) {
117 iop13xx_atue_mem_base = 116 iop13xx_atue_mem_base = __arm_ioremap_pfn(
118 (u32) __arm_ioremap_pfn(
119 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) 117 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
120 , 0, iop13xx_atue_mem_size, MT_DEVICE); 118 , 0, iop13xx_atue_mem_size, MT_DEVICE);
121 if (!iop13xx_atue_mem_base) { 119 if (!iop13xx_atue_mem_base) {
@@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void)
125 } 123 }
126 } else 124 } else
127 iop13xx_atue_mem_size = 0; 125 iop13xx_atue_mem_size = 0;
128 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", 126 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
129 __func__, atu, iop13xx_atue_mem_size, 127 __func__, atu, iop13xx_atue_mem_size,
130 iop13xx_atue_mem_base); 128 iop13xx_atue_mem_base);
131 break; 129 break;
132 } 130 }
133 131
134 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n", 132 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
135 atu ? "ATUE" : "ATUX", 133 atu ? "ATUE" : "ATUX",
136 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / 134 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
137 SZ_1M, 135 SZ_1M,
@@ -970,7 +968,6 @@ void __init iop13xx_pci_init(void)
970 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); 968 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
971 969
972 /* Setup the Min Address for PCI memory... */ 970 /* Setup the Min Address for PCI memory... */
973 pcibios_min_io = 0;
974 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; 971 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
975 972
976 /* if Linux is given control of an ATU 973 /* if Linux is given control of an ATU
@@ -1003,7 +1000,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1003 if (nr > 1) 1000 if (nr > 1)
1004 return 0; 1001 return 0;
1005 1002
1006 res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); 1003 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1007 if (!res) 1004 if (!res)
1008 panic("PCI: unable to alloc resources"); 1005 panic("PCI: unable to alloc resources");
1009 1006
@@ -1042,17 +1039,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1042 << IOP13XX_ATUX_PCIXSR_FUNC_NUM; 1039 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1043 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); 1040 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1044 1041
1045 res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; 1042 pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
1046 res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
1047 res[0].name = "IQ81340 ATUX PCI I/O Space";
1048 res[0].flags = IORESOURCE_IO;
1049 1043
1050 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; 1044 res->start = IOP13XX_PCIX_LOWER_MEM_RA;
1051 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; 1045 res->end = IOP13XX_PCIX_UPPER_MEM_RA;
1052 res[1].name = "IQ81340 ATUX PCI Memory Space"; 1046 res->name = "IQ81340 ATUX PCI Memory Space";
1053 res[1].flags = IORESOURCE_MEM; 1047 res->flags = IORESOURCE_MEM;
1054 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; 1048 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1055 sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
1056 break; 1049 break;
1057 case IOP13XX_INIT_ATU_ATUE: 1050 case IOP13XX_INIT_ATU_ATUE:
1058 /* Note: the function number field in the PCSR is ro */ 1051 /* Note: the function number field in the PCSR is ro */
@@ -1063,17 +1056,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1063 1056
1064 __raw_writel(pcsr, IOP13XX_ATUE_PCSR); 1057 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1065 1058
1066 res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; 1059 pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
1067 res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
1068 res[0].name = "IQ81340 ATUE PCI I/O Space";
1069 res[0].flags = IORESOURCE_IO;
1070 1060
1071 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; 1061 res->start = IOP13XX_PCIE_LOWER_MEM_RA;
1072 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; 1062 res->end = IOP13XX_PCIE_UPPER_MEM_RA;
1073 res[1].name = "IQ81340 ATUE PCI Memory Space"; 1063 res->name = "IQ81340 ATUE PCI Memory Space";
1074 res[1].flags = IORESOURCE_MEM; 1064 res->flags = IORESOURCE_MEM;
1075 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; 1065 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1076 sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
1077 sys->map_irq = iop13xx_pcie_map_irq; 1066 sys->map_irq = iop13xx_pcie_map_irq;
1078 break; 1067 break;
1079 default: 1068 default:
@@ -1081,11 +1070,9 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1081 return 0; 1070 return 0;
1082 } 1071 }
1083 1072
1084 request_resource(&ioport_resource, &res[0]); 1073 request_resource(&iomem_resource, res);
1085 request_resource(&iomem_resource, &res[1]);
1086 1074
1087 pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); 1075 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
1088 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
1089 1076
1090 return 1; 1077 return 1;
1091} 1078}
diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h
index c70cf5b41e31..d45a80b3080e 100644
--- a/arch/arm/mach-iop13xx/pci.h
+++ b/arch/arm/mach-iop13xx/pci.h
@@ -1,6 +1,6 @@
1#include <linux/types.h> 1#include <linux/types.h>
2 2
3extern u32 iop13xx_atue_mem_base; 3extern void __iomem *iop13xx_atue_mem_base;
4extern u32 iop13xx_atux_mem_base; 4extern void __iomem *iop13xx_atux_mem_base;
5extern size_t iop13xx_atue_mem_size; 5extern size_t iop13xx_atue_mem_size;
6extern size_t iop13xx_atux_mem_size; 6extern size_t iop13xx_atux_mem_size;
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index daabb1fa6c2c..3181f61ea63e 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -36,20 +36,10 @@
36 */ 36 */
37static struct map_desc iop13xx_std_desc[] __initdata = { 37static struct map_desc iop13xx_std_desc[] __initdata = {
38 { /* mem mapped registers */ 38 { /* mem mapped registers */
39 .virtual = IOP13XX_PMMR_VIRT_MEM_BASE, 39 .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
40 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), 40 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
41 .length = IOP13XX_PMMR_SIZE, 41 .length = IOP13XX_PMMR_SIZE,
42 .type = MT_DEVICE, 42 .type = MT_DEVICE,
43 }, { /* PCIE IO space */
44 .virtual = IOP13XX_PCIE_LOWER_IO_VA,
45 .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
46 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
47 .type = MT_DEVICE,
48 }, { /* PCIX IO space */
49 .virtual = IOP13XX_PCIX_LOWER_IO_VA,
50 .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
51 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
52 .type = MT_DEVICE,
53 }, 43 },
54}; 44};
55 45
@@ -81,8 +71,8 @@ static struct resource iop13xx_uart1_resources[] = {
81 71
82static struct plat_serial8250_port iop13xx_uart0_data[] = { 72static struct plat_serial8250_port iop13xx_uart0_data[] = {
83 { 73 {
84 .membase = (char*)(IOP13XX_UART0_VIRT), 74 .membase = IOP13XX_UART0_VIRT,
85 .mapbase = (IOP13XX_UART0_PHYS), 75 .mapbase = IOP13XX_UART0_PHYS,
86 .irq = IRQ_IOP13XX_UART0, 76 .irq = IRQ_IOP13XX_UART0,
87 .uartclk = IOP13XX_UART_XTAL, 77 .uartclk = IOP13XX_UART_XTAL,
88 .regshift = 2, 78 .regshift = 2,
@@ -94,8 +84,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = {
94 84
95static struct plat_serial8250_port iop13xx_uart1_data[] = { 85static struct plat_serial8250_port iop13xx_uart1_data[] = {
96 { 86 {
97 .membase = (char*)(IOP13XX_UART1_VIRT), 87 .membase = IOP13XX_UART1_VIRT,
98 .mapbase = (IOP13XX_UART1_PHYS), 88 .mapbase = IOP13XX_UART1_PHYS,
99 .irq = IRQ_IOP13XX_UART1, 89 .irq = IRQ_IOP13XX_UART1,
100 .uartclk = IOP13XX_UART_XTAL, 90 .uartclk = IOP13XX_UART_XTAL,
101 .regshift = 2, 91 .regshift = 2,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 22:09:30 -0500