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-rw-r--r--arch/arm/mach-iop13xx/irq.c54
-rw-r--r--arch/arm/mach-iop13xx/msi.c18
-rw-r--r--arch/arm/mach-iop13xx/pci.c10
3 files changed, 23 insertions, 59 deletions
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index 5791addd436b..69f07b25b3c9 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -30,77 +30,65 @@
30 30
31/* INTCTL0 CP6 R0 Page 4 31/* INTCTL0 CP6 R0 Page 4
32 */ 32 */
33static inline u32 read_intctl_0(void) 33static u32 read_intctl_0(void)
34{ 34{
35 u32 val; 35 u32 val;
36 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); 36 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
37 return val; 37 return val;
38} 38}
39static inline void write_intctl_0(u32 val) 39static void write_intctl_0(u32 val)
40{ 40{
41 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); 41 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
42} 42}
43 43
44/* INTCTL1 CP6 R1 Page 4 44/* INTCTL1 CP6 R1 Page 4
45 */ 45 */
46static inline u32 read_intctl_1(void) 46static u32 read_intctl_1(void)
47{ 47{
48 u32 val; 48 u32 val;
49 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); 49 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
50 return val; 50 return val;
51} 51}
52static inline void write_intctl_1(u32 val) 52static void write_intctl_1(u32 val)
53{ 53{
54 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); 54 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
55} 55}
56 56
57/* INTCTL2 CP6 R2 Page 4 57/* INTCTL2 CP6 R2 Page 4
58 */ 58 */
59static inline u32 read_intctl_2(void) 59static u32 read_intctl_2(void)
60{ 60{
61 u32 val; 61 u32 val;
62 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); 62 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
63 return val; 63 return val;
64} 64}
65static inline void write_intctl_2(u32 val) 65static void write_intctl_2(u32 val)
66{ 66{
67 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); 67 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
68} 68}
69 69
70/* INTCTL3 CP6 R3 Page 4 70/* INTCTL3 CP6 R3 Page 4
71 */ 71 */
72static inline u32 read_intctl_3(void) 72static u32 read_intctl_3(void)
73{ 73{
74 u32 val; 74 u32 val;
75 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); 75 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
76 return val; 76 return val;
77} 77}
78static inline void write_intctl_3(u32 val) 78static void write_intctl_3(u32 val)
79{ 79{
80 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); 80 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
81} 81}
82 82
83/* INTSTR0 CP6 R0 Page 5 83/* INTSTR0 CP6 R0 Page 5
84 */ 84 */
85static inline u32 read_intstr_0(void) 85static void write_intstr_0(u32 val)
86{
87 u32 val;
88 asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
89 return val;
90}
91static inline void write_intstr_0(u32 val)
92{ 86{
93 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); 87 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
94} 88}
95 89
96/* INTSTR1 CP6 R1 Page 5 90/* INTSTR1 CP6 R1 Page 5
97 */ 91 */
98static inline u32 read_intstr_1(void)
99{
100 u32 val;
101 asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
102 return val;
103}
104static void write_intstr_1(u32 val) 92static void write_intstr_1(u32 val)
105{ 93{
106 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); 94 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
@@ -108,12 +96,6 @@ static void write_intstr_1(u32 val)
108 96
109/* INTSTR2 CP6 R2 Page 5 97/* INTSTR2 CP6 R2 Page 5
110 */ 98 */
111static inline u32 read_intstr_2(void)
112{
113 u32 val;
114 asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
115 return val;
116}
117static void write_intstr_2(u32 val) 99static void write_intstr_2(u32 val)
118{ 100{
119 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); 101 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
@@ -121,12 +103,6 @@ static void write_intstr_2(u32 val)
121 103
122/* INTSTR3 CP6 R3 Page 5 104/* INTSTR3 CP6 R3 Page 5
123 */ 105 */
124static inline u32 read_intstr_3(void)
125{
126 u32 val;
127 asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
128 return val;
129}
130static void write_intstr_3(u32 val) 106static void write_intstr_3(u32 val)
131{ 107{
132 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); 108 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
@@ -134,12 +110,6 @@ static void write_intstr_3(u32 val)
134 110
135/* INTBASE CP6 R0 Page 2 111/* INTBASE CP6 R0 Page 2
136 */ 112 */
137static inline u32 read_intbase(void)
138{
139 u32 val;
140 asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
141 return val;
142}
143static void write_intbase(u32 val) 113static void write_intbase(u32 val)
144{ 114{
145 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); 115 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
@@ -147,12 +117,6 @@ static void write_intbase(u32 val)
147 117
148/* INTSIZE CP6 R2 Page 2 118/* INTSIZE CP6 R2 Page 2
149 */ 119 */
150static inline u32 read_intsize(void)
151{
152 u32 val;
153 asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
154 return val;
155}
156static void write_intsize(u32 val) 120static void write_intsize(u32 val)
157{ 121{
158 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); 122 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index 2d2369302220..63ef1124ca5c 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -30,52 +30,52 @@ static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
30 30
31/* IMIPR0 CP6 R8 Page 1 31/* IMIPR0 CP6 R8 Page 1
32 */ 32 */
33static inline u32 read_imipr_0(void) 33static u32 read_imipr_0(void)
34{ 34{
35 u32 val; 35 u32 val;
36 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); 36 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
37 return val; 37 return val;
38} 38}
39static inline void write_imipr_0(u32 val) 39static void write_imipr_0(u32 val)
40{ 40{
41 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); 41 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
42} 42}
43 43
44/* IMIPR1 CP6 R9 Page 1 44/* IMIPR1 CP6 R9 Page 1
45 */ 45 */
46static inline u32 read_imipr_1(void) 46static u32 read_imipr_1(void)
47{ 47{
48 u32 val; 48 u32 val;
49 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); 49 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
50 return val; 50 return val;
51} 51}
52static inline void write_imipr_1(u32 val) 52static void write_imipr_1(u32 val)
53{ 53{
54 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); 54 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
55} 55}
56 56
57/* IMIPR2 CP6 R10 Page 1 57/* IMIPR2 CP6 R10 Page 1
58 */ 58 */
59static inline u32 read_imipr_2(void) 59static u32 read_imipr_2(void)
60{ 60{
61 u32 val; 61 u32 val;
62 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); 62 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
63 return val; 63 return val;
64} 64}
65static inline void write_imipr_2(u32 val) 65static void write_imipr_2(u32 val)
66{ 66{
67 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); 67 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
68} 68}
69 69
70/* IMIPR3 CP6 R11 Page 1 70/* IMIPR3 CP6 R11 Page 1
71 */ 71 */
72static inline u32 read_imipr_3(void) 72static u32 read_imipr_3(void)
73{ 73{
74 u32 val; 74 u32 val;
75 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); 75 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
76 return val; 76 return val;
77} 77}
78static inline void write_imipr_3(u32 val) 78static void write_imipr_3(u32 val)
79{ 79{
80 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); 80 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
81} 81}
@@ -190,5 +190,5 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
190 write_msi_msg(irq, &msg); 190 write_msi_msg(irq, &msg);
191 set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); 191 set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
192 192
193 return irq; 193 return 0;
194} 194}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 6baeb26c3aa3..9d63d7f260ca 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -145,7 +145,7 @@ void iop13xx_map_pci_memory(void)
145 } 145 }
146} 146}
147 147
148static inline int iop13xx_atu_function(int atu) 148static int iop13xx_atu_function(int atu)
149{ 149{
150 int func = 0; 150 int func = 0;
151 /* the function number depends on the value of the 151 /* the function number depends on the value of the
@@ -260,7 +260,7 @@ static int iop13xx_atux_pci_status(int clear)
260 * data. Note that the data dependency on %0 encourages an abort 260 * data. Note that the data dependency on %0 encourages an abort
261 * to be detected before we return. 261 * to be detected before we return.
262 */ 262 */
263static inline u32 iop13xx_atux_read(unsigned long addr) 263static u32 iop13xx_atux_read(unsigned long addr)
264{ 264{
265 u32 val; 265 u32 val;
266 266
@@ -388,7 +388,7 @@ static int iop13xx_atue_pci_status(int clear)
388 return err; 388 return err;
389} 389}
390 390
391static inline int __init 391static int
392iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) 392iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
393{ 393{
394 WARN_ON(idsel != 0); 394 WARN_ON(idsel != 0);
@@ -402,7 +402,7 @@ iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
402 } 402 }
403} 403}
404 404
405static inline u32 iop13xx_atue_read(unsigned long addr) 405static u32 iop13xx_atue_read(unsigned long addr)
406{ 406{
407 u32 val; 407 u32 val;
408 408
@@ -990,7 +990,7 @@ void __init iop13xx_pci_init(void)
990 "imprecise external abort"); 990 "imprecise external abort");
991} 991}
992 992
993/* intialize the pci memory space. handle any combination of 993/* initialize the pci memory space. handle any combination of
994 * atue and atux enabled/disabled 994 * atue and atux enabled/disabled
995 */ 995 */
996int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) 996int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 21:21:33 -0500