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Diffstat (limited to 'arch/arm/mach-iop13xx/irq.c')
-rw-r--r-- | arch/arm/mach-iop13xx/irq.c | 286 |
1 files changed, 286 insertions, 0 deletions
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c new file mode 100644 index 000000000000..c4d9c8c5579c --- /dev/null +++ b/arch/arm/mach-iop13xx/irq.c | |||
@@ -0,0 +1,286 @@ | |||
1 | /* | ||
2 | * iop13xx IRQ handling / support functions | ||
3 | * Copyright (c) 2005-2006, Intel Corporation. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it | ||
6 | * under the terms and conditions of the GNU General Public License, | ||
7 | * version 2, as published by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
12 | * more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along with | ||
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | ||
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | ||
17 | * | ||
18 | */ | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/interrupt.h> | ||
21 | #include <linux/list.h> | ||
22 | #include <linux/sysctl.h> | ||
23 | #include <asm/uaccess.h> | ||
24 | #include <asm/mach/irq.h> | ||
25 | #include <asm/irq.h> | ||
26 | #include <asm/hardware.h> | ||
27 | #include <asm/mach-types.h> | ||
28 | #include <asm/arch/irqs.h> | ||
29 | |||
30 | /* INTCTL0 CP6 R0 Page 4 | ||
31 | */ | ||
32 | static inline u32 read_intctl_0(void) | ||
33 | { | ||
34 | u32 val; | ||
35 | asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); | ||
36 | return val; | ||
37 | } | ||
38 | static inline void write_intctl_0(u32 val) | ||
39 | { | ||
40 | asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); | ||
41 | } | ||
42 | |||
43 | /* INTCTL1 CP6 R1 Page 4 | ||
44 | */ | ||
45 | static inline u32 read_intctl_1(void) | ||
46 | { | ||
47 | u32 val; | ||
48 | asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); | ||
49 | return val; | ||
50 | } | ||
51 | static inline void write_intctl_1(u32 val) | ||
52 | { | ||
53 | asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); | ||
54 | } | ||
55 | |||
56 | /* INTCTL2 CP6 R2 Page 4 | ||
57 | */ | ||
58 | static inline u32 read_intctl_2(void) | ||
59 | { | ||
60 | u32 val; | ||
61 | asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); | ||
62 | return val; | ||
63 | } | ||
64 | static inline void write_intctl_2(u32 val) | ||
65 | { | ||
66 | asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); | ||
67 | } | ||
68 | |||
69 | /* INTCTL3 CP6 R3 Page 4 | ||
70 | */ | ||
71 | static inline u32 read_intctl_3(void) | ||
72 | { | ||
73 | u32 val; | ||
74 | asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); | ||
75 | return val; | ||
76 | } | ||
77 | static inline void write_intctl_3(u32 val) | ||
78 | { | ||
79 | asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); | ||
80 | } | ||
81 | |||
82 | /* INTSTR0 CP6 R0 Page 5 | ||
83 | */ | ||
84 | static inline u32 read_intstr_0(void) | ||
85 | { | ||
86 | u32 val; | ||
87 | asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val)); | ||
88 | return val; | ||
89 | } | ||
90 | static inline void write_intstr_0(u32 val) | ||
91 | { | ||
92 | asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); | ||
93 | } | ||
94 | |||
95 | /* INTSTR1 CP6 R1 Page 5 | ||
96 | */ | ||
97 | static inline u32 read_intstr_1(void) | ||
98 | { | ||
99 | u32 val; | ||
100 | asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val)); | ||
101 | return val; | ||
102 | } | ||
103 | static void write_intstr_1(u32 val) | ||
104 | { | ||
105 | asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); | ||
106 | } | ||
107 | |||
108 | /* INTSTR2 CP6 R2 Page 5 | ||
109 | */ | ||
110 | static inline u32 read_intstr_2(void) | ||
111 | { | ||
112 | u32 val; | ||
113 | asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val)); | ||
114 | return val; | ||
115 | } | ||
116 | static void write_intstr_2(u32 val) | ||
117 | { | ||
118 | asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); | ||
119 | } | ||
120 | |||
121 | /* INTSTR3 CP6 R3 Page 5 | ||
122 | */ | ||
123 | static inline u32 read_intstr_3(void) | ||
124 | { | ||
125 | u32 val; | ||
126 | asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val)); | ||
127 | return val; | ||
128 | } | ||
129 | static void write_intstr_3(u32 val) | ||
130 | { | ||
131 | asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); | ||
132 | } | ||
133 | |||
134 | /* INTBASE CP6 R0 Page 2 | ||
135 | */ | ||
136 | static inline u32 read_intbase(void) | ||
137 | { | ||
138 | u32 val; | ||
139 | asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val)); | ||
140 | return val; | ||
141 | } | ||
142 | static void write_intbase(u32 val) | ||
143 | { | ||
144 | asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); | ||
145 | } | ||
146 | |||
147 | /* INTSIZE CP6 R2 Page 2 | ||
148 | */ | ||
149 | static inline u32 read_intsize(void) | ||
150 | { | ||
151 | u32 val; | ||
152 | asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val)); | ||
153 | return val; | ||
154 | } | ||
155 | static void write_intsize(u32 val) | ||
156 | { | ||
157 | asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); | ||
158 | } | ||
159 | |||
160 | /* 0 = Interrupt Masked and 1 = Interrupt not masked */ | ||
161 | static void | ||
162 | iop13xx_irq_mask0 (unsigned int irq) | ||
163 | { | ||
164 | u32 cp_flags = iop13xx_cp6_save(); | ||
165 | write_intctl_0(read_intctl_0() & ~(1 << (irq - 0))); | ||
166 | iop13xx_cp6_restore(cp_flags); | ||
167 | } | ||
168 | |||
169 | static void | ||
170 | iop13xx_irq_mask1 (unsigned int irq) | ||
171 | { | ||
172 | u32 cp_flags = iop13xx_cp6_save(); | ||
173 | write_intctl_1(read_intctl_1() & ~(1 << (irq - 32))); | ||
174 | iop13xx_cp6_restore(cp_flags); | ||
175 | } | ||
176 | |||
177 | static void | ||
178 | iop13xx_irq_mask2 (unsigned int irq) | ||
179 | { | ||
180 | u32 cp_flags = iop13xx_cp6_save(); | ||
181 | write_intctl_2(read_intctl_2() & ~(1 << (irq - 64))); | ||
182 | iop13xx_cp6_restore(cp_flags); | ||
183 | } | ||
184 | |||
185 | static void | ||
186 | iop13xx_irq_mask3 (unsigned int irq) | ||
187 | { | ||
188 | u32 cp_flags = iop13xx_cp6_save(); | ||
189 | write_intctl_3(read_intctl_3() & ~(1 << (irq - 96))); | ||
190 | iop13xx_cp6_restore(cp_flags); | ||
191 | } | ||
192 | |||
193 | static void | ||
194 | iop13xx_irq_unmask0(unsigned int irq) | ||
195 | { | ||
196 | u32 cp_flags = iop13xx_cp6_save(); | ||
197 | write_intctl_0(read_intctl_0() | (1 << (irq - 0))); | ||
198 | iop13xx_cp6_restore(cp_flags); | ||
199 | } | ||
200 | |||
201 | static void | ||
202 | iop13xx_irq_unmask1(unsigned int irq) | ||
203 | { | ||
204 | u32 cp_flags = iop13xx_cp6_save(); | ||
205 | write_intctl_1(read_intctl_1() | (1 << (irq - 32))); | ||
206 | iop13xx_cp6_restore(cp_flags); | ||
207 | } | ||
208 | |||
209 | static void | ||
210 | iop13xx_irq_unmask2(unsigned int irq) | ||
211 | { | ||
212 | u32 cp_flags = iop13xx_cp6_save(); | ||
213 | write_intctl_2(read_intctl_2() | (1 << (irq - 64))); | ||
214 | iop13xx_cp6_restore(cp_flags); | ||
215 | } | ||
216 | |||
217 | static void | ||
218 | iop13xx_irq_unmask3(unsigned int irq) | ||
219 | { | ||
220 | u32 cp_flags = iop13xx_cp6_save(); | ||
221 | write_intctl_3(read_intctl_3() | (1 << (irq - 96))); | ||
222 | iop13xx_cp6_restore(cp_flags); | ||
223 | } | ||
224 | |||
225 | static struct irqchip iop13xx_irqchip0 = { | ||
226 | .ack = iop13xx_irq_mask0, | ||
227 | .mask = iop13xx_irq_mask0, | ||
228 | .unmask = iop13xx_irq_unmask0, | ||
229 | }; | ||
230 | |||
231 | static struct irqchip iop13xx_irqchip1 = { | ||
232 | .ack = iop13xx_irq_mask1, | ||
233 | .mask = iop13xx_irq_mask1, | ||
234 | .unmask = iop13xx_irq_unmask1, | ||
235 | }; | ||
236 | |||
237 | static struct irqchip iop13xx_irqchip2 = { | ||
238 | .ack = iop13xx_irq_mask2, | ||
239 | .mask = iop13xx_irq_mask2, | ||
240 | .unmask = iop13xx_irq_unmask2, | ||
241 | }; | ||
242 | |||
243 | static struct irqchip iop13xx_irqchip3 = { | ||
244 | .ack = iop13xx_irq_mask3, | ||
245 | .mask = iop13xx_irq_mask3, | ||
246 | .unmask = iop13xx_irq_unmask3, | ||
247 | }; | ||
248 | |||
249 | void __init iop13xx_init_irq(void) | ||
250 | { | ||
251 | unsigned int i; | ||
252 | |||
253 | u32 cp_flags = iop13xx_cp6_save(); | ||
254 | |||
255 | /* disable all interrupts */ | ||
256 | write_intctl_0(0); | ||
257 | write_intctl_1(0); | ||
258 | write_intctl_2(0); | ||
259 | write_intctl_3(0); | ||
260 | |||
261 | /* treat all as IRQ */ | ||
262 | write_intstr_0(0); | ||
263 | write_intstr_1(0); | ||
264 | write_intstr_2(0); | ||
265 | write_intstr_3(0); | ||
266 | |||
267 | /* initialize the interrupt vector generator */ | ||
268 | write_intbase(INTBASE); | ||
269 | write_intsize(INTSIZE_4); | ||
270 | |||
271 | for(i = 0; i < NR_IOP13XX_IRQS; i++) { | ||
272 | if (i < 32) | ||
273 | set_irq_chip(i, &iop13xx_irqchip0); | ||
274 | else if (i < 64) | ||
275 | set_irq_chip(i, &iop13xx_irqchip1); | ||
276 | else if (i < 96) | ||
277 | set_irq_chip(i, &iop13xx_irqchip2); | ||
278 | else | ||
279 | set_irq_chip(i, &iop13xx_irqchip3); | ||
280 | |||
281 | set_irq_handler(i, do_level_IRQ); | ||
282 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | ||
283 | } | ||
284 | |||
285 | iop13xx_cp6_restore(cp_flags); | ||
286 | } | ||