diff options
Diffstat (limited to 'arch/arm/mach-integrator')
-rw-r--r-- | arch/arm/mach-integrator/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-integrator/common.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-integrator/core.c | 7 | ||||
-rw-r--r-- | arch/arm/mach-integrator/impd1.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-integrator/include/mach/cm.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-integrator/integrator_ap.c | 44 | ||||
-rw-r--r-- | arch/arm/mach-integrator/integrator_cp.c | 239 |
7 files changed, 92 insertions, 209 deletions
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 769b0f10c834..d701d32a07f1 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig | |||
@@ -13,6 +13,7 @@ config ARCH_INTEGRATOR_CP | |||
13 | bool "Support Integrator/CP platform" | 13 | bool "Support Integrator/CP platform" |
14 | select ARCH_CINTEGRATOR | 14 | select ARCH_CINTEGRATOR |
15 | select ARM_TIMER_SP804 | 15 | select ARM_TIMER_SP804 |
16 | select PLAT_VERSATILE_CLCD | ||
16 | help | 17 | help |
17 | Include support for the ARM(R) Integrator CP platform. | 18 | Include support for the ARM(R) Integrator CP platform. |
18 | 19 | ||
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h index 5f96e1518aa9..a08f9b0299df 100644 --- a/arch/arm/mach-integrator/common.h +++ b/arch/arm/mach-integrator/common.h | |||
@@ -1 +1,2 @@ | |||
1 | void integrator_init_early(void); | ||
1 | void integrator_reserve(void); | 2 | void integrator_reserve(void); |
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index b8e884b450da..77315b995681 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c | |||
@@ -144,12 +144,15 @@ static struct clk_lookup lookups[] = { | |||
144 | } | 144 | } |
145 | }; | 145 | }; |
146 | 146 | ||
147 | void __init integrator_init_early(void) | ||
148 | { | ||
149 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
150 | } | ||
151 | |||
147 | static int __init integrator_init(void) | 152 | static int __init integrator_init(void) |
148 | { | 153 | { |
149 | int i; | 154 | int i; |
150 | 155 | ||
151 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
152 | |||
153 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 156 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
154 | struct amba_device *d = amba_devs[i]; | 157 | struct amba_device *d = amba_devs[i]; |
155 | amba_device_register(d, &iomem_resource); | 158 | amba_device_register(d, &iomem_resource); |
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index 5db574f8ae3f..8cbb75a96bd4 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c | |||
@@ -121,6 +121,7 @@ static struct clcd_panel vga = { | |||
121 | .height = -1, | 121 | .height = -1, |
122 | .tim2 = TIM2_BCD | TIM2_IPC, | 122 | .tim2 = TIM2_BCD | TIM2_IPC, |
123 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | 123 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), |
124 | .caps = CLCD_CAP_5551, | ||
124 | .connector = IMPD1_CTRL_DISP_VGA, | 125 | .connector = IMPD1_CTRL_DISP_VGA, |
125 | .bpp = 16, | 126 | .bpp = 16, |
126 | .grayscale = 0, | 127 | .grayscale = 0, |
@@ -149,6 +150,7 @@ static struct clcd_panel svga = { | |||
149 | .tim2 = TIM2_BCD, | 150 | .tim2 = TIM2_BCD, |
150 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | 151 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), |
151 | .connector = IMPD1_CTRL_DISP_VGA, | 152 | .connector = IMPD1_CTRL_DISP_VGA, |
153 | .caps = CLCD_CAP_5551, | ||
152 | .bpp = 16, | 154 | .bpp = 16, |
153 | .grayscale = 0, | 155 | .grayscale = 0, |
154 | }; | 156 | }; |
@@ -175,6 +177,7 @@ static struct clcd_panel prospector = { | |||
175 | .height = -1, | 177 | .height = -1, |
176 | .tim2 = TIM2_BCD, | 178 | .tim2 = TIM2_BCD, |
177 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | 179 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), |
180 | .caps = CLCD_CAP_5551, | ||
178 | .fixedtimings = 1, | 181 | .fixedtimings = 1, |
179 | .connector = IMPD1_CTRL_DISP_LCD, | 182 | .connector = IMPD1_CTRL_DISP_LCD, |
180 | .bpp = 16, | 183 | .bpp = 16, |
@@ -206,6 +209,7 @@ static struct clcd_panel ltm10c209 = { | |||
206 | .height = -1, | 209 | .height = -1, |
207 | .tim2 = TIM2_BCD, | 210 | .tim2 = TIM2_BCD, |
208 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | 211 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), |
212 | .caps = CLCD_CAP_5551, | ||
209 | .fixedtimings = 1, | 213 | .fixedtimings = 1, |
210 | .connector = IMPD1_CTRL_DISP_LCD, | 214 | .connector = IMPD1_CTRL_DISP_LCD, |
211 | .bpp = 16, | 215 | .bpp = 16, |
@@ -279,6 +283,7 @@ static void impd1fb_clcd_remove(struct clcd_fb *fb) | |||
279 | 283 | ||
280 | static struct clcd_board impd1_clcd_data = { | 284 | static struct clcd_board impd1_clcd_data = { |
281 | .name = "IM-PD/1", | 285 | .name = "IM-PD/1", |
286 | .caps = CLCD_CAP_5551 | CLCD_CAP_888, | ||
282 | .check = clcdfb_check, | 287 | .check = clcdfb_check, |
283 | .decode = clcdfb_decode, | 288 | .decode = clcdfb_decode, |
284 | .disable = impd1fb_clcd_disable, | 289 | .disable = impd1fb_clcd_disable, |
diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/include/mach/cm.h index 1ab353e23595..445d57adb043 100644 --- a/arch/arm/mach-integrator/include/mach/cm.h +++ b/arch/arm/mach-integrator/include/mach/cm.h | |||
@@ -24,9 +24,9 @@ void cm_control(u32, u32); | |||
24 | #define CM_CTRL_LCDBIASDN (1 << 10) | 24 | #define CM_CTRL_LCDBIASDN (1 << 10) |
25 | #define CM_CTRL_LCDMUXSEL_MASK (7 << 11) | 25 | #define CM_CTRL_LCDMUXSEL_MASK (7 << 11) |
26 | #define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11) | 26 | #define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11) |
27 | #define CM_CTRL_LCDMUXSEL_VGA_16BPP (2 << 11) | 27 | #define CM_CTRL_LCDMUXSEL_VGA565_TFT555 (2 << 11) |
28 | #define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11) | 28 | #define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11) |
29 | #define CM_CTRL_LCDMUXSEL_VGA_8421BPP (4 << 11) | 29 | #define CM_CTRL_LCDMUXSEL_VGA555_TFT555 (4 << 11) |
30 | #define CM_CTRL_LCDEN0 (1 << 14) | 30 | #define CM_CTRL_LCDEN0 (1 << 14) |
31 | #define CM_CTRL_LCDEN1 (1 << 15) | 31 | #define CM_CTRL_LCDEN1 (1 << 15) |
32 | #define CM_CTRL_STATIC1 (1 << 16) | 32 | #define CM_CTRL_STATIC1 (1 << 16) |
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index b666443b5cbb..980803ff348c 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c | |||
@@ -48,6 +48,8 @@ | |||
48 | #include <asm/mach/map.h> | 48 | #include <asm/mach/map.h> |
49 | #include <asm/mach/time.h> | 49 | #include <asm/mach/time.h> |
50 | 50 | ||
51 | #include <plat/fpga-irq.h> | ||
52 | |||
51 | #include "common.h" | 53 | #include "common.h" |
52 | 54 | ||
53 | /* | 55 | /* |
@@ -57,10 +59,10 @@ | |||
57 | * Setup a VA for the Integrator interrupt controller (for header #0, | 59 | * Setup a VA for the Integrator interrupt controller (for header #0, |
58 | * just for now). | 60 | * just for now). |
59 | */ | 61 | */ |
60 | #define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) | 62 | #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) |
61 | #define VA_SC_BASE IO_ADDRESS(INTEGRATOR_SC_BASE) | 63 | #define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE) |
62 | #define VA_EBI_BASE IO_ADDRESS(INTEGRATOR_EBI_BASE) | 64 | #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE) |
63 | #define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_IC) | 65 | #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC) |
64 | 66 | ||
65 | /* | 67 | /* |
66 | * Logical Physical | 68 | * Logical Physical |
@@ -156,27 +158,14 @@ static void __init ap_map_io(void) | |||
156 | 158 | ||
157 | #define INTEGRATOR_SC_VALID_INT 0x003fffff | 159 | #define INTEGRATOR_SC_VALID_INT 0x003fffff |
158 | 160 | ||
159 | static void sc_mask_irq(struct irq_data *d) | 161 | static struct fpga_irq_data sc_irq_data = { |
160 | { | 162 | .base = VA_IC_BASE, |
161 | writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_CLEAR); | 163 | .irq_start = 0, |
162 | } | 164 | .chip.name = "SC", |
163 | |||
164 | static void sc_unmask_irq(struct irq_data *d) | ||
165 | { | ||
166 | writel(1 << d->irq, VA_IC_BASE + IRQ_ENABLE_SET); | ||
167 | } | ||
168 | |||
169 | static struct irq_chip sc_chip = { | ||
170 | .name = "SC", | ||
171 | .irq_ack = sc_mask_irq, | ||
172 | .irq_mask = sc_mask_irq, | ||
173 | .irq_unmask = sc_unmask_irq, | ||
174 | }; | 165 | }; |
175 | 166 | ||
176 | static void __init ap_init_irq(void) | 167 | static void __init ap_init_irq(void) |
177 | { | 168 | { |
178 | unsigned int i; | ||
179 | |||
180 | /* Disable all interrupts initially. */ | 169 | /* Disable all interrupts initially. */ |
181 | /* Do the core module ones */ | 170 | /* Do the core module ones */ |
182 | writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | 171 | writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); |
@@ -185,13 +174,7 @@ static void __init ap_init_irq(void) | |||
185 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); | 174 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); |
186 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | 175 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); |
187 | 176 | ||
188 | for (i = 0; i < NR_IRQS; i++) { | 177 | fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data); |
189 | if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) { | ||
190 | set_irq_chip(i, &sc_chip); | ||
191 | set_irq_handler(i, handle_level_irq); | ||
192 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | ||
193 | } | ||
194 | } | ||
195 | } | 178 | } |
196 | 179 | ||
197 | #ifdef CONFIG_PM | 180 | #ifdef CONFIG_PM |
@@ -282,7 +265,7 @@ static void ap_flash_exit(void) | |||
282 | 265 | ||
283 | static void ap_flash_set_vpp(int on) | 266 | static void ap_flash_set_vpp(int on) |
284 | { | 267 | { |
285 | unsigned long reg = on ? SC_CTRLS : SC_CTRLC; | 268 | void __iomem *reg = on ? SC_CTRLS : SC_CTRLC; |
286 | 269 | ||
287 | writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); | 270 | writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); |
288 | } | 271 | } |
@@ -499,8 +482,9 @@ static struct sys_timer ap_timer = { | |||
499 | MACHINE_START(INTEGRATOR, "ARM-Integrator") | 482 | MACHINE_START(INTEGRATOR, "ARM-Integrator") |
500 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | 483 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
501 | .boot_params = 0x00000100, | 484 | .boot_params = 0x00000100, |
502 | .map_io = ap_map_io, | ||
503 | .reserve = integrator_reserve, | 485 | .reserve = integrator_reserve, |
486 | .map_io = ap_map_io, | ||
487 | .init_early = integrator_init_early, | ||
504 | .init_irq = ap_init_irq, | 488 | .init_irq = ap_init_irq, |
505 | .timer = &ap_timer, | 489 | .timer = &ap_timer, |
506 | .init_machine = ap_init, | 490 | .init_machine = ap_init, |
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index e9327da1382e..9e3ce26023e8 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
@@ -42,6 +42,10 @@ | |||
42 | 42 | ||
43 | #include <asm/hardware/timer-sp.h> | 43 | #include <asm/hardware/timer-sp.h> |
44 | 44 | ||
45 | #include <plat/clcd.h> | ||
46 | #include <plat/fpga-irq.h> | ||
47 | #include <plat/sched_clock.h> | ||
48 | |||
45 | #include "common.h" | 49 | #include "common.h" |
46 | 50 | ||
47 | #define INTCP_PA_FLASH_BASE 0x24000000 | 51 | #define INTCP_PA_FLASH_BASE 0x24000000 |
@@ -49,9 +53,9 @@ | |||
49 | 53 | ||
50 | #define INTCP_PA_CLCD_BASE 0xc0000000 | 54 | #define INTCP_PA_CLCD_BASE 0xc0000000 |
51 | 55 | ||
52 | #define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40) | 56 | #define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40) |
53 | #define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) | 57 | #define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE) |
54 | #define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE) | 58 | #define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE) |
55 | 59 | ||
56 | #define INTCP_ETH_SIZE 0x10 | 60 | #define INTCP_ETH_SIZE 0x10 |
57 | 61 | ||
@@ -139,129 +143,48 @@ static void __init intcp_map_io(void) | |||
139 | iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); | 143 | iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); |
140 | } | 144 | } |
141 | 145 | ||
142 | #define cic_writel __raw_writel | 146 | static struct fpga_irq_data cic_irq_data = { |
143 | #define cic_readl __raw_readl | 147 | .base = INTCP_VA_CIC_BASE, |
144 | #define pic_writel __raw_writel | 148 | .irq_start = IRQ_CIC_START, |
145 | #define pic_readl __raw_readl | 149 | .chip.name = "CIC", |
146 | #define sic_writel __raw_writel | ||
147 | #define sic_readl __raw_readl | ||
148 | |||
149 | static void cic_mask_irq(struct irq_data *d) | ||
150 | { | ||
151 | unsigned int irq = d->irq - IRQ_CIC_START; | ||
152 | cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | ||
153 | } | ||
154 | |||
155 | static void cic_unmask_irq(struct irq_data *d) | ||
156 | { | ||
157 | unsigned int irq = d->irq - IRQ_CIC_START; | ||
158 | cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET); | ||
159 | } | ||
160 | |||
161 | static struct irq_chip cic_chip = { | ||
162 | .name = "CIC", | ||
163 | .irq_ack = cic_mask_irq, | ||
164 | .irq_mask = cic_mask_irq, | ||
165 | .irq_unmask = cic_unmask_irq, | ||
166 | }; | 150 | }; |
167 | 151 | ||
168 | static void pic_mask_irq(struct irq_data *d) | 152 | static struct fpga_irq_data pic_irq_data = { |
169 | { | 153 | .base = INTCP_VA_PIC_BASE, |
170 | unsigned int irq = d->irq - IRQ_PIC_START; | 154 | .irq_start = IRQ_PIC_START, |
171 | pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); | 155 | .chip.name = "PIC", |
172 | } | ||
173 | |||
174 | static void pic_unmask_irq(struct irq_data *d) | ||
175 | { | ||
176 | unsigned int irq = d->irq - IRQ_PIC_START; | ||
177 | pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET); | ||
178 | } | ||
179 | |||
180 | static struct irq_chip pic_chip = { | ||
181 | .name = "PIC", | ||
182 | .irq_ack = pic_mask_irq, | ||
183 | .irq_mask = pic_mask_irq, | ||
184 | .irq_unmask = pic_unmask_irq, | ||
185 | }; | 156 | }; |
186 | 157 | ||
187 | static void sic_mask_irq(struct irq_data *d) | 158 | static struct fpga_irq_data sic_irq_data = { |
188 | { | 159 | .base = INTCP_VA_SIC_BASE, |
189 | unsigned int irq = d->irq - IRQ_SIC_START; | 160 | .irq_start = IRQ_SIC_START, |
190 | sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); | 161 | .chip.name = "SIC", |
191 | } | ||
192 | |||
193 | static void sic_unmask_irq(struct irq_data *d) | ||
194 | { | ||
195 | unsigned int irq = d->irq - IRQ_SIC_START; | ||
196 | sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET); | ||
197 | } | ||
198 | |||
199 | static struct irq_chip sic_chip = { | ||
200 | .name = "SIC", | ||
201 | .irq_ack = sic_mask_irq, | ||
202 | .irq_mask = sic_mask_irq, | ||
203 | .irq_unmask = sic_unmask_irq, | ||
204 | }; | 162 | }; |
205 | 163 | ||
206 | static void | ||
207 | sic_handle_irq(unsigned int irq, struct irq_desc *desc) | ||
208 | { | ||
209 | unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS); | ||
210 | |||
211 | if (status == 0) { | ||
212 | do_bad_IRQ(irq, desc); | ||
213 | return; | ||
214 | } | ||
215 | |||
216 | do { | ||
217 | irq = ffs(status) - 1; | ||
218 | status &= ~(1 << irq); | ||
219 | |||
220 | irq += IRQ_SIC_START; | ||
221 | |||
222 | generic_handle_irq(irq); | ||
223 | } while (status); | ||
224 | } | ||
225 | |||
226 | static void __init intcp_init_irq(void) | 164 | static void __init intcp_init_irq(void) |
227 | { | 165 | { |
228 | unsigned int i; | 166 | u32 pic_mask, sic_mask; |
167 | |||
168 | pic_mask = ~((~0u) << (11 - IRQ_PIC_START)); | ||
169 | pic_mask |= (~((~0u) << (29 - 22))) << 22; | ||
170 | sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); | ||
229 | 171 | ||
230 | /* | 172 | /* |
231 | * Disable all interrupt sources | 173 | * Disable all interrupt sources |
232 | */ | 174 | */ |
233 | pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); | 175 | writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); |
234 | pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); | 176 | writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); |
235 | 177 | writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | |
236 | for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) { | 178 | writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); |
237 | if (i == 11) | 179 | writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); |
238 | i = 22; | 180 | writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); |
239 | if (i == 29) | ||
240 | break; | ||
241 | set_irq_chip(i, &pic_chip); | ||
242 | set_irq_handler(i, handle_level_irq); | ||
243 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | ||
244 | } | ||
245 | 181 | ||
246 | cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | 182 | fpga_irq_init(-1, pic_mask, &pic_irq_data); |
247 | cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); | ||
248 | 183 | ||
249 | for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) { | 184 | fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)), |
250 | set_irq_chip(i, &cic_chip); | 185 | &cic_irq_data); |
251 | set_irq_handler(i, handle_level_irq); | ||
252 | set_irq_flags(i, IRQF_VALID); | ||
253 | } | ||
254 | |||
255 | sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); | ||
256 | sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); | ||
257 | |||
258 | for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { | ||
259 | set_irq_chip(i, &sic_chip); | ||
260 | set_irq_handler(i, handle_level_irq); | ||
261 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | ||
262 | } | ||
263 | 186 | ||
264 | set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq); | 187 | fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data); |
265 | } | 188 | } |
266 | 189 | ||
267 | /* | 190 | /* |
@@ -449,43 +372,21 @@ static struct amba_device aaci_device = { | |||
449 | /* | 372 | /* |
450 | * CLCD support | 373 | * CLCD support |
451 | */ | 374 | */ |
452 | static struct clcd_panel vga = { | ||
453 | .mode = { | ||
454 | .name = "VGA", | ||
455 | .refresh = 60, | ||
456 | .xres = 640, | ||
457 | .yres = 480, | ||
458 | .pixclock = 39721, | ||
459 | .left_margin = 40, | ||
460 | .right_margin = 24, | ||
461 | .upper_margin = 32, | ||
462 | .lower_margin = 11, | ||
463 | .hsync_len = 96, | ||
464 | .vsync_len = 2, | ||
465 | .sync = 0, | ||
466 | .vmode = FB_VMODE_NONINTERLACED, | ||
467 | }, | ||
468 | .width = -1, | ||
469 | .height = -1, | ||
470 | .tim2 = TIM2_BCD | TIM2_IPC, | ||
471 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | ||
472 | .bpp = 16, | ||
473 | .grayscale = 0, | ||
474 | }; | ||
475 | |||
476 | /* | 375 | /* |
477 | * Ensure VGA is selected. | 376 | * Ensure VGA is selected. |
478 | */ | 377 | */ |
479 | static void cp_clcd_enable(struct clcd_fb *fb) | 378 | static void cp_clcd_enable(struct clcd_fb *fb) |
480 | { | 379 | { |
481 | u32 val; | 380 | struct fb_var_screeninfo *var = &fb->fb.var; |
381 | u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2; | ||
482 | 382 | ||
483 | if (fb->fb.var.bits_per_pixel <= 8) | 383 | if (var->bits_per_pixel <= 8 || |
484 | val = CM_CTRL_LCDMUXSEL_VGA_8421BPP; | 384 | (var->bits_per_pixel == 16 && var->green.length == 5)) |
385 | /* Pseudocolor, RGB555, BGR555 */ | ||
386 | val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555; | ||
485 | else if (fb->fb.var.bits_per_pixel <= 16) | 387 | else if (fb->fb.var.bits_per_pixel <= 16) |
486 | val = CM_CTRL_LCDMUXSEL_VGA_16BPP | 388 | /* truecolor RGB565 */ |
487 | | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1 | 389 | val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555; |
488 | | CM_CTRL_STATIC1 | CM_CTRL_STATIC2; | ||
489 | else | 390 | else |
490 | val = 0; /* no idea for this, don't trust the docs */ | 391 | val = 0; /* no idea for this, don't trust the docs */ |
491 | 392 | ||
@@ -498,49 +399,24 @@ static void cp_clcd_enable(struct clcd_fb *fb) | |||
498 | CM_CTRL_n24BITEN, val); | 399 | CM_CTRL_n24BITEN, val); |
499 | } | 400 | } |
500 | 401 | ||
501 | static unsigned long framesize = SZ_1M; | ||
502 | |||
503 | static int cp_clcd_setup(struct clcd_fb *fb) | 402 | static int cp_clcd_setup(struct clcd_fb *fb) |
504 | { | 403 | { |
505 | dma_addr_t dma; | 404 | fb->panel = versatile_clcd_get_panel("VGA"); |
506 | 405 | if (!fb->panel) | |
507 | fb->panel = &vga; | 406 | return -EINVAL; |
508 | |||
509 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, | ||
510 | &dma, GFP_KERNEL); | ||
511 | if (!fb->fb.screen_base) { | ||
512 | printk(KERN_ERR "CLCD: unable to map framebuffer\n"); | ||
513 | return -ENOMEM; | ||
514 | } | ||
515 | |||
516 | fb->fb.fix.smem_start = dma; | ||
517 | fb->fb.fix.smem_len = framesize; | ||
518 | |||
519 | return 0; | ||
520 | } | ||
521 | |||
522 | static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) | ||
523 | { | ||
524 | return dma_mmap_writecombine(&fb->dev->dev, vma, | ||
525 | fb->fb.screen_base, | ||
526 | fb->fb.fix.smem_start, | ||
527 | fb->fb.fix.smem_len); | ||
528 | } | ||
529 | 407 | ||
530 | static void cp_clcd_remove(struct clcd_fb *fb) | 408 | return versatile_clcd_setup_dma(fb, SZ_1M); |
531 | { | ||
532 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, | ||
533 | fb->fb.screen_base, fb->fb.fix.smem_start); | ||
534 | } | 409 | } |
535 | 410 | ||
536 | static struct clcd_board clcd_data = { | 411 | static struct clcd_board clcd_data = { |
537 | .name = "Integrator/CP", | 412 | .name = "Integrator/CP", |
413 | .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888, | ||
538 | .check = clcdfb_check, | 414 | .check = clcdfb_check, |
539 | .decode = clcdfb_decode, | 415 | .decode = clcdfb_decode, |
540 | .enable = cp_clcd_enable, | 416 | .enable = cp_clcd_enable, |
541 | .setup = cp_clcd_setup, | 417 | .setup = cp_clcd_setup, |
542 | .mmap = cp_clcd_mmap, | 418 | .mmap = versatile_clcd_mmap_dma, |
543 | .remove = cp_clcd_remove, | 419 | .remove = versatile_clcd_remove_dma, |
544 | }; | 420 | }; |
545 | 421 | ||
546 | static struct amba_device clcd_device = { | 422 | static struct amba_device clcd_device = { |
@@ -565,11 +441,23 @@ static struct amba_device *amba_devs[] __initdata = { | |||
565 | &clcd_device, | 441 | &clcd_device, |
566 | }; | 442 | }; |
567 | 443 | ||
444 | #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) | ||
445 | |||
446 | static void __init intcp_init_early(void) | ||
447 | { | ||
448 | clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups)); | ||
449 | |||
450 | integrator_init_early(); | ||
451 | |||
452 | #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK | ||
453 | versatile_sched_clock_init(REFCOUNTER, 24000000); | ||
454 | #endif | ||
455 | } | ||
456 | |||
568 | static void __init intcp_init(void) | 457 | static void __init intcp_init(void) |
569 | { | 458 | { |
570 | int i; | 459 | int i; |
571 | 460 | ||
572 | clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups)); | ||
573 | platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); | 461 | platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); |
574 | 462 | ||
575 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 463 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
@@ -599,8 +487,9 @@ static struct sys_timer cp_timer = { | |||
599 | MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") | 487 | MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") |
600 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | 488 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
601 | .boot_params = 0x00000100, | 489 | .boot_params = 0x00000100, |
602 | .map_io = intcp_map_io, | ||
603 | .reserve = integrator_reserve, | 490 | .reserve = integrator_reserve, |
491 | .map_io = intcp_map_io, | ||
492 | .init_early = intcp_init_early, | ||
604 | .init_irq = intcp_init_irq, | 493 | .init_irq = intcp_init_irq, |
605 | .timer = &cp_timer, | 494 | .timer = &cp_timer, |
606 | .init_machine = intcp_init, | 495 | .init_machine = intcp_init, |