34 files changed, 475 insertions, 185 deletions

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 11b2957f792b..e8627e04e1e6 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -633,12 +633,41 @@ config SOC_VF610
         bool "Vybrid Family VF610 support"
         select ARM_GIC
         select PINCTRL_VF610
-        select VF_PIT_TIMER
         select PL310_ERRATA_769419 if CACHE_L2X0
 
         help
           This enable support for Freescale Vybrid VF610 processor.
 
+choice
+        prompt "Clocksource for scheduler clock"
+        depends on SOC_VF610
+        default VF_USE_ARM_GLOBAL_TIMER
+
+        config VF_USE_ARM_GLOBAL_TIMER
+                bool "Use ARM Global Timer"
+                select ARM_GLOBAL_TIMER
+                select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+                help
+                  Use the ARM Global Timer as clocksource
+
+        config VF_USE_PIT_TIMER
+                bool "Use PIT timer"
+                select VF_PIT_TIMER
+                help
+                  Use SoC Periodic Interrupt Timer (PIT) as clocksource
+
+endchoice
+
+config SOC_LS1021A
+        bool "Freescale LS1021A support"
+        select ARM_GIC
+        select HAVE_ARM_ARCH_TIMER
+        select PCI_DOMAINS if PCI
+        select ZONE_DMA if ARM_LPAE
+
+        help
+          This enable support for Freescale LS1021A processor.
+
 endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 6e4fcd8339cd..f5ac685a29fc 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
 imx5-pm-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o clk-cpu.o $(imx5-pm-y)
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
                             clk-pfd.o clk-busy.o clk.o \
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-ifdef CONFIG_SOC_IMX6
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
 AFLAGS_headsmp.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
@@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
 obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
 
+obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
+
 obj-y += devices/
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 8259a625a920..7f262fe4ba77 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -30,8 +30,11 @@
 #define ANADIG_DIGPROG_IMX6SL   0x280
 
 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG    0x40000
+#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN       0x8
 #define BM_ANADIG_REG_CORE_FET_ODRIVE           0x20000000
 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG    0x1000
+/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
+#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS    0x2000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x80000
 #define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x100000
 
@@ -56,16 +59,43 @@ static void imx_anatop_enable_fet_odrive(bool enable)
                 BM_ANADIG_REG_CORE_FET_ODRIVE);
 }
 
+static inline void imx_anatop_enable_2p5_pulldown(bool enable)
+{
+        regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
+                BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
+}
+
+static inline void imx_anatop_disconnect_high_snvs(bool enable)
+{
+        regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
+                BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
+}
+
 void imx_anatop_pre_suspend(void)
 {
-        imx_anatop_enable_weak2p5(true);
+        if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
+                imx_anatop_enable_2p5_pulldown(true);
+        else
+                imx_anatop_enable_weak2p5(true);
+
         imx_anatop_enable_fet_odrive(true);
+
+        if (cpu_is_imx6sl())
+                imx_anatop_disconnect_high_snvs(true);
 }
 
 void imx_anatop_post_resume(void)
 {
+        if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
+                imx_anatop_enable_2p5_pulldown(false);
+        else
+                imx_anatop_enable_weak2p5(false);
+
         imx_anatop_enable_fet_odrive(false);
-        imx_anatop_enable_weak2p5(false);
+
+        if (cpu_is_imx6sl())
+                imx_anatop_disconnect_high_snvs(false);
+
 }
 
 static void imx_anatop_usb_chrg_detect_disable(void)
diff --git a/arch/arm/mach-imx/clk-cpu.c b/arch/arm/mach-imx/clk-cpu.c
new file mode 100644
index 000000000000..aa1c345e2a19
--- /dev/null
+++ b/arch/arm/mach-imx/clk-cpu.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+
+struct clk_cpu {
+        struct clk_hw   hw;
+        struct clk      *div;
+        struct clk      *mux;
+        struct clk      *pll;
+        struct clk      *step;
+};
+
+static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
+{
+        return container_of(hw, struct clk_cpu, hw);
+}
+
+static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+        struct clk_cpu *cpu = to_clk_cpu(hw);
+
+        return clk_get_rate(cpu->div);
+}
+
+static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *prate)
+{
+        struct clk_cpu *cpu = to_clk_cpu(hw);
+
+        return clk_round_rate(cpu->pll, rate);
+}
+
+static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
+                            unsigned long parent_rate)
+{
+        struct clk_cpu *cpu = to_clk_cpu(hw);
+        int ret;
+
+        /* switch to PLL bypass clock */
+        ret = clk_set_parent(cpu->mux, cpu->step);
+        if (ret)
+                return ret;
+
+        /* reprogram PLL */
+        ret = clk_set_rate(cpu->pll, rate);
+        if (ret) {
+                clk_set_parent(cpu->mux, cpu->pll);
+                return ret;
+        }
+        /* switch back to PLL clock */
+        clk_set_parent(cpu->mux, cpu->pll);
+
+        /* Ensure the divider is what we expect */
+        clk_set_rate(cpu->div, rate);
+
+        return 0;
+}
+
+static const struct clk_ops clk_cpu_ops = {
+        .recalc_rate    = clk_cpu_recalc_rate,
+        .round_rate     = clk_cpu_round_rate,
+        .set_rate       = clk_cpu_set_rate,
+};
+
+struct clk *imx_clk_cpu(const char *name, const char *parent_name,
+                struct clk *div, struct clk *mux, struct clk *pll,
+                struct clk *step)
+{
+        struct clk_cpu *cpu;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
+        if (!cpu)
+                return ERR_PTR(-ENOMEM);
+
+        cpu->div = div;
+        cpu->mux = mux;
+        cpu->pll = pll;
+        cpu->step = step;
+
+        init.name = name;
+        init.ops = &clk_cpu_ops;
+        init.flags = 0;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        cpu->hw.init = &init;
+
+        clk = clk_register(NULL, &cpu->hw);
+        if (IS_ERR(clk))
+                kfree(cpu);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 72d65214223e..0f7e536147cb 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -125,6 +125,8 @@ static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw",
 static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
 static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
 static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
+static const char *step_sels[] = { "lp_apm", };
+static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
 
 static struct clk *clk[IMX5_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -193,7 +195,9 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
         clk[IMX5_CLK_USB_PHY_PODF]      = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
         clk[IMX5_CLK_USB_PHY_SEL]       = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
                                                 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
-        clk[IMX5_CLK_CPU_PODF]          = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
+        clk[IMX5_CLK_STEP_SEL]          = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
+        clk[IMX5_CLK_CPU_PODF_SEL]      = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
+        clk[IMX5_CLK_CPU_PODF]          = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
         clk[IMX5_CLK_DI_PRED]           = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
         clk[IMX5_CLK_IIM_GATE]          = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
         clk[IMX5_CLK_UART1_IPG_GATE]    = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
@@ -537,6 +541,11 @@ static void __init mx53_clocks_init(struct device_node *np)
         clk[IMX5_CLK_CKO2]              = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
         clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
                                                 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
+        clk[IMX5_CLK_ARM]               = imx_clk_cpu("arm", "cpu_podf",
+                                                clk[IMX5_CLK_CPU_PODF],
+                                                clk[IMX5_CLK_CPU_PODF_SEL],
+                                                clk[IMX5_CLK_PLL1_SW],
+                                                clk[IMX5_CLK_STEP_SEL]);
 
         imx_check_clocks(clk, ARRAY_SIZE(clk));
 
@@ -551,6 +560,9 @@ static void __init mx53_clocks_init(struct device_node *np)
         /* move can bus clk to 24MHz */
         clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
 
+        /* make sure step clock is running from 24MHz */
+        clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
+
         clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
         imx_print_silicon_rev("i.MX53", mx53_revision());
         clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e79da7c5e30..5951660d1bd2 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -145,7 +145,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                 post_div_table[2].div = 1;
                 video_div_table[1].div = 1;
                 video_div_table[2].div = 1;
-        };
+        }
 
         clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
         clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 57de74da0acf..0ad6e5442fd8 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -69,7 +69,6 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
 {
         struct clk_pllv3 *pll = to_clk_pllv3(hw);
         u32 val;
-        int ret;
 
         val = readl_relaxed(pll->base);
         if (pll->powerup_set)
@@ -78,11 +77,7 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
                 val &= ~BM_PLL_POWER;
         writel_relaxed(val, pll->base);
 
-        ret = clk_pllv3_wait_lock(pll);
-        if (ret)
-                return ret;
-
-        return 0;
+        return clk_pllv3_wait_lock(pll);
 }
 
 static void clk_pllv3_unprepare(struct clk_hw *hw)
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index a17818475050..5937ddee1a99 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -58,8 +58,14 @@
 #define PFD_PLL1_BASE           (anatop_base + 0x2b0)
 #define PFD_PLL2_BASE           (anatop_base + 0x100)
 #define PFD_PLL3_BASE           (anatop_base + 0xf0)
+#define PLL1_CTRL               (anatop_base + 0x270)
+#define PLL2_CTRL               (anatop_base + 0x30)
 #define PLL3_CTRL               (anatop_base + 0x10)
+#define PLL4_CTRL               (anatop_base + 0x70)
+#define PLL5_CTRL               (anatop_base + 0xe0)
+#define PLL6_CTRL               (anatop_base + 0xa0)
 #define PLL7_CTRL               (anatop_base + 0x20)
+#define ANA_MISC1               (anatop_base + 0x160)
 
 static void __iomem *anatop_base;
 static void __iomem *ccm_base;
@@ -67,25 +73,34 @@ static void __iomem *ccm_base;
 /* sources for multiplexer clocks, this is used multiple times */
 static const char *fast_sels[]  = { "firc", "fxosc", };
 static const char *slow_sels[]  = { "sirc_32k", "sxosc", };
-static const char *pll1_sels[]  = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
-static const char *pll2_sels[]  = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
-static const char *sys_sels[]   = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
+static const char *pll1_sels[]  = { "pll1_sys", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
+static const char *pll2_sels[]  = { "pll2_bus", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
+static const char *pll_bypass_src_sels[] = { "fast_clk_sel", "lvds1_in", };
+static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
+static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
+static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
+static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
+static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
+static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
+static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
+static const char *sys_sels[]   = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_bus", "pll1_pfd_sel", "pll3_usb_otg", };
 static const char *ddr_sels[]   = { "pll2_pfd2", "sys_sel", };
 static const char *rmii_sels[]  = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
 static const char *enet_ts_sels[]       = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
-static const char *esai_sels[]  = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
-static const char *sai_sels[]   = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char *esai_sels[]  = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", };
+static const char *sai_sels[]   = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", };
 static const char *nfc_sels[]   = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
-static const char *qspi_sels[]  = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
-static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
-static const char *dcu_sels[]   = { "pll1_pfd2", "pll3_main", };
+static const char *qspi_sels[]  = { "pll3_usb_otg", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
+static const char *esdhc_sels[] = { "pll3_usb_otg", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
+static const char *dcu_sels[]   = { "pll1_pfd2", "pll3_usb_otg", };
 static const char *gpu_sels[]   = { "pll2_pfd2", "pll3_pfd2", };
-static const char *vadc_sels[]  = { "pll6_main_div", "pll3_main_div", "pll3_main", };
+static const char *vadc_sels[]  = { "pll6_video_div", "pll3_usb_otg_div", "pll3_usb_otg", };
 /* FTM counter clock source, not module clock */
 static const char *ftm_ext_sels[]       = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
 static const char *ftm_fix_sels[]       = { "sxosc", "ipg_bus", };
 
-static struct clk_div_table pll4_main_div_table[] = {
+
+static struct clk_div_table pll4_audio_div_table[] = {
         { .val = 0, .div = 1 },
         { .val = 1, .div = 2 },
         { .val = 2, .div = 6 },
@@ -105,6 +120,17 @@ static unsigned int const clks_init_on[] __initconst = {
         VF610_CLK_DDR_SEL,
 };
 
+static struct clk * __init vf610_get_fixed_clock(
+                                struct device_node *ccm_node, const char *name)
+{
+        struct clk *clk = of_clk_get_by_name(ccm_node, name);
+
+        /* Backward compatibility if device tree is missing clks assignments */
+        if (IS_ERR(clk))
+                clk = imx_obtain_fixed_clock(name, 0);
+        return clk;
+};
+
 static void __init vf610_clocks_init(struct device_node *ccm_node)
 {
         struct device_node *np;
@@ -115,10 +141,13 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
         clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
         clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
 
-        clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
-        clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
-        clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
-        clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
+        clk[VF610_CLK_SXOSC] = vf610_get_fixed_clock(ccm_node, "sxosc");
+        clk[VF610_CLK_FXOSC] = vf610_get_fixed_clock(ccm_node, "fxosc");
+        clk[VF610_CLK_AUDIO_EXT] = vf610_get_fixed_clock(ccm_node, "audio_ext");
+        clk[VF610_CLK_ENET_EXT] = vf610_get_fixed_clock(ccm_node, "enet_ext");
+
+        /* Clock source from external clock via LVDs PAD */
+        clk[VF610_CLK_ANACLK1] = vf610_get_fixed_clock(ccm_node, "anaclk1");
 
         clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
 
@@ -133,31 +162,63 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
         clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
         clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
 
-        clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
-        clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
-        clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
-        clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
-        clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
-
-        clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
-        clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
-        clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
-        clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
-        clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
-
-        clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
-        clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
-        clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
-        clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
-        clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
-
-        clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
-        /* Enet pll: fixed 50Mhz */
-        clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
-        /* pll6: default 960Mhz */
-        clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
-        /* pll7: USB1 PLL at 480MHz */
-        clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2);
+        clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[VF610_CLK_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", PLL3_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[VF610_CLK_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", PLL4_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[VF610_CLK_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", PLL5_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+        clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+
+        clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);
+        clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);
+        clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1);
+        clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);
+        clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);
+        clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f);
+        clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1);
+
+        clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[VF610_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[VF610_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[VF610_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[VF610_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
+        clk[VF610_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
+
+        /* Do not bypass PLLs initially */
+        clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]);
+        clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]);
+        clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]);
+        clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]);
+        clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]);
+        clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]);
+        clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]);
+
+        clk[VF610_CLK_PLL1_SYS]      = imx_clk_gate("pll1_sys",      "pll1_bypass", PLL1_CTRL, 13);
+        clk[VF610_CLK_PLL2_BUS]      = imx_clk_gate("pll2_bus",      "pll2_bypass", PLL2_CTRL, 13);
+        clk[VF610_CLK_PLL3_USB_OTG]  = imx_clk_gate("pll3_usb_otg",  "pll3_bypass", PLL3_CTRL, 13);
+        clk[VF610_CLK_PLL4_AUDIO]    = imx_clk_gate("pll4_audio",    "pll4_bypass", PLL4_CTRL, 13);
+        clk[VF610_CLK_PLL5_ENET]     = imx_clk_gate("pll5_enet",     "pll5_bypass", PLL5_CTRL, 13);
+        clk[VF610_CLK_PLL6_VIDEO]    = imx_clk_gate("pll6_video",    "pll6_bypass", PLL6_CTRL, 13);
+        clk[VF610_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", PLL7_CTRL, 13);
+
+        clk[VF610_CLK_LVDS1_IN]  = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10));
+
+        clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_sys", PFD_PLL1_BASE, 0);
+        clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_sys", PFD_PLL1_BASE, 1);
+        clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_sys", PFD_PLL1_BASE, 2);
+        clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_sys", PFD_PLL1_BASE, 3);
+
+        clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", PFD_PLL2_BASE, 0);
+        clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", PFD_PLL2_BASE, 1);
+        clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_bus", PFD_PLL2_BASE, 2);
+        clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_bus", PFD_PLL2_BASE, 3);
+
+        clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", PFD_PLL3_BASE, 0);
+        clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", PFD_PLL3_BASE, 1);
+        clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", PFD_PLL3_BASE, 2);
+        clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_usb_otg", PFD_PLL3_BASE, 3);
 
         clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
         clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
@@ -167,12 +228,12 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
         clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
         clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
 
-        clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
-        clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
-        clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
+        clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_usb_otg_div", "pll3_usb_otg", CCM_CACRR, 20, 1);
+        clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock);
+        clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1);
 
-        clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6);
-        clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6);
+        clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6);
+        clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6);
 
         clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
         clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
@@ -191,8 +252,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
         clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
         clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
 
-        clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
-        clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
+        clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_enet", 1, 10);
+        clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_enet", 1, 20);
         clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
         clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
         clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 4cdf8b6a74e8..5ef82e2f8fc5 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -131,4 +131,8 @@ static inline struct clk *imx_clk_fixed_factor(const char *name,
                         CLK_SET_RATE_PARENT, mult, div);
 }
 
+struct clk *imx_clk_cpu(const char *name, const char *parent_name,
+                struct clk *div, struct clk *mux, struct clk *pll,
+                struct clk *step);
+
 #endif
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 1dabf435c592..cfcdb623d78f 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -61,7 +61,6 @@ struct platform_device *mxc_register_gpio(char *name, int id,
 void mxc_set_cpu_type(unsigned int type);
 void mxc_restart(enum reboot_mode, const char *);
 void mxc_arch_reset_init(void __iomem *);
-void mxc_arch_reset_init_dt(void);
 int mx51_revision(void);
 int mx53_revision(void);
 void imx_set_aips(void __iomem *);
@@ -108,14 +107,15 @@ void imx_gpc_pre_suspend(bool arm_power_off);
 void imx_gpc_post_resume(void);
 void imx_gpc_mask_all(void);
 void imx_gpc_restore_all(void);
-void imx_gpc_irq_mask(struct irq_data *d);
-void imx_gpc_irq_unmask(struct irq_data *d);
+void imx_gpc_hwirq_mask(unsigned int hwirq);
+void imx_gpc_hwirq_unmask(unsigned int hwirq);
 void imx_anatop_init(void);
 void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
 void imx6q_set_int_mem_clk_lpm(bool enable);
 void imx6sl_set_wait_clk(bool enter);
+int imx_mmdc_get_ddr_type(void);
 
 void imx_cpu_die(unsigned int cpu);
 int imx_cpu_kill(unsigned int cpu);
@@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {}
 #endif
 
 extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
 
 #endif
diff --git a/arch/arm/mach-imx/cpuidle-imx5.c b/arch/arm/mach-imx/cpuidle-imx5.c
index 5a47e3c6172f..3feca526d16b 100644
--- a/arch/arm/mach-imx/cpuidle-imx5.c
+++ b/arch/arm/mach-imx/cpuidle-imx5.c
@@ -24,7 +24,6 @@ static struct cpuidle_driver imx5_cpuidle_driver = {
                 .enter            = imx5_cpuidle_enter,
                 .exit_latency     = 2,
                 .target_residency = 1,
-                .flags            = CPUIDLE_FLAG_TIME_VALID,
                 .name             = "IMX5 SRPG",
                 .desc             = "CPU state retained,powered off",
         },
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index aa935787b743..d76d08623f9f 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -53,8 +53,7 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
                 {
                         .exit_latency = 50,
                         .target_residency = 75,
-                        .flags = CPUIDLE_FLAG_TIME_VALID |
-                                 CPUIDLE_FLAG_TIMER_STOP,
+                        .flags = CPUIDLE_FLAG_TIMER_STOP,
                         .enter = imx6q_enter_wait,
                         .name = "WAIT",
                         .desc = "Clock off",
diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c
index d4b6b8171fa9..7d92e6584551 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sl.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sl.c
@@ -40,8 +40,7 @@ static struct cpuidle_driver imx6sl_cpuidle_driver = {
                 {
                         .exit_latency = 50,
                         .target_residency = 75,
-                        .flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_TIMER_STOP,
+                        .flags = CPUIDLE_FLAG_TIMER_STOP,
                         .enter = imx6sl_enter_wait,
                         .name = "WAIT",
                         .desc = "Clock off",
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 82ea74e68482..5f3602ec74fa 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -56,14 +56,14 @@ void imx_gpc_post_resume(void)
 
 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
 {
-        unsigned int idx = d->irq / 32 - 1;
+        unsigned int idx = d->hwirq / 32 - 1;
         u32 mask;
 
         /* Sanity check for SPI irq */
-        if (d->irq < 32)
+        if (d->hwirq < 32)
                 return -EINVAL;
 
-        mask = 1 << d->irq % 32;
+        mask = 1 << d->hwirq % 32;
         gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
                                   gpc_wake_irqs[idx] & ~mask;
 
@@ -91,34 +91,44 @@ void imx_gpc_restore_all(void)
                 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
 }
 
-void imx_gpc_irq_unmask(struct irq_data *d)
+void imx_gpc_hwirq_unmask(unsigned int hwirq)
 {
         void __iomem *reg;
         u32 val;
 
-        /* Sanity check for SPI irq */
-        if (d->irq < 32)
-                return;
-
-        reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
+        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
         val = readl_relaxed(reg);
-        val &= ~(1 << d->irq % 32);
+        val &= ~(1 << hwirq % 32);
         writel_relaxed(val, reg);
 }
 
-void imx_gpc_irq_mask(struct irq_data *d)
+void imx_gpc_hwirq_mask(unsigned int hwirq)
 {
         void __iomem *reg;
         u32 val;
 
+        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+        val = readl_relaxed(reg);
+        val |= 1 << (hwirq % 32);
+        writel_relaxed(val, reg);
+}
+
+static void imx_gpc_irq_unmask(struct irq_data *d)
+{
+        /* Sanity check for SPI irq */
+        if (d->hwirq < 32)
+                return;
+
+        imx_gpc_hwirq_unmask(d->hwirq);
+}
+
+static void imx_gpc_irq_mask(struct irq_data *d)
+{
         /* Sanity check for SPI irq */
-        if (d->irq < 32)
+        if (d->hwirq < 32)
                 return;
 
-        reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
-        val = readl_relaxed(reg);
-        val |= 1 << (d->irq % 32);
-        writel_relaxed(val, reg);
+        imx_gpc_hwirq_mask(d->hwirq);
 }
 
 void __init imx_gpc_init(void)
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index cf8032bae277..25defbdb06c4 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -17,13 +17,6 @@
 #include "common.h"
 #include "mx25.h"
 
-static void __init imx25_dt_init(void)
-{
-        mxc_arch_reset_init_dt();
-
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char * const imx25_dt_board_compat[] __initconst = {
         "fsl,imx25",
         NULL
@@ -33,7 +26,5 @@ DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
         .map_io         = mx25_map_io,
         .init_early     = imx25_init_early,
         .init_irq       = mx25_init_irq,
-        .init_machine   = imx25_dt_init,
         .dt_compat      = imx25_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index dc8f1a6f45f2..bd42d1bd10af 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -22,8 +22,6 @@ static void __init imx27_dt_init(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-dt", };
 
-        mxc_arch_reset_init_dt();
-
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         platform_device_register_full(&devinfo);
@@ -40,5 +38,4 @@ DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
         .init_irq       = mx27_init_irq,
         .init_machine   = imx27_dt_init,
         .dt_compat      = imx27_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 418dbc82adc4..32100222a017 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -18,13 +18,6 @@
 #include "common.h"
 #include "mx31.h"
 
-static void __init imx31_dt_init(void)
-{
-        mxc_arch_reset_init_dt();
-
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char * const imx31_dt_board_compat[] __initconst = {
         "fsl,imx31",
         NULL
@@ -40,7 +33,5 @@ DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
         .init_early     = imx31_init_early,
         .init_irq       = mx31_init_irq,
         .init_time      = imx31_dt_timer_init,
-        .init_machine   = imx31_dt_init,
         .dt_compat      = imx31_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
index 584fbe105579..e9396037235d 100644
--- a/arch/arm/mach-imx/imx35-dt.c
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -20,14 +20,6 @@
 #include "common.h"
 #include "mx35.h"
 
-static void __init imx35_dt_init(void)
-{
-        mxc_arch_reset_init_dt();
-
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             NULL, NULL);
-}
-
 static void __init imx35_irq_init(void)
 {
         imx_init_l2cache();
@@ -43,7 +35,5 @@ DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
         .map_io         = mx35_map_io,
         .init_early     = imx35_init_early,
         .init_irq       = imx35_irq_init,
-        .init_machine   = imx35_dt_init,
         .dt_compat      = imx35_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index 1657fe64cd0f..d6a30753ca7c 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -44,9 +44,11 @@ static unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
 /*
  * set the mode for a IOMUX pin.
  */
-int mxc_iomux_mode(unsigned int pin_mode)
+void mxc_iomux_mode(unsigned int pin_mode)
 {
-        u32 field, l, mode, ret = 0;
+        u32 field;
+        u32 l;
+        u32 mode;
         void __iomem *reg;
 
         reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
@@ -61,8 +63,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
         __raw_writel(l, reg);
 
         spin_unlock(&gpio_mux_lock);
-
-        return ret;
 }
 
 /*
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index f79f78a1c0ed..0a5adba61e0b 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -144,7 +144,7 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool en);
  * It is called by the setup functions and should not be called directly anymore.
  * It is here visible for backward compatibility
  */
-int mxc_iomux_mode(unsigned int pin_mode);
+void mxc_iomux_mode(unsigned int pin_mode);
 
 #define IOMUX_PADNUM_MASK       0x1ff
 #define IOMUX_GPIONUM_SHIFT     9
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
index b1e56a94a382..ecf58b9e974b 100644
--- a/arch/arm/mach-imx/mach-imx50.c
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -16,13 +16,6 @@
 
 #include "common.h"
 
-static void __init imx50_dt_init(void)
-{
-        mxc_arch_reset_init_dt();
-
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char * const imx50_dt_board_compat[] __initconst = {
         "fsl,imx50",
         NULL
@@ -30,7 +23,5 @@ static const char * const imx50_dt_board_compat[] __initconst = {
 
 DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
         .init_irq       = tzic_init_irq,
-        .init_machine   = imx50_dt_init,
         .dt_compat      = imx50_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c
index 2c5fcaf8675b..b015129e4045 100644
--- a/arch/arm/mach-imx/mach-imx51.c
+++ b/arch/arm/mach-imx/mach-imx51.c
@@ -53,7 +53,6 @@ static void __init imx51_dt_init(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-dt", };
 
-        mxc_arch_reset_init_dt();
         imx51_ipu_mipi_setup();
         imx_src_init();
 
@@ -78,5 +77,4 @@ DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
         .init_machine   = imx51_dt_init,
         .init_late      = imx51_init_late,
         .dt_compat      = imx51_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 03dd6ea13acc..86316a979297 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -30,7 +30,6 @@ static void __init imx53_init_early(void)
 
 static void __init imx53_dt_init(void)
 {
-        mxc_arch_reset_init_dt();
         imx_src_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -41,6 +40,8 @@ static void __init imx53_dt_init(void)
 static void __init imx53_init_late(void)
 {
         imx53_pm_init();
+
+        platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
 }
 
 static const char * const imx53_dt_board_compat[] __initconst = {
@@ -54,5 +55,4 @@ DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
         .init_machine   = imx53_dt_init,
         .init_late      = imx53_init_late,
         .dt_compat      = imx53_dt_board_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index d51c6e99a2e9..5057d61298b7 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -268,8 +268,6 @@ static void __init imx6q_init_machine(void)
         imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
                               imx_get_soc_revision());
 
-        mxc_arch_reset_init_dt();
-
         parent = imx_soc_device_init();
         if (parent == NULL)
                 pr_warn("failed to initialize soc device\n");
@@ -409,5 +407,4 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
         .init_machine   = imx6q_init_machine,
         .init_late      = imx6q_init_late,
         .dt_compat      = imx6q_dt_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index ed263a21d928..24bfaaf944c8 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -48,8 +48,6 @@ static void __init imx6sl_init_machine(void)
 {
         struct device *parent;
 
-        mxc_arch_reset_init_dt();
-
         parent = imx_soc_device_init();
         if (parent == NULL)
                 pr_warn("failed to initialize soc device\n");
@@ -76,10 +74,8 @@ static const char * const imx6sl_dt_compat[] __initconst = {
 };
 
 DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
-        .map_io         = debug_ll_io_init,
         .init_irq       = imx6sl_init_irq,
         .init_machine   = imx6sl_init_machine,
         .init_late      = imx6sl_init_late,
         .dt_compat      = imx6sl_dt_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 3de3b7369aef..7a96c6577234 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -8,24 +8,73 @@
 
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include "common.h"
 #include "cpuidle.h"
 
+static int ar8031_phy_fixup(struct phy_device *dev)
+{
+        u16 val;
+
+        /* Set RGMII IO voltage to 1.8V */
+        phy_write(dev, 0x1d, 0x1f);
+        phy_write(dev, 0x1e, 0x8);
+
+        /* introduce tx clock delay */
+        phy_write(dev, 0x1d, 0x5);
+        val = phy_read(dev, 0x1e);
+        val |= 0x0100;
+        phy_write(dev, 0x1e, val);
+
+        return 0;
+}
+
+#define PHY_ID_AR8031   0x004dd074
+static void __init imx6sx_enet_phy_init(void)
+{
+        if (IS_BUILTIN(CONFIG_PHYLIB))
+                phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
+                                           ar8031_phy_fixup);
+}
+
+static void __init imx6sx_enet_clk_sel(void)
+{
+        struct regmap *gpr;
+
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
+        if (!IS_ERR(gpr)) {
+                regmap_update_bits(gpr, IOMUXC_GPR1,
+                                   IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
+                regmap_update_bits(gpr, IOMUXC_GPR1,
+                                   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
+        } else {
+                pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
+        }
+}
+
+static inline void imx6sx_enet_init(void)
+{
+        imx6sx_enet_phy_init();
+        imx6sx_enet_clk_sel();
+}
+
 static void __init imx6sx_init_machine(void)
 {
         struct device *parent;
 
-        mxc_arch_reset_init_dt();
-
         parent = imx_soc_device_init();
         if (parent == NULL)
                 pr_warn("failed to initialize soc device\n");
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
 
+        imx6sx_enet_init();
         imx_anatop_init();
         imx6sx_pm_init();
 }
@@ -53,10 +102,8 @@ static const char * const imx6sx_dt_compat[] __initconst = {
 };
 
 DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
-        .map_io         = debug_ll_io_init,
         .init_irq       = imx6sx_init_irq,
         .init_machine   = imx6sx_init_machine,
         .dt_compat      = imx6sx_dt_compat,
         .init_late      = imx6sx_init_late,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
new file mode 100644
index 000000000000..b89c858ebfd6
--- /dev/null
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const char * const ls1021a_dt_compat[] __initconst = {
+        "fsl,ls1021a",
+        NULL,
+};
+
+DT_MACHINE_START(LS1021A, "Freescale LS1021A")
+        .smp            = smp_ops(ls1021a_smp_ops),
+        .dt_compat      = ls1021a_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index ee7e57b752a7..c11ab6a1dc87 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -12,14 +12,6 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include "common.h"
-
-static void __init vf610_init_machine(void)
-{
-        mxc_arch_reset_init_dt();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char * const vf610_dt_compat[] __initconst = {
         "fsl,vf610",
         NULL,
@@ -28,7 +20,5 @@ static const char * const vf610_dt_compat[] __initconst = {
 DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
         .l2c_aux_val    = 0,
         .l2c_aux_mask   = ~0,
-        .init_machine   = vf610_init_machine,
         .dt_compat      = vf610_dt_compat,
-        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index a3dedc309bbc..a377f95033ae 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -21,6 +21,12 @@
 #define BP_MMDC_MAPSR_PSD       0
 #define BP_MMDC_MAPSR_PSS       4
 
+#define MMDC_MDMISC             0x18
+#define BM_MMDC_MDMISC_DDR_TYPE 0x18
+#define BP_MMDC_MDMISC_DDR_TYPE 0x3
+
+static int ddr_type;
+
 static int imx_mmdc_probe(struct platform_device *pdev)
 {
         struct device_node *np = pdev->dev.of_node;
@@ -31,6 +37,12 @@ static int imx_mmdc_probe(struct platform_device *pdev)
         mmdc_base = of_iomap(np, 0);
         WARN_ON(!mmdc_base);
 
+        reg = mmdc_base + MMDC_MDMISC;
+        /* Get ddr type */
+        val = readl_relaxed(reg);
+        ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >>
+                 BP_MMDC_MDMISC_DDR_TYPE;
+
         reg = mmdc_base + MMDC_MAPSR;
 
         /* Enable automatic power saving */
@@ -51,6 +63,11 @@ static int imx_mmdc_probe(struct platform_device *pdev)
         return 0;
 }
 
+int imx_mmdc_get_ddr_type(void)
+{
+        return ddr_type;
+}
+
 static struct of_device_id imx_mmdc_dt_ids[] = {
         { .compatible = "fsl,imx6q-mmdc", },
         { /* sentinel */ }
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 17a41ca65acf..4c1343df2ba4 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -55,6 +55,8 @@
 #define IMX_CHIP_REVISION_3_3           0x33
 #define IMX_CHIP_REVISION_UNKNOWN       0xff
 
+#define IMX_DDR_TYPE_LPDDR2             1
+
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
 #endif
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 771bd25c1025..7f270015fe58 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -11,7 +11,10 @@
  */
 
 #include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 #include <linux/smp.h>
+
 #include <asm/cacheflush.h>
 #include <asm/page.h>
 #include <asm/smp_scu.h>
@@ -94,3 +97,33 @@ struct smp_operations  imx_smp_ops __initdata = {
         .cpu_kill               = imx_cpu_kill,
 #endif
 };
+
+#define DCFG_CCSR_SCRATCHRW1    0x200
+
+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+        return 0;
+}
+
+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *np;
+        void __iomem *dcfg_base;
+        unsigned long paddr;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+        dcfg_base = of_iomap(np, 0);
+        BUG_ON(!dcfg_base);
+
+        paddr = virt_to_phys(secondary_startup);
+        writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
+
+        iounmap(dcfg_base);
+}
+
+struct smp_operations  ls1021a_smp_ops __initdata = {
+        .smp_prepare_cpus       = ls1021a_smp_prepare_cpus,
+        .smp_boot_secondary     = ls1021a_boot_secondary,
+};
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 5c3af8f993d0..5d2c1bd5f5ef 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -88,7 +88,7 @@ struct imx6_pm_base {
 };
 
 struct imx6_pm_socdata {
-        u32 cpu_type;
+        u32 ddr_type;
         const char *mmdc_compat;
         const char *src_compat;
         const char *iomuxc_compat;
@@ -138,7 +138,6 @@ static const u32 imx6sx_mmdc_io_offset[] __initconst = {
 };
 
 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
-        .cpu_type = MXC_CPU_IMX6Q,
         .mmdc_compat = "fsl,imx6q-mmdc",
         .src_compat = "fsl,imx6q-src",
         .iomuxc_compat = "fsl,imx6q-iomuxc",
@@ -148,7 +147,6 @@ static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
 };
 
 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
-        .cpu_type = MXC_CPU_IMX6DL,
         .mmdc_compat = "fsl,imx6q-mmdc",
         .src_compat = "fsl,imx6q-src",
         .iomuxc_compat = "fsl,imx6dl-iomuxc",
@@ -158,7 +156,6 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
 };
 
 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
-        .cpu_type = MXC_CPU_IMX6SL,
         .mmdc_compat = "fsl,imx6sl-mmdc",
         .src_compat = "fsl,imx6sl-src",
         .iomuxc_compat = "fsl,imx6sl-iomuxc",
@@ -168,7 +165,6 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
 };
 
 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
-        .cpu_type = MXC_CPU_IMX6SX,
         .mmdc_compat = "fsl,imx6sx-mmdc",
         .src_compat = "fsl,imx6sx-src",
         .iomuxc_compat = "fsl,imx6sx-iomuxc",
@@ -187,7 +183,7 @@ static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
 struct imx6_cpu_pm_info {
         phys_addr_t pbase; /* The physical address of pm_info. */
         phys_addr_t resume_addr; /* The physical resume address for asm code */
-        u32 cpu_type;
+        u32 ddr_type;
         u32 pm_info_size; /* Size of pm_info. */
         struct imx6_pm_base mmdc_base;
         struct imx6_pm_base src_base;
@@ -261,7 +257,6 @@ static void imx6q_enable_wb(bool enable)
 
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
 {
-        struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
         u32 val = readl_relaxed(ccm_base + CLPCR);
 
         val &= ~BM_CLPCR_LPM;
@@ -316,9 +311,9 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
          * 3) Software should mask IRQ #32 right after CCM Low-Power mode
          *    is set (set bits 0-1 of CCM_CLPCR).
          */
-        imx_gpc_irq_unmask(iomuxc_irq_data);
+        imx_gpc_hwirq_unmask(32);
         writel_relaxed(val, ccm_base + CLPCR);
-        imx_gpc_irq_mask(iomuxc_irq_data);
+        imx_gpc_hwirq_mask(32);
 
         return 0;
 }
@@ -522,7 +517,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
                 goto pl310_cache_map_failed;
         }
 
-        pm_info->cpu_type = socdata->cpu_type;
+        pm_info->ddr_type = imx_mmdc_get_ddr_type();
         pm_info->mmdc_io_num = socdata->mmdc_io_num;
         mmdc_offset_array = socdata->mmdc_io_offset;
 
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index ca4ea2daf25b..b99987b023fa 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -45,7 +45,7 @@
  */
 #define PM_INFO_PBASE_OFFSET                    0x0
 #define PM_INFO_RESUME_ADDR_OFFSET              0x4
-#define PM_INFO_CPU_TYPE_OFFSET                 0x8
+#define PM_INFO_DDR_TYPE_OFFSET                 0x8
 #define PM_INFO_PM_INFO_SIZE_OFFSET             0xC
 #define PM_INFO_MX6Q_MMDC_P_OFFSET              0x10
 #define PM_INFO_MX6Q_MMDC_V_OFFSET              0x14
@@ -110,7 +110,7 @@
         ldreq   r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
         ldrne   r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
 
-        cmp     r3, #MXC_CPU_IMX6SL
+        cmp     r3, #IMX_DDR_TYPE_LPDDR2
         bne     4f
 
         /* reset read FIFO, RST_RD_FIFO */
@@ -151,7 +151,7 @@
 ENTRY(imx6_suspend)
         ldr     r1, [r0, #PM_INFO_PBASE_OFFSET]
         ldr     r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
-        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        ldr     r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
         ldr     r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
 
         /*
@@ -209,8 +209,8 @@ poll_dvfs_set:
         ldr     r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
         ldr     r8, =PM_INFO_MMDC_IO_VAL_OFFSET
         add     r8, r8, r0
-        /* i.MX6SL's last 3 IOs need special setting */
-        cmp     r3, #MXC_CPU_IMX6SL
+        /* LPDDR2's last 3 IOs need special setting */
+        cmp     r3, #IMX_DDR_TYPE_LPDDR2
         subeq   r7, r7, #0x3
 set_mmdc_io_lpm:
         ldr     r9, [r8], #0x8
@@ -218,7 +218,7 @@ set_mmdc_io_lpm:
         subs    r7, r7, #0x1
         bne     set_mmdc_io_lpm
 
-        cmp     r3, #MXC_CPU_IMX6SL
+        cmp     r3, #IMX_DDR_TYPE_LPDDR2
         bne     set_mmdc_io_lpm_done
         ldr     r6, =0x1000
         ldr     r9, [r8], #0x8
@@ -324,7 +324,7 @@ resume:
         str     r7, [r11, #MX6Q_SRC_GPR1]
         str     r7, [r11, #MX6Q_SRC_GPR2]
 
-        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        ldr     r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
         mov     r5, #0x1
         resume_mmdc
 
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index d14c33fd6b03..51c35013b673 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -89,21 +89,6 @@ void __init mxc_arch_reset_init(void __iomem *base)
                 clk_prepare(wdog_clk);
 }
 
-void __init mxc_arch_reset_init_dt(void)
-{
-        struct device_node *np;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
-        wdog_base = of_iomap(np, 0);
-        WARN_ON(!wdog_base);
-
-        wdog_clk = of_clk_get(np, 0);
-        if (IS_ERR(wdog_clk))
-                pr_warn("%s: failed to get wdog clock\n", __func__);
-        else
-                clk_prepare(wdog_clk);
-}
-
 #ifdef CONFIG_CACHE_L2X0
 void __init imx_init_l2cache(void)
 {