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-rw-r--r--arch/arm/mach-imx/Kconfig20
-rw-r--r--arch/arm/mach-imx/Makefile8
-rw-r--r--arch/arm/mach-imx/Makefile.boot3
-rw-r--r--arch/arm/mach-imx/clock-imx27.c18
-rw-r--r--arch/arm/mach-imx/clock-imx31.c2
-rw-r--r--arch/arm/mach-imx/clock-imx35.c166
-rw-r--r--arch/arm/mach-imx/clock-imx6q.c74
-rw-r--r--arch/arm/mach-imx/cpu-imx5.c36
-rw-r--r--arch/arm/mach-imx/crmregs-imx3.h (renamed from arch/arm/mach-imx/crmregs-imx31.h)16
-rw-r--r--arch/arm/mach-imx/dma-v1.c846
-rw-r--r--arch/arm/mach-imx/imx27-dt.c89
-rw-r--r--arch/arm/mach-imx/imx51-dt.c1
-rw-r--r--arch/arm/mach-imx/imx53-dt.c1
-rw-r--r--arch/arm/mach-imx/include/mach/dma-v1.h103
-rw-r--r--arch/arm/mach-imx/lluart.c2
-rw-r--r--arch/arm/mach-imx/localtimer.c35
-rw-r--r--arch/arm/mach-imx/mach-armadillo5x0.c2
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c139
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c4
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c16
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c108
-rw-r--r--arch/arm/mach-imx/mach-mx31ads.c35
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c6
-rw-r--r--arch/arm/mach-imx/mach-mx35_3ds.c216
-rw-r--r--arch/arm/mach-imx/mach-mx51_efikamx.c1
-rw-r--r--arch/arm/mach-imx/mach-mx51_efikasb.c1
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c2
-rw-r--r--arch/arm/mach-imx/mm-imx3.c23
-rw-r--r--arch/arm/mach-imx/mm-imx5.c10
-rw-r--r--arch/arm/mach-imx/pm-imx3.c37
-rw-r--r--arch/arm/mach-imx/pm-imx5.c4
31 files changed, 879 insertions, 1145 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3919fba52ac8..7561eca131b0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,3 @@
1config IMX_HAVE_DMA_V1
2 bool
3
4config HAVE_IMX_GPC 1config HAVE_IMX_GPC
5 bool 2 bool
6 3
@@ -38,7 +35,6 @@ config SOC_IMX1
38 bool 35 bool
39 select ARCH_MX1 36 select ARCH_MX1
40 select CPU_ARM920T 37 select CPU_ARM920T
41 select IMX_HAVE_DMA_V1
42 select IMX_HAVE_IOMUX_V1 38 select IMX_HAVE_IOMUX_V1
43 select MXC_AVIC 39 select MXC_AVIC
44 40
@@ -46,7 +42,6 @@ config SOC_IMX21
46 bool 42 bool
47 select MACH_MX21 43 select MACH_MX21
48 select CPU_ARM926T 44 select CPU_ARM926T
49 select IMX_HAVE_DMA_V1
50 select IMX_HAVE_IOMUX_V1 45 select IMX_HAVE_IOMUX_V1
51 select MXC_AVIC 46 select MXC_AVIC
52 47
@@ -61,7 +56,6 @@ config SOC_IMX27
61 bool 56 bool
62 select MACH_MX27 57 select MACH_MX27
63 select CPU_ARM926T 58 select CPU_ARM926T
64 select IMX_HAVE_DMA_V1
65 select IMX_HAVE_IOMUX_V1 59 select IMX_HAVE_IOMUX_V1
66 select MXC_AVIC 60 select MXC_AVIC
67 61
@@ -298,6 +292,7 @@ config MACH_MX27_3DS
298 select IMX_HAVE_PLATFORM_IMX_I2C 292 select IMX_HAVE_PLATFORM_IMX_I2C
299 select IMX_HAVE_PLATFORM_IMX_KEYPAD 293 select IMX_HAVE_PLATFORM_IMX_KEYPAD
300 select IMX_HAVE_PLATFORM_IMX_UART 294 select IMX_HAVE_PLATFORM_IMX_UART
295 select IMX_HAVE_PLATFORM_MX2_CAMERA
301 select IMX_HAVE_PLATFORM_MXC_EHCI 296 select IMX_HAVE_PLATFORM_MXC_EHCI
302 select IMX_HAVE_PLATFORM_MXC_MMC 297 select IMX_HAVE_PLATFORM_MXC_MMC
303 select IMX_HAVE_PLATFORM_SPI_IMX 298 select IMX_HAVE_PLATFORM_SPI_IMX
@@ -314,8 +309,10 @@ config MACH_IMX27_VISSTRIM_M10
314 select IMX_HAVE_PLATFORM_IMX_I2C 309 select IMX_HAVE_PLATFORM_IMX_I2C
315 select IMX_HAVE_PLATFORM_IMX_SSI 310 select IMX_HAVE_PLATFORM_IMX_SSI
316 select IMX_HAVE_PLATFORM_IMX_UART 311 select IMX_HAVE_PLATFORM_IMX_UART
317 select IMX_HAVE_PLATFORM_MXC_MMC 312 select IMX_HAVE_PLATFORM_MX2_CAMERA
318 select IMX_HAVE_PLATFORM_MXC_EHCI 313 select IMX_HAVE_PLATFORM_MXC_EHCI
314 select IMX_HAVE_PLATFORM_MXC_MMC
315 select LEDS_GPIO_REGISTER
319 help 316 help
320 Include support for Visstrim_m10 platform and its different variants. 317 Include support for Visstrim_m10 platform and its different variants.
321 This includes specific configurations for the board and its 318 This includes specific configurations for the board and its
@@ -370,6 +367,14 @@ config MACH_IMX27IPCAM
370 Include support for IMX27 IPCAM platform. This includes specific 367 Include support for IMX27 IPCAM platform. This includes specific
371 configurations for the board and its peripherals. 368 configurations for the board and its peripherals.
372 369
370config MACH_IMX27_DT
371 bool "Support i.MX27 platforms from device tree"
372 select SOC_IMX27
373 select USE_OF
374 help
375 Include support for Freescale i.MX27 based platforms
376 using the device tree for discovery
377
373endif 378endif
374 379
375if ARCH_IMX_V6_V7 380if ARCH_IMX_V6_V7
@@ -486,6 +491,7 @@ config MACH_MX31MOBOARD
486 bool "Support mx31moboard platforms (EPFL Mobots group)" 491 bool "Support mx31moboard platforms (EPFL Mobots group)"
487 select SOC_IMX31 492 select SOC_IMX31
488 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 493 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
494 select IMX_HAVE_PLATFORM_IMX2_WDT
489 select IMX_HAVE_PLATFORM_IMX_I2C 495 select IMX_HAVE_PLATFORM_IMX_I2C
490 select IMX_HAVE_PLATFORM_IMX_UART 496 select IMX_HAVE_PLATFORM_IMX_UART
491 select IMX_HAVE_PLATFORM_IPU_CORE 497 select IMX_HAVE_PLATFORM_IPU_CORE
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 55db9c488f2b..ab939c5046c3 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,5 +1,3 @@
1obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
2
3obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o 1obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
4obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o 2obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
5 3
@@ -8,8 +6,8 @@ obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
8obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o 6obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
9obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o 7obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
10 8
11obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o 9obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
12obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o 10obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o
13 11
14obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o 12obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
15 13
@@ -41,6 +39,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
41obj-$(CONFIG_MACH_PCA100) += mach-pca100.o 39obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
42obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o 40obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
43obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o 41obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
42obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
44 43
45# i.MX31 based machines 44# i.MX31 based machines
46obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o 45obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
@@ -71,7 +70,6 @@ obj-$(CONFIG_CPU_V7) += head-v7.o
71AFLAGS_head-v7.o :=-Wa,-march=armv7-a 70AFLAGS_head-v7.o :=-Wa,-march=armv7-a
72obj-$(CONFIG_SMP) += platsmp.o 71obj-$(CONFIG_SMP) += platsmp.o
73obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 72obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
74obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
75obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o 73obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
76 74
77ifeq ($(CONFIG_PM),y) 75ifeq ($(CONFIG_PM),y)
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 6dfdbcc83afd..3851d8a27875 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -38,5 +38,8 @@ zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
38params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 38params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
39initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 39initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
40 40
41dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
42dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
43 imx53-qsb.dtb imx53-smd.dtb
41dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ 44dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
42 imx6q-sabrelite.dtb 45 imx6q-sabrelite.dtb
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index dc2d7a511d9b..b9a95ed75553 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/module.h> 23#include <linux/module.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <linux/of.h>
25 26
26#include <asm/div64.h> 27#include <asm/div64.h>
27 28
@@ -764,3 +765,20 @@ int __init mx27_clocks_init(unsigned long fref)
764 return 0; 765 return 0;
765} 766}
766 767
768#ifdef CONFIG_OF
769int __init mx27_clocks_init_dt(void)
770{
771 struct device_node *np;
772 u32 fref = 26000000; /* default */
773
774 for_each_compatible_node(np, NULL, "fixed-clock") {
775 if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
776 continue;
777
778 if (!of_property_read_u32(np, "clock-frequency", &fref))
779 break;
780 }
781
782 return mx27_clocks_init(fref);
783}
784#endif
diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
index 988a28178d4c..3a943cd4159f 100644
--- a/arch/arm/mach-imx/clock-imx31.c
+++ b/arch/arm/mach-imx/clock-imx31.c
@@ -32,7 +32,7 @@
32#include <mach/mx31.h> 32#include <mach/mx31.h>
33#include <mach/common.h> 33#include <mach/common.h>
34 34
35#include "crmregs-imx31.h" 35#include "crmregs-imx3.h"
36 36
37#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */ 37#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
38 38
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index ac8238caecb9..1e279af656ad 100644
--- a/arch/arm/mach-imx/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -27,23 +27,7 @@
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/common.h> 28#include <mach/common.h>
29 29
30#define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR) 30#include "crmregs-imx3.h"
31
32#define CCM_CCMR 0x00
33#define CCM_PDR0 0x04
34#define CCM_PDR1 0x08
35#define CCM_PDR2 0x0C
36#define CCM_PDR3 0x10
37#define CCM_PDR4 0x14
38#define CCM_RCSR 0x18
39#define CCM_MPCTL 0x1C
40#define CCM_PPCTL 0x20
41#define CCM_ACMR 0x24
42#define CCM_COSR 0x28
43#define CCM_CGR0 0x2C
44#define CCM_CGR1 0x30
45#define CCM_CGR2 0x34
46#define CCM_CGR3 0x38
47 31
48#ifdef HAVE_SET_RATE_SUPPORT 32#ifdef HAVE_SET_RATE_SUPPORT
49static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost) 33static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
@@ -111,14 +95,14 @@ static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
111 95
112static unsigned long get_rate_mpll(void) 96static unsigned long get_rate_mpll(void)
113{ 97{
114 ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL); 98 ulong mpctl = __raw_readl(MX35_CCM_MPCTL);
115 99
116 return mxc_decode_pll(mpctl, 24000000); 100 return mxc_decode_pll(mpctl, 24000000);
117} 101}
118 102
119static unsigned long get_rate_ppll(void) 103static unsigned long get_rate_ppll(void)
120{ 104{
121 ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL); 105 ulong ppctl = __raw_readl(MX35_CCM_PPCTL);
122 106
123 return mxc_decode_pll(ppctl, 24000000); 107 return mxc_decode_pll(ppctl, 24000000);
124} 108}
@@ -148,7 +132,7 @@ static struct arm_ahb_div clk_consumer[] = {
148 132
149static unsigned long get_rate_arm(void) 133static unsigned long get_rate_arm(void)
150{ 134{
151 unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); 135 unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
152 struct arm_ahb_div *aad; 136 struct arm_ahb_div *aad;
153 unsigned long fref = get_rate_mpll(); 137 unsigned long fref = get_rate_mpll();
154 138
@@ -161,7 +145,7 @@ static unsigned long get_rate_arm(void)
161 145
162static unsigned long get_rate_ahb(struct clk *clk) 146static unsigned long get_rate_ahb(struct clk *clk)
163{ 147{
164 unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); 148 unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
165 struct arm_ahb_div *aad; 149 struct arm_ahb_div *aad;
166 unsigned long fref = get_rate_arm(); 150 unsigned long fref = get_rate_arm();
167 151
@@ -177,8 +161,8 @@ static unsigned long get_rate_ipg(struct clk *clk)
177 161
178static unsigned long get_rate_uart(struct clk *clk) 162static unsigned long get_rate_uart(struct clk *clk)
179{ 163{
180 unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3); 164 unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
181 unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4); 165 unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
182 unsigned long div = ((pdr4 >> 10) & 0x3f) + 1; 166 unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
183 167
184 if (pdr3 & (1 << 14)) 168 if (pdr3 & (1 << 14))
@@ -189,7 +173,7 @@ static unsigned long get_rate_uart(struct clk *clk)
189 173
190static unsigned long get_rate_sdhc(struct clk *clk) 174static unsigned long get_rate_sdhc(struct clk *clk)
191{ 175{
192 unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3); 176 unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
193 unsigned long div, rate; 177 unsigned long div, rate;
194 178
195 if (pdr3 & (1 << 6)) 179 if (pdr3 & (1 << 6))
@@ -215,7 +199,7 @@ static unsigned long get_rate_sdhc(struct clk *clk)
215 199
216static unsigned long get_rate_mshc(struct clk *clk) 200static unsigned long get_rate_mshc(struct clk *clk)
217{ 201{
218 unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1); 202 unsigned long pdr1 = __raw_readl(MXC_CCM_PDR1);
219 unsigned long div1, div2, rate; 203 unsigned long div1, div2, rate;
220 204
221 if (pdr1 & (1 << 7)) 205 if (pdr1 & (1 << 7))
@@ -231,7 +215,7 @@ static unsigned long get_rate_mshc(struct clk *clk)
231 215
232static unsigned long get_rate_ssi(struct clk *clk) 216static unsigned long get_rate_ssi(struct clk *clk)
233{ 217{
234 unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2); 218 unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
235 unsigned long div1, div2, rate; 219 unsigned long div1, div2, rate;
236 220
237 if (pdr2 & (1 << 6)) 221 if (pdr2 & (1 << 6))
@@ -256,7 +240,7 @@ static unsigned long get_rate_ssi(struct clk *clk)
256 240
257static unsigned long get_rate_csi(struct clk *clk) 241static unsigned long get_rate_csi(struct clk *clk)
258{ 242{
259 unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2); 243 unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
260 unsigned long rate; 244 unsigned long rate;
261 245
262 if (pdr2 & (1 << 7)) 246 if (pdr2 & (1 << 7))
@@ -269,7 +253,7 @@ static unsigned long get_rate_csi(struct clk *clk)
269 253
270static unsigned long get_rate_otg(struct clk *clk) 254static unsigned long get_rate_otg(struct clk *clk)
271{ 255{
272 unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4); 256 unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
273 unsigned long rate; 257 unsigned long rate;
274 258
275 if (pdr4 & (1 << 9)) 259 if (pdr4 & (1 << 9))
@@ -282,8 +266,8 @@ static unsigned long get_rate_otg(struct clk *clk)
282 266
283static unsigned long get_rate_ipg_per(struct clk *clk) 267static unsigned long get_rate_ipg_per(struct clk *clk)
284{ 268{
285 unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); 269 unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
286 unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4); 270 unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
287 unsigned long div; 271 unsigned long div;
288 272
289 if (pdr0 & (1 << 26)) { 273 if (pdr0 & (1 << 26)) {
@@ -297,7 +281,7 @@ static unsigned long get_rate_ipg_per(struct clk *clk)
297 281
298static unsigned long get_rate_hsp(struct clk *clk) 282static unsigned long get_rate_hsp(struct clk *clk)
299{ 283{
300 unsigned long hsp_podf = (__raw_readl(CCM_BASE + CCM_PDR0) >> 20) & 0x03; 284 unsigned long hsp_podf = (__raw_readl(MXC_CCM_PDR0) >> 20) & 0x03;
301 unsigned long fref = get_rate_mpll(); 285 unsigned long fref = get_rate_mpll();
302 286
303 if (fref > 400 * 1000 * 1000) { 287 if (fref > 400 * 1000 * 1000) {
@@ -345,7 +329,7 @@ static void clk_cgr_disable(struct clk *clk)
345#define DEFINE_CLOCK(name, i, er, es, gr, sr) \ 329#define DEFINE_CLOCK(name, i, er, es, gr, sr) \
346 static struct clk name = { \ 330 static struct clk name = { \
347 .id = i, \ 331 .id = i, \
348 .enable_reg = CCM_BASE + er, \ 332 .enable_reg = er, \
349 .enable_shift = es, \ 333 .enable_shift = es, \
350 .get_rate = gr, \ 334 .get_rate = gr, \
351 .set_rate = sr, \ 335 .set_rate = sr, \
@@ -353,59 +337,59 @@ static void clk_cgr_disable(struct clk *clk)
353 .disable = clk_cgr_disable, \ 337 .disable = clk_cgr_disable, \
354 } 338 }
355 339
356DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); 340DEFINE_CLOCK(asrc_clk, 0, MX35_CCM_CGR0, 0, NULL, NULL);
357DEFINE_CLOCK(pata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); 341DEFINE_CLOCK(pata_clk, 0, MX35_CCM_CGR0, 2, get_rate_ipg, NULL);
358/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */ 342/* DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR0, 4, NULL, NULL); */
359DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); 343DEFINE_CLOCK(can1_clk, 0, MX35_CCM_CGR0, 6, get_rate_ipg, NULL);
360DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); 344DEFINE_CLOCK(can2_clk, 1, MX35_CCM_CGR0, 8, get_rate_ipg, NULL);
361DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL); 345DEFINE_CLOCK(cspi1_clk, 0, MX35_CCM_CGR0, 10, get_rate_ipg, NULL);
362DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL); 346DEFINE_CLOCK(cspi2_clk, 1, MX35_CCM_CGR0, 12, get_rate_ipg, NULL);
363DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL); 347DEFINE_CLOCK(ect_clk, 0, MX35_CCM_CGR0, 14, get_rate_ipg, NULL);
364DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL); 348DEFINE_CLOCK(edio_clk, 0, MX35_CCM_CGR0, 16, NULL, NULL);
365DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL); 349DEFINE_CLOCK(emi_clk, 0, MX35_CCM_CGR0, 18, get_rate_ipg, NULL);
366DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg, NULL); 350DEFINE_CLOCK(epit1_clk, 0, MX35_CCM_CGR0, 20, get_rate_ipg, NULL);
367DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg, NULL); 351DEFINE_CLOCK(epit2_clk, 1, MX35_CCM_CGR0, 22, get_rate_ipg, NULL);
368DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL); 352DEFINE_CLOCK(esai_clk, 0, MX35_CCM_CGR0, 24, NULL, NULL);
369DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL); 353DEFINE_CLOCK(esdhc1_clk, 0, MX35_CCM_CGR0, 26, get_rate_sdhc, NULL);
370DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL); 354DEFINE_CLOCK(esdhc2_clk, 1, MX35_CCM_CGR0, 28, get_rate_sdhc, NULL);
371DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL); 355DEFINE_CLOCK(esdhc3_clk, 2, MX35_CCM_CGR0, 30, get_rate_sdhc, NULL);
372 356
373DEFINE_CLOCK(fec_clk, 0, CCM_CGR1, 0, get_rate_ipg, NULL); 357DEFINE_CLOCK(fec_clk, 0, MX35_CCM_CGR1, 0, get_rate_ipg, NULL);
374DEFINE_CLOCK(gpio1_clk, 0, CCM_CGR1, 2, NULL, NULL); 358DEFINE_CLOCK(gpio1_clk, 0, MX35_CCM_CGR1, 2, NULL, NULL);
375DEFINE_CLOCK(gpio2_clk, 1, CCM_CGR1, 4, NULL, NULL); 359DEFINE_CLOCK(gpio2_clk, 1, MX35_CCM_CGR1, 4, NULL, NULL);
376DEFINE_CLOCK(gpio3_clk, 2, CCM_CGR1, 6, NULL, NULL); 360DEFINE_CLOCK(gpio3_clk, 2, MX35_CCM_CGR1, 6, NULL, NULL);
377DEFINE_CLOCK(gpt_clk, 0, CCM_CGR1, 8, get_rate_ipg, NULL); 361DEFINE_CLOCK(gpt_clk, 0, MX35_CCM_CGR1, 8, get_rate_ipg, NULL);
378DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL); 362DEFINE_CLOCK(i2c1_clk, 0, MX35_CCM_CGR1, 10, get_rate_ipg_per, NULL);
379DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL); 363DEFINE_CLOCK(i2c2_clk, 1, MX35_CCM_CGR1, 12, get_rate_ipg_per, NULL);
380DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL); 364DEFINE_CLOCK(i2c3_clk, 2, MX35_CCM_CGR1, 14, get_rate_ipg_per, NULL);
381DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL); 365DEFINE_CLOCK(iomuxc_clk, 0, MX35_CCM_CGR1, 16, NULL, NULL);
382DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_hsp, NULL); 366DEFINE_CLOCK(ipu_clk, 0, MX35_CCM_CGR1, 18, get_rate_hsp, NULL);
383DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL); 367DEFINE_CLOCK(kpp_clk, 0, MX35_CCM_CGR1, 20, get_rate_ipg, NULL);
384DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL); 368DEFINE_CLOCK(mlb_clk, 0, MX35_CCM_CGR1, 22, get_rate_ahb, NULL);
385DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL); 369DEFINE_CLOCK(mshc_clk, 0, MX35_CCM_CGR1, 24, get_rate_mshc, NULL);
386DEFINE_CLOCK(owire_clk, 0, CCM_CGR1, 26, get_rate_ipg_per, NULL); 370DEFINE_CLOCK(owire_clk, 0, MX35_CCM_CGR1, 26, get_rate_ipg_per, NULL);
387DEFINE_CLOCK(pwm_clk, 0, CCM_CGR1, 28, get_rate_ipg_per, NULL); 371DEFINE_CLOCK(pwm_clk, 0, MX35_CCM_CGR1, 28, get_rate_ipg_per, NULL);
388DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL); 372DEFINE_CLOCK(rngc_clk, 0, MX35_CCM_CGR1, 30, get_rate_ipg, NULL);
389 373
390DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL); 374DEFINE_CLOCK(rtc_clk, 0, MX35_CCM_CGR2, 0, get_rate_ipg, NULL);
391DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL); 375DEFINE_CLOCK(rtic_clk, 0, MX35_CCM_CGR2, 2, get_rate_ahb, NULL);
392DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL); 376DEFINE_CLOCK(scc_clk, 0, MX35_CCM_CGR2, 4, get_rate_ipg, NULL);
393DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL); 377DEFINE_CLOCK(sdma_clk, 0, MX35_CCM_CGR2, 6, NULL, NULL);
394DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL); 378DEFINE_CLOCK(spba_clk, 0, MX35_CCM_CGR2, 8, get_rate_ipg, NULL);
395DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL); 379DEFINE_CLOCK(spdif_clk, 0, MX35_CCM_CGR2, 10, NULL, NULL);
396DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL); 380DEFINE_CLOCK(ssi1_clk, 0, MX35_CCM_CGR2, 12, get_rate_ssi, NULL);
397DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL); 381DEFINE_CLOCK(ssi2_clk, 1, MX35_CCM_CGR2, 14, get_rate_ssi, NULL);
398DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL); 382DEFINE_CLOCK(uart1_clk, 0, MX35_CCM_CGR2, 16, get_rate_uart, NULL);
399DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL); 383DEFINE_CLOCK(uart2_clk, 1, MX35_CCM_CGR2, 18, get_rate_uart, NULL);
400DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL); 384DEFINE_CLOCK(uart3_clk, 2, MX35_CCM_CGR2, 20, get_rate_uart, NULL);
401DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL); 385DEFINE_CLOCK(usbotg_clk, 0, MX35_CCM_CGR2, 22, get_rate_otg, NULL);
402DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); 386DEFINE_CLOCK(wdog_clk, 0, MX35_CCM_CGR2, 24, NULL, NULL);
403DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); 387DEFINE_CLOCK(max_clk, 0, MX35_CCM_CGR2, 26, NULL, NULL);
404DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL); 388DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR2, 30, NULL, NULL);
405 389
406DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); 390DEFINE_CLOCK(csi_clk, 0, MX35_CCM_CGR3, 0, get_rate_csi, NULL);
407DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); 391DEFINE_CLOCK(iim_clk, 0, MX35_CCM_CGR3, 2, NULL, NULL);
408DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); 392DEFINE_CLOCK(gpu2d_clk, 0, MX35_CCM_CGR3, 4, NULL, NULL);
409 393
410DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL); 394DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL);
411 395
@@ -422,7 +406,7 @@ static unsigned long get_rate_nfc(struct clk *clk)
422{ 406{
423 unsigned long div1; 407 unsigned long div1;
424 408
425 div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1; 409 div1 = (__raw_readl(MX35_CCM_PDR4) >> 28) + 1;
426 410
427 return get_rate_ahb(NULL) / div1; 411 return get_rate_ahb(NULL) / div1;
428} 412}
@@ -518,11 +502,11 @@ int __init mx35_clocks_init()
518 /* Turn off all clocks except the ones we need to survive, namely: 502 /* Turn off all clocks except the ones we need to survive, namely:
519 * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart 503 * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
520 */ 504 */
521 __raw_writel((3 << 18), CCM_BASE + CCM_CGR0); 505 __raw_writel((3 << 18), MX35_CCM_CGR0);
522 __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16), 506 __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
523 CCM_BASE + CCM_CGR1); 507 MX35_CCM_CGR1);
524 __raw_writel(cgr2, CCM_BASE + CCM_CGR2); 508 __raw_writel(cgr2, MX35_CCM_CGR2);
525 __raw_writel(0, CCM_BASE + CCM_CGR3); 509 __raw_writel(0, MX35_CCM_CGR3);
526 510
527 clk_enable(&iim_clk); 511 clk_enable(&iim_clk);
528 imx_print_silicon_rev("i.MX35", mx35_revision()); 512 imx_print_silicon_rev("i.MX35", mx35_revision());
@@ -533,7 +517,7 @@ int __init mx35_clocks_init()
533 * extra clocks turned on, otherwise the MX35 boot ROM code will 517 * extra clocks turned on, otherwise the MX35 boot ROM code will
534 * hang after a watchdog reset. 518 * hang after a watchdog reset.
535 */ 519 */
536 if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) { 520 if (!(__raw_readl(MX35_CCM_RCSR) & (3 << 10))) {
537 /* Additionally turn on UART1, SCC, and IIM clocks */ 521 /* Additionally turn on UART1, SCC, and IIM clocks */
538 clk_enable(&iim_clk); 522 clk_enable(&iim_clk);
539 clk_enable(&uart1_clk); 523 clk_enable(&uart1_clk);
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 2d88f8b9a454..111c328f5420 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -329,6 +329,12 @@
329#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) 329#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
330#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) 330#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
331 331
332#define BP_CCOSR_CKO1_EN 7
333#define BP_CCOSR_CKO1_PODF 4
334#define BM_CCOSR_CKO1_PODF (0x7 << 4)
335#define BP_CCOSR_CKO1_SEL 0
336#define BM_CCOSR_CKO1_SEL (0xf << 0)
337
332#define FREQ_480M 480000000 338#define FREQ_480M 480000000
333#define FREQ_528M 528000000 339#define FREQ_528M 528000000
334#define FREQ_594M 594000000 340#define FREQ_594M 594000000
@@ -393,6 +399,7 @@ static struct clk ipu1_di1_clk;
393static struct clk ipu2_di0_clk; 399static struct clk ipu2_di0_clk;
394static struct clk ipu2_di1_clk; 400static struct clk ipu2_di1_clk;
395static struct clk enfc_clk; 401static struct clk enfc_clk;
402static struct clk cko1_clk;
396static struct clk dummy_clk = {}; 403static struct clk dummy_clk = {};
397 404
398static unsigned long external_high_reference; 405static unsigned long external_high_reference;
@@ -938,6 +945,24 @@ static void _clk_disable(struct clk *clk)
938 writel_relaxed(reg, clk->enable_reg); 945 writel_relaxed(reg, clk->enable_reg);
939} 946}
940 947
948static int _clk_enable_1b(struct clk *clk)
949{
950 u32 reg;
951 reg = readl_relaxed(clk->enable_reg);
952 reg |= 0x1 << clk->enable_shift;
953 writel_relaxed(reg, clk->enable_reg);
954
955 return 0;
956}
957
958static void _clk_disable_1b(struct clk *clk)
959{
960 u32 reg;
961 reg = readl_relaxed(clk->enable_reg);
962 reg &= ~(0x1 << clk->enable_shift);
963 writel_relaxed(reg, clk->enable_reg);
964}
965
941struct divider { 966struct divider {
942 struct clk *clk; 967 struct clk *clk;
943 void __iomem *reg; 968 void __iomem *reg;
@@ -983,6 +1008,7 @@ DEF_CLK_DIV1(ipu2_di0_pre_div, &ipu2_di0_pre_clk, CSCDR2, IPU2_DI0_PRE);
983DEF_CLK_DIV1(ipu2_di1_pre_div, &ipu2_di1_pre_clk, CSCDR2, IPU2_DI1_PRE); 1008DEF_CLK_DIV1(ipu2_di1_pre_div, &ipu2_di1_pre_clk, CSCDR2, IPU2_DI1_PRE);
984DEF_CLK_DIV1(ipu1_div, &ipu1_clk, CSCDR3, IPU1_HSP); 1009DEF_CLK_DIV1(ipu1_div, &ipu1_clk, CSCDR3, IPU1_HSP);
985DEF_CLK_DIV1(ipu2_div, &ipu2_clk, CSCDR3, IPU2_HSP); 1010DEF_CLK_DIV1(ipu2_div, &ipu2_clk, CSCDR3, IPU2_HSP);
1011DEF_CLK_DIV1(cko1_div, &cko1_clk, CCOSR, CKO1);
986 1012
987#define DEF_CLK_DIV2(d, c, r, b) \ 1013#define DEF_CLK_DIV2(d, c, r, b) \
988 static struct divider d = { \ 1014 static struct divider d = { \
@@ -1038,6 +1064,7 @@ static struct divider *dividers[] = {
1038 &enfc_div, 1064 &enfc_div,
1039 &spdif_div, 1065 &spdif_div,
1040 &asrc_serial_div, 1066 &asrc_serial_div,
1067 &cko1_div,
1041}; 1068};
1042 1069
1043static unsigned long ldb_di_clk_get_rate(struct clk *clk) 1070static unsigned long ldb_di_clk_get_rate(struct clk *clk)
@@ -1625,6 +1652,32 @@ DEF_IPU_DI_MUX(CSCDR2, 2, 1);
1625DEF_IPU_MUX(1); 1652DEF_IPU_MUX(1);
1626DEF_IPU_MUX(2); 1653DEF_IPU_MUX(2);
1627 1654
1655static struct multiplexer cko1_mux = {
1656 .clk = &cko1_clk,
1657 .reg = CCOSR,
1658 .bp = BP_CCOSR_CKO1_SEL,
1659 .bm = BM_CCOSR_CKO1_SEL,
1660 .parents = {
1661 &pll3_usb_otg,
1662 &pll2_bus,
1663 &pll1_sys,
1664 &pll5_video,
1665 &dummy_clk,
1666 &axi_clk,
1667 &enfc_clk,
1668 &ipu1_di0_clk,
1669 &ipu1_di1_clk,
1670 &ipu2_di0_clk,
1671 &ipu2_di1_clk,
1672 &ahb_clk,
1673 &ipg_clk,
1674 &ipg_perclk,
1675 &ckil_clk,
1676 &pll4_audio,
1677 NULL
1678 },
1679};
1680
1628static struct multiplexer *multiplexers[] = { 1681static struct multiplexer *multiplexers[] = {
1629 &axi_mux, 1682 &axi_mux,
1630 &periph_mux, 1683 &periph_mux,
@@ -1667,6 +1720,7 @@ static struct multiplexer *multiplexers[] = {
1667 &ipu2_di1_mux, 1720 &ipu2_di1_mux,
1668 &ipu1_mux, 1721 &ipu1_mux,
1669 &ipu2_mux, 1722 &ipu2_mux,
1723 &cko1_mux,
1670}; 1724};
1671 1725
1672static int _clk_set_parent(struct clk *clk, struct clk *parent) 1726static int _clk_set_parent(struct clk *clk, struct clk *parent)
@@ -1690,7 +1744,7 @@ static int _clk_set_parent(struct clk *clk, struct clk *parent)
1690 break; 1744 break;
1691 i++; 1745 i++;
1692 } 1746 }
1693 if (!m->parents[i]) 1747 if (!m->parents[i] || m->parents[i] == &dummy_clk)
1694 return -EINVAL; 1748 return -EINVAL;
1695 1749
1696 val = readl_relaxed(m->reg); 1750 val = readl_relaxed(m->reg);
@@ -1745,6 +1799,20 @@ DEF_NG_CLK(asrc_serial_clk, &pll3_usb_otg);
1745 .secondary = s, \ 1799 .secondary = s, \
1746 } 1800 }
1747 1801
1802#define DEF_CLK_1B(name, er, es, p, s) \
1803 static struct clk name = { \
1804 .enable_reg = er, \
1805 .enable_shift = es, \
1806 .enable = _clk_enable_1b, \
1807 .disable = _clk_disable_1b, \
1808 .get_rate = _clk_get_rate, \
1809 .set_rate = _clk_set_rate, \
1810 .round_rate = _clk_round_rate, \
1811 .set_parent = _clk_set_parent, \
1812 .parent = p, \
1813 .secondary = s, \
1814 }
1815
1748DEF_CLK(aips_tz1_clk, CCGR0, CG0, &ahb_clk, NULL); 1816DEF_CLK(aips_tz1_clk, CCGR0, CG0, &ahb_clk, NULL);
1749DEF_CLK(aips_tz2_clk, CCGR0, CG1, &ahb_clk, NULL); 1817DEF_CLK(aips_tz2_clk, CCGR0, CG1, &ahb_clk, NULL);
1750DEF_CLK(apbh_dma_clk, CCGR0, CG2, &ahb_clk, NULL); 1818DEF_CLK(apbh_dma_clk, CCGR0, CG2, &ahb_clk, NULL);
@@ -1811,6 +1879,7 @@ DEF_CLK(usdhc4_clk, CCGR6, CG4, &pll2_pfd_400m, NULL);
1811DEF_CLK(emi_slow_clk, CCGR6, CG5, &axi_clk, NULL); 1879DEF_CLK(emi_slow_clk, CCGR6, CG5, &axi_clk, NULL);
1812DEF_CLK(vdo_axi_clk, CCGR6, CG6, &axi_clk, NULL); 1880DEF_CLK(vdo_axi_clk, CCGR6, CG6, &axi_clk, NULL);
1813DEF_CLK(vpu_clk, CCGR6, CG7, &axi_clk, NULL); 1881DEF_CLK(vpu_clk, CCGR6, CG7, &axi_clk, NULL);
1882DEF_CLK_1B(cko1_clk, CCOSR, BP_CCOSR_CKO1_EN, &pll2_bus, NULL);
1814 1883
1815static int pcie_clk_enable(struct clk *clk) 1884static int pcie_clk_enable(struct clk *clk)
1816{ 1885{
@@ -1922,6 +1991,7 @@ static struct clk_lookup lookups[] = {
1922 _REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk), 1991 _REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
1923 _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk), 1992 _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
1924 _REGISTER_CLOCK(NULL, "sata_clk", sata_clk), 1993 _REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
1994 _REGISTER_CLOCK(NULL, "cko1_clk", cko1_clk),
1925}; 1995};
1926 1996
1927int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) 1997int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
@@ -2029,6 +2099,8 @@ int __init mx6q_clocks_init(void)
2029 clk_set_rate(&usdhc3_clk, 49500000); 2099 clk_set_rate(&usdhc3_clk, 49500000);
2030 clk_set_rate(&usdhc4_clk, 49500000); 2100 clk_set_rate(&usdhc4_clk, 49500000);
2031 2101
2102 clk_set_parent(&cko1_clk, &ahb_clk);
2103
2032 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); 2104 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
2033 base = of_iomap(np, 0); 2105 base = of_iomap(np, 0);
2034 WARN_ON(!base); 2106 WARN_ON(!base);
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index 5e2e7a843860..aa15c517d06e 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -149,39 +149,3 @@ int mx50_revision(void)
149 return mx5_cpu_rev; 149 return mx5_cpu_rev;
150} 150}
151EXPORT_SYMBOL(mx50_revision); 151EXPORT_SYMBOL(mx50_revision);
152
153static int __init post_cpu_init(void)
154{
155 unsigned int reg;
156 void __iomem *base;
157
158 if (cpu_is_mx51() || cpu_is_mx53()) {
159 if (cpu_is_mx51())
160 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
161 else
162 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
163
164 __raw_writel(0x0, base + 0x40);
165 __raw_writel(0x0, base + 0x44);
166 __raw_writel(0x0, base + 0x48);
167 __raw_writel(0x0, base + 0x4C);
168 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
169 __raw_writel(reg, base + 0x50);
170
171 if (cpu_is_mx51())
172 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
173 else
174 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
175
176 __raw_writel(0x0, base + 0x40);
177 __raw_writel(0x0, base + 0x44);
178 __raw_writel(0x0, base + 0x48);
179 __raw_writel(0x0, base + 0x4C);
180 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
181 __raw_writel(reg, base + 0x50);
182 }
183
184 return 0;
185}
186
187postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-imx/crmregs-imx31.h b/arch/arm/mach-imx/crmregs-imx3.h
index 37a8a07beda3..53141273df45 100644
--- a/arch/arm/mach-imx/crmregs-imx31.h
+++ b/arch/arm/mach-imx/crmregs-imx3.h
@@ -24,23 +24,36 @@
24#define CKIH_CLK_FREQ_27MHZ 27000000 24#define CKIH_CLK_FREQ_27MHZ 27000000
25#define CKIL_CLK_FREQ 32768 25#define CKIL_CLK_FREQ 32768
26 26
27#define MXC_CCM_BASE MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) 27#define MXC_CCM_BASE (cpu_is_mx31() ? \
28MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR))
28 29
29/* Register addresses */ 30/* Register addresses */
30#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) 31#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
31#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04) 32#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04)
32#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08) 33#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08)
34#define MX35_CCM_PDR2 (MXC_CCM_BASE + 0x0C)
33#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C) 35#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C)
36#define MX35_CCM_PDR3 (MXC_CCM_BASE + 0x10)
34#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10) 37#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10)
38#define MX35_CCM_PDR4 (MXC_CCM_BASE + 0x14)
35#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14) 39#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14)
40#define MX35_CCM_RCSR (MXC_CCM_BASE + 0x18)
36#define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18) 41#define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18)
42#define MX35_CCM_MPCTL (MXC_CCM_BASE + 0x1C)
37#define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C) 43#define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C)
44#define MX35_CCM_PPCTL (MXC_CCM_BASE + 0x20)
38#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20) 45#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20)
46#define MX35_CCM_ACMR (MXC_CCM_BASE + 0x24)
39#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24) 47#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24)
48#define MX35_CCM_COSR (MXC_CCM_BASE + 0x28)
40#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28) 49#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28)
50#define MX35_CCM_CGR0 (MXC_CCM_BASE + 0x2C)
41#define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C) 51#define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C)
52#define MX35_CCM_CGR1 (MXC_CCM_BASE + 0x30)
42#define MXC_CCM_LDC (MXC_CCM_BASE + 0x30) 53#define MXC_CCM_LDC (MXC_CCM_BASE + 0x30)
54#define MX35_CCM_CGR2 (MXC_CCM_BASE + 0x34)
43#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34) 55#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34)
56#define MX35_CCM_CGR3 (MXC_CCM_BASE + 0x38)
44#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38) 57#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38)
45#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C) 58#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C)
46#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40) 59#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40)
@@ -64,6 +77,7 @@
64#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) 77#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21)
65#define MXC_CCM_CCMR_LPM_OFFSET 14 78#define MXC_CCM_CCMR_LPM_OFFSET 14
66#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) 79#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
80#define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14)
67#define MXC_CCM_CCMR_FIRS_OFFSET 11 81#define MXC_CCM_CCMR_FIRS_OFFSET 11
68#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) 82#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11)
69#define MXC_CCM_CCMR_UPE (1 << 9) 83#define MXC_CCM_CCMR_UPE (1 << 9)
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
deleted file mode 100644
index 42afc29a7da8..000000000000
--- a/arch/arm/mach-imx/dma-v1.c
+++ /dev/null
@@ -1,846 +0,0 @@
1/*
2 * linux/arch/arm/plat-mxc/dma-v1.c
3 *
4 * i.MX DMA registration and IRQ dispatching
5 *
6 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
7 * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
8 * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/interrupt.h>
29#include <linux/err.h>
30#include <linux/errno.h>
31#include <linux/clk.h>
32#include <linux/scatterlist.h>
33#include <linux/io.h>
34
35#include <asm/system.h>
36#include <asm/irq.h>
37#include <mach/hardware.h>
38#include <mach/dma-v1.h>
39
40#define DMA_DCR 0x00 /* Control Register */
41#define DMA_DISR 0x04 /* Interrupt status Register */
42#define DMA_DIMR 0x08 /* Interrupt mask Register */
43#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
44#define DMA_DRTOSR 0x10 /* Request timeout Register */
45#define DMA_DSESR 0x14 /* Transfer Error Status Register */
46#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
47#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
48#define DMA_WSRA 0x40 /* W-Size Register A */
49#define DMA_XSRA 0x44 /* X-Size Register A */
50#define DMA_YSRA 0x48 /* Y-Size Register A */
51#define DMA_WSRB 0x4c /* W-Size Register B */
52#define DMA_XSRB 0x50 /* X-Size Register B */
53#define DMA_YSRB 0x54 /* Y-Size Register B */
54#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
55#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
56#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
57#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
58#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
59#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
60#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
61#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
62#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
63
64#define DCR_DRST (1<<1)
65#define DCR_DEN (1<<0)
66#define DBTOCR_EN (1<<15)
67#define DBTOCR_CNT(x) ((x) & 0x7fff)
68#define CNTR_CNT(x) ((x) & 0xffffff)
69#define CCR_ACRPT (1<<14)
70#define CCR_DMOD_LINEAR (0x0 << 12)
71#define CCR_DMOD_2D (0x1 << 12)
72#define CCR_DMOD_FIFO (0x2 << 12)
73#define CCR_DMOD_EOBFIFO (0x3 << 12)
74#define CCR_SMOD_LINEAR (0x0 << 10)
75#define CCR_SMOD_2D (0x1 << 10)
76#define CCR_SMOD_FIFO (0x2 << 10)
77#define CCR_SMOD_EOBFIFO (0x3 << 10)
78#define CCR_MDIR_DEC (1<<9)
79#define CCR_MSEL_B (1<<8)
80#define CCR_DSIZ_32 (0x0 << 6)
81#define CCR_DSIZ_8 (0x1 << 6)
82#define CCR_DSIZ_16 (0x2 << 6)
83#define CCR_SSIZ_32 (0x0 << 4)
84#define CCR_SSIZ_8 (0x1 << 4)
85#define CCR_SSIZ_16 (0x2 << 4)
86#define CCR_REN (1<<3)
87#define CCR_RPT (1<<2)
88#define CCR_FRC (1<<1)
89#define CCR_CEN (1<<0)
90#define RTOR_EN (1<<15)
91#define RTOR_CLK (1<<14)
92#define RTOR_PSC (1<<13)
93
94/*
95 * struct imx_dma_channel - i.MX specific DMA extension
96 * @name: name specified by DMA client
97 * @irq_handler: client callback for end of transfer
98 * @err_handler: client callback for error condition
99 * @data: clients context data for callbacks
100 * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
101 * @sg: pointer to the actual read/written chunk for scatter-gather emulation
102 * @resbytes: total residual number of bytes to transfer
103 * (it can be lower or same as sum of SG mapped chunk sizes)
104 * @sgcount: number of chunks to be read/written
105 *
106 * Structure is used for IMX DMA processing. It would be probably good
107 * @struct dma_struct in the future for external interfacing and use
108 * @struct imx_dma_channel only as extension to it.
109 */
110
111struct imx_dma_channel {
112 const char *name;
113 void (*irq_handler) (int, void *);
114 void (*err_handler) (int, void *, int errcode);
115 void (*prog_handler) (int, void *, struct scatterlist *);
116 void *data;
117 unsigned int dma_mode;
118 struct scatterlist *sg;
119 unsigned int resbytes;
120 int dma_num;
121
122 int in_use;
123
124 u32 ccr_from_device;
125 u32 ccr_to_device;
126
127 struct timer_list watchdog;
128
129 int hw_chaining;
130};
131
132static void __iomem *imx_dmav1_baseaddr;
133
134static void imx_dmav1_writel(unsigned val, unsigned offset)
135{
136 __raw_writel(val, imx_dmav1_baseaddr + offset);
137}
138
139static unsigned imx_dmav1_readl(unsigned offset)
140{
141 return __raw_readl(imx_dmav1_baseaddr + offset);
142}
143
144static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
145
146static struct clk *dma_clk;
147
148static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
149{
150 if (cpu_is_mx27())
151 return imxdma->hw_chaining;
152 else
153 return 0;
154}
155
156/*
157 * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
158 */
159static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
160{
161 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
162 unsigned long now;
163
164 if (!imxdma->name) {
165 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
166 __func__, channel);
167 return 0;
168 }
169
170 now = min(imxdma->resbytes, sg->length);
171 if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
172 imxdma->resbytes -= now;
173
174 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
175 imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
176 else
177 imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
178
179 imx_dmav1_writel(now, DMA_CNTR(channel));
180
181 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
182 "size 0x%08x\n", channel,
183 imx_dmav1_readl(DMA_DAR(channel)),
184 imx_dmav1_readl(DMA_SAR(channel)),
185 imx_dmav1_readl(DMA_CNTR(channel)));
186
187 return now;
188}
189
190/**
191 * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
192 * device transfer
193 *
194 * @channel: i.MX DMA channel number
195 * @dma_address: the DMA/physical memory address of the linear data block
196 * to transfer
197 * @dma_length: length of the data block in bytes
198 * @dev_addr: physical device port address
199 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
200 * or %DMA_MODE_WRITE from memory to the device
201 *
202 * Return value: if incorrect parameters are provided -%EINVAL.
203 * Zero indicates success.
204 */
205int
206imx_dma_setup_single(int channel, dma_addr_t dma_address,
207 unsigned int dma_length, unsigned int dev_addr,
208 unsigned int dmamode)
209{
210 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
211
212 imxdma->sg = NULL;
213 imxdma->dma_mode = dmamode;
214
215 if (!dma_address) {
216 printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
217 channel);
218 return -EINVAL;
219 }
220
221 if (!dma_length) {
222 printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
223 channel);
224 return -EINVAL;
225 }
226
227 if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
228 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
229 "dev_addr=0x%08x for read\n",
230 channel, __func__, (unsigned int)dma_address,
231 dma_length, dev_addr);
232
233 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
234 imx_dmav1_writel(dma_address, DMA_DAR(channel));
235 imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
236 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
237 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
238 "dev_addr=0x%08x for write\n",
239 channel, __func__, (unsigned int)dma_address,
240 dma_length, dev_addr);
241
242 imx_dmav1_writel(dma_address, DMA_SAR(channel));
243 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
244 imx_dmav1_writel(imxdma->ccr_to_device,
245 DMA_CCR(channel));
246 } else {
247 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
248 channel);
249 return -EINVAL;
250 }
251
252 imx_dmav1_writel(dma_length, DMA_CNTR(channel));
253
254 return 0;
255}
256EXPORT_SYMBOL(imx_dma_setup_single);
257
258/**
259 * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
260 * @channel: i.MX DMA channel number
261 * @sg: pointer to the scatter-gather list/vector
262 * @sgcount: scatter-gather list hungs count
263 * @dma_length: total length of the transfer request in bytes
264 * @dev_addr: physical device port address
265 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
266 * or %DMA_MODE_WRITE from memory to the device
267 *
268 * The function sets up DMA channel state and registers to be ready for
269 * transfer specified by provided parameters. The scatter-gather emulation
270 * is set up according to the parameters.
271 *
272 * The full preparation of the transfer requires setup of more register
273 * by the caller before imx_dma_enable() can be called.
274 *
275 * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
276 *
277 * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
278 *
279 * %CCR(channel) has to specify transfer parameters, the next settings is
280 * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
281 * specified
282 *
283 * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
284 *
285 * The typical setup for %DMA_MODE_WRITE is specified by next options
286 * combination
287 *
288 * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
289 *
290 * Be careful here and do not mistakenly mix source and target device
291 * port sizes constants, they are really different:
292 * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
293 * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
294 *
295 * Return value: if incorrect parameters are provided -%EINVAL.
296 * Zero indicates success.
297 */
298int
299imx_dma_setup_sg(int channel,
300 struct scatterlist *sg, unsigned int sgcount,
301 unsigned int dma_length, unsigned int dev_addr,
302 unsigned int dmamode)
303{
304 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
305
306 if (imxdma->in_use)
307 return -EBUSY;
308
309 imxdma->sg = sg;
310 imxdma->dma_mode = dmamode;
311 imxdma->resbytes = dma_length;
312
313 if (!sg || !sgcount) {
314 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
315 channel);
316 return -EINVAL;
317 }
318
319 if (!sg->length) {
320 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
321 channel);
322 return -EINVAL;
323 }
324
325 if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
326 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
327 "dev_addr=0x%08x for read\n",
328 channel, __func__, sg, sgcount, dma_length, dev_addr);
329
330 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
331 imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
332 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
333 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
334 "dev_addr=0x%08x for write\n",
335 channel, __func__, sg, sgcount, dma_length, dev_addr);
336
337 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
338 imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
339 } else {
340 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
341 channel);
342 return -EINVAL;
343 }
344
345 imx_dma_sg_next(channel, sg);
346
347 return 0;
348}
349EXPORT_SYMBOL(imx_dma_setup_sg);
350
351int
352imx_dma_config_channel(int channel, unsigned int config_port,
353 unsigned int config_mem, unsigned int dmareq, int hw_chaining)
354{
355 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
356 u32 dreq = 0;
357
358 imxdma->hw_chaining = 0;
359
360 if (hw_chaining) {
361 imxdma->hw_chaining = 1;
362 if (!imx_dma_hw_chain(imxdma))
363 return -EINVAL;
364 }
365
366 if (dmareq)
367 dreq = CCR_REN;
368
369 imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
370 imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
371
372 imx_dmav1_writel(dmareq, DMA_RSSR(channel));
373
374 return 0;
375}
376EXPORT_SYMBOL(imx_dma_config_channel);
377
378void imx_dma_config_burstlen(int channel, unsigned int burstlen)
379{
380 imx_dmav1_writel(burstlen, DMA_BLR(channel));
381}
382EXPORT_SYMBOL(imx_dma_config_burstlen);
383
384/**
385 * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
386 * handlers
387 * @channel: i.MX DMA channel number
388 * @irq_handler: the pointer to the function called if the transfer
389 * ends successfully
390 * @err_handler: the pointer to the function called if the premature
391 * end caused by error occurs
392 * @data: user specified value to be passed to the handlers
393 */
394int
395imx_dma_setup_handlers(int channel,
396 void (*irq_handler) (int, void *),
397 void (*err_handler) (int, void *, int),
398 void *data)
399{
400 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
401 unsigned long flags;
402
403 if (!imxdma->name) {
404 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
405 __func__, channel);
406 return -ENODEV;
407 }
408
409 local_irq_save(flags);
410 imx_dmav1_writel(1 << channel, DMA_DISR);
411 imxdma->irq_handler = irq_handler;
412 imxdma->err_handler = err_handler;
413 imxdma->data = data;
414 local_irq_restore(flags);
415 return 0;
416}
417EXPORT_SYMBOL(imx_dma_setup_handlers);
418
419/**
420 * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
421 * handlers
422 * @channel: i.MX DMA channel number
423 * @prog_handler: the pointer to the function called if the transfer progresses
424 */
425int
426imx_dma_setup_progression_handler(int channel,
427 void (*prog_handler) (int, void*, struct scatterlist*))
428{
429 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
430 unsigned long flags;
431
432 if (!imxdma->name) {
433 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
434 __func__, channel);
435 return -ENODEV;
436 }
437
438 local_irq_save(flags);
439 imxdma->prog_handler = prog_handler;
440 local_irq_restore(flags);
441 return 0;
442}
443EXPORT_SYMBOL(imx_dma_setup_progression_handler);
444
445/**
446 * imx_dma_enable - function to start i.MX DMA channel operation
447 * @channel: i.MX DMA channel number
448 *
449 * The channel has to be allocated by driver through imx_dma_request()
450 * or imx_dma_request_by_prio() function.
451 * The transfer parameters has to be set to the channel registers through
452 * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
453 * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
454 * be set prior this function call by the channel user.
455 */
456void imx_dma_enable(int channel)
457{
458 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
459 unsigned long flags;
460
461 pr_debug("imxdma%d: imx_dma_enable\n", channel);
462
463 if (!imxdma->name) {
464 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
465 __func__, channel);
466 return;
467 }
468
469 if (imxdma->in_use)
470 return;
471
472 local_irq_save(flags);
473
474 imx_dmav1_writel(1 << channel, DMA_DISR);
475 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
476 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
477 CCR_ACRPT, DMA_CCR(channel));
478
479 if ((cpu_is_mx21() || cpu_is_mx27()) &&
480 imxdma->sg && imx_dma_hw_chain(imxdma)) {
481 imxdma->sg = sg_next(imxdma->sg);
482 if (imxdma->sg) {
483 u32 tmp;
484 imx_dma_sg_next(channel, imxdma->sg);
485 tmp = imx_dmav1_readl(DMA_CCR(channel));
486 imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
487 DMA_CCR(channel));
488 }
489 }
490 imxdma->in_use = 1;
491
492 local_irq_restore(flags);
493}
494EXPORT_SYMBOL(imx_dma_enable);
495
496/**
497 * imx_dma_disable - stop, finish i.MX DMA channel operatin
498 * @channel: i.MX DMA channel number
499 */
500void imx_dma_disable(int channel)
501{
502 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
503 unsigned long flags;
504
505 pr_debug("imxdma%d: imx_dma_disable\n", channel);
506
507 if (imx_dma_hw_chain(imxdma))
508 del_timer(&imxdma->watchdog);
509
510 local_irq_save(flags);
511 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
512 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
513 DMA_CCR(channel));
514 imx_dmav1_writel(1 << channel, DMA_DISR);
515 imxdma->in_use = 0;
516 local_irq_restore(flags);
517}
518EXPORT_SYMBOL(imx_dma_disable);
519
520static void imx_dma_watchdog(unsigned long chno)
521{
522 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
523
524 imx_dmav1_writel(0, DMA_CCR(chno));
525 imxdma->in_use = 0;
526 imxdma->sg = NULL;
527
528 if (imxdma->err_handler)
529 imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
530}
531
532static irqreturn_t dma_err_handler(int irq, void *dev_id)
533{
534 int i, disr;
535 struct imx_dma_channel *imxdma;
536 unsigned int err_mask;
537 int errcode;
538
539 disr = imx_dmav1_readl(DMA_DISR);
540
541 err_mask = imx_dmav1_readl(DMA_DBTOSR) |
542 imx_dmav1_readl(DMA_DRTOSR) |
543 imx_dmav1_readl(DMA_DSESR) |
544 imx_dmav1_readl(DMA_DBOSR);
545
546 if (!err_mask)
547 return IRQ_HANDLED;
548
549 imx_dmav1_writel(disr & err_mask, DMA_DISR);
550
551 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
552 if (!(err_mask & (1 << i)))
553 continue;
554 imxdma = &imx_dma_channels[i];
555 errcode = 0;
556
557 if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
558 imx_dmav1_writel(1 << i, DMA_DBTOSR);
559 errcode |= IMX_DMA_ERR_BURST;
560 }
561 if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
562 imx_dmav1_writel(1 << i, DMA_DRTOSR);
563 errcode |= IMX_DMA_ERR_REQUEST;
564 }
565 if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
566 imx_dmav1_writel(1 << i, DMA_DSESR);
567 errcode |= IMX_DMA_ERR_TRANSFER;
568 }
569 if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
570 imx_dmav1_writel(1 << i, DMA_DBOSR);
571 errcode |= IMX_DMA_ERR_BUFFER;
572 }
573 if (imxdma->name && imxdma->err_handler) {
574 imxdma->err_handler(i, imxdma->data, errcode);
575 continue;
576 }
577
578 imx_dma_channels[i].sg = NULL;
579
580 printk(KERN_WARNING
581 "DMA timeout on channel %d (%s) -%s%s%s%s\n",
582 i, imxdma->name,
583 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
584 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
585 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
586 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
587 }
588 return IRQ_HANDLED;
589}
590
591static void dma_irq_handle_channel(int chno)
592{
593 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
594
595 if (!imxdma->name) {
596 /*
597 * IRQ for an unregistered DMA channel:
598 * let's clear the interrupts and disable it.
599 */
600 printk(KERN_WARNING
601 "spurious IRQ for DMA channel %d\n", chno);
602 return;
603 }
604
605 if (imxdma->sg) {
606 u32 tmp;
607 struct scatterlist *current_sg = imxdma->sg;
608 imxdma->sg = sg_next(imxdma->sg);
609
610 if (imxdma->sg) {
611 imx_dma_sg_next(chno, imxdma->sg);
612
613 tmp = imx_dmav1_readl(DMA_CCR(chno));
614
615 if (imx_dma_hw_chain(imxdma)) {
616 /* FIXME: The timeout should probably be
617 * configurable
618 */
619 mod_timer(&imxdma->watchdog,
620 jiffies + msecs_to_jiffies(500));
621
622 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
623 imx_dmav1_writel(tmp, DMA_CCR(chno));
624 } else {
625 imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
626 tmp |= CCR_CEN;
627 }
628
629 imx_dmav1_writel(tmp, DMA_CCR(chno));
630
631 if (imxdma->prog_handler)
632 imxdma->prog_handler(chno, imxdma->data,
633 current_sg);
634
635 return;
636 }
637
638 if (imx_dma_hw_chain(imxdma)) {
639 del_timer(&imxdma->watchdog);
640 return;
641 }
642 }
643
644 imx_dmav1_writel(0, DMA_CCR(chno));
645 imxdma->in_use = 0;
646 if (imxdma->irq_handler)
647 imxdma->irq_handler(chno, imxdma->data);
648}
649
650static irqreturn_t dma_irq_handler(int irq, void *dev_id)
651{
652 int i, disr;
653
654 if (cpu_is_mx21() || cpu_is_mx27())
655 dma_err_handler(irq, dev_id);
656
657 disr = imx_dmav1_readl(DMA_DISR);
658
659 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
660 disr);
661
662 imx_dmav1_writel(disr, DMA_DISR);
663 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
664 if (disr & (1 << i))
665 dma_irq_handle_channel(i);
666 }
667
668 return IRQ_HANDLED;
669}
670
671/**
672 * imx_dma_request - request/allocate specified channel number
673 * @channel: i.MX DMA channel number
674 * @name: the driver/caller own non-%NULL identification
675 */
676int imx_dma_request(int channel, const char *name)
677{
678 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
679 unsigned long flags;
680 int ret = 0;
681
682 /* basic sanity checks */
683 if (!name)
684 return -EINVAL;
685
686 if (channel >= IMX_DMA_CHANNELS) {
687 printk(KERN_CRIT "%s: called for non-existed channel %d\n",
688 __func__, channel);
689 return -EINVAL;
690 }
691
692 local_irq_save(flags);
693 if (imxdma->name) {
694 local_irq_restore(flags);
695 return -EBUSY;
696 }
697 memset(imxdma, 0, sizeof(*imxdma));
698 imxdma->name = name;
699 local_irq_restore(flags); /* request_irq() can block */
700
701 if (cpu_is_mx21() || cpu_is_mx27()) {
702 ret = request_irq(MX2x_INT_DMACH0 + channel,
703 dma_irq_handler, 0, "DMA", NULL);
704 if (ret) {
705 imxdma->name = NULL;
706 pr_crit("Can't register IRQ %d for DMA channel %d\n",
707 MX2x_INT_DMACH0 + channel, channel);
708 return ret;
709 }
710 init_timer(&imxdma->watchdog);
711 imxdma->watchdog.function = &imx_dma_watchdog;
712 imxdma->watchdog.data = channel;
713 }
714
715 return ret;
716}
717EXPORT_SYMBOL(imx_dma_request);
718
719/**
720 * imx_dma_free - release previously acquired channel
721 * @channel: i.MX DMA channel number
722 */
723void imx_dma_free(int channel)
724{
725 unsigned long flags;
726 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
727
728 if (!imxdma->name) {
729 printk(KERN_CRIT
730 "%s: trying to free free channel %d\n",
731 __func__, channel);
732 return;
733 }
734
735 local_irq_save(flags);
736 /* Disable interrupts */
737 imx_dma_disable(channel);
738 imxdma->name = NULL;
739
740 if (cpu_is_mx21() || cpu_is_mx27())
741 free_irq(MX2x_INT_DMACH0 + channel, NULL);
742
743 local_irq_restore(flags);
744}
745EXPORT_SYMBOL(imx_dma_free);
746
747/**
748 * imx_dma_request_by_prio - find and request some of free channels best
749 * suiting requested priority
750 * @channel: i.MX DMA channel number
751 * @name: the driver/caller own non-%NULL identification
752 *
753 * This function tries to find a free channel in the specified priority group
754 * if the priority cannot be achieved it tries to look for free channel
755 * in the higher and then even lower priority groups.
756 *
757 * Return value: If there is no free channel to allocate, -%ENODEV is returned.
758 * On successful allocation channel is returned.
759 */
760int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
761{
762 int i;
763 int best;
764
765 switch (prio) {
766 case (DMA_PRIO_HIGH):
767 best = 8;
768 break;
769 case (DMA_PRIO_MEDIUM):
770 best = 4;
771 break;
772 case (DMA_PRIO_LOW):
773 default:
774 best = 0;
775 break;
776 }
777
778 for (i = best; i < IMX_DMA_CHANNELS; i++)
779 if (!imx_dma_request(i, name))
780 return i;
781
782 for (i = best - 1; i >= 0; i--)
783 if (!imx_dma_request(i, name))
784 return i;
785
786 printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
787
788 return -ENODEV;
789}
790EXPORT_SYMBOL(imx_dma_request_by_prio);
791
792static int __init imx_dma_init(void)
793{
794 int ret = 0;
795 int i;
796
797 if (cpu_is_mx1())
798 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
799 else if (cpu_is_mx21())
800 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
801 else if (cpu_is_mx27())
802 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
803 else
804 return 0;
805
806 dma_clk = clk_get(NULL, "dma");
807 if (IS_ERR(dma_clk))
808 return PTR_ERR(dma_clk);
809 clk_enable(dma_clk);
810
811 /* reset DMA module */
812 imx_dmav1_writel(DCR_DRST, DMA_DCR);
813
814 if (cpu_is_mx1()) {
815 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
816 if (ret) {
817 pr_crit("Wow! Can't register IRQ for DMA\n");
818 return ret;
819 }
820
821 ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
822 if (ret) {
823 pr_crit("Wow! Can't register ERRIRQ for DMA\n");
824 free_irq(MX1_DMA_INT, NULL);
825 return ret;
826 }
827 }
828
829 /* enable DMA module */
830 imx_dmav1_writel(DCR_DEN, DMA_DCR);
831
832 /* clear all interrupts */
833 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
834
835 /* disable interrupts */
836 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
837
838 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
839 imx_dma_channels[i].sg = NULL;
840 imx_dma_channels[i].dma_num = i;
841 }
842
843 return ret;
844}
845
846arch_initcall(imx_dma_init);
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
new file mode 100644
index 000000000000..861ceb8232d6
--- /dev/null
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -0,0 +1,89 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/irq.h>
13#include <linux/irqdomain.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h>
16#include <asm/mach/arch.h>
17#include <asm/mach/time.h>
18#include <mach/common.h>
19#include <mach/mx27.h>
20
21static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
22 OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
23 OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
24 OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL),
25 OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL),
26 OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
27 OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
28 OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL),
29 OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
30 OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
31 OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
32 { /* sentinel */ }
33};
34
35static int __init imx27_avic_add_irq_domain(struct device_node *np,
36 struct device_node *interrupt_parent)
37{
38 irq_domain_add_simple(np, 0);
39 return 0;
40}
41
42static int __init imx27_gpio_add_irq_domain(struct device_node *np,
43 struct device_node *interrupt_parent)
44{
45 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
46
47 irq_domain_add_simple(np, gpio_irq_base);
48
49 return 0;
50}
51
52static const struct of_device_id imx27_irq_match[] __initconst = {
53 { .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, },
54 { .compatible = "fsl,imx27-gpio", .data = imx27_gpio_add_irq_domain, },
55 { /* sentinel */ }
56};
57
58static void __init imx27_dt_init(void)
59{
60 of_irq_init(imx27_irq_match);
61
62 of_platform_populate(NULL, of_default_bus_match_table,
63 imx27_auxdata_lookup, NULL);
64}
65
66static void __init imx27_timer_init(void)
67{
68 mx27_clocks_init_dt();
69}
70
71static struct sys_timer imx27_timer = {
72 .init = imx27_timer_init,
73};
74
75static const char *imx27_dt_board_compat[] __initdata = {
76 "fsl,imx27",
77 NULL
78};
79
80DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
81 .map_io = mx27_map_io,
82 .init_early = imx27_init_early,
83 .init_irq = mx27_init_irq,
84 .handle_irq = imx27_handle_irq,
85 .timer = &imx27_timer,
86 .init_machine = imx27_dt_init,
87 .dt_compat = imx27_dt_board_compat,
88 .restart = mxc_restart,
89MACHINE_END
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 1e03ef42faa0..5cca573964f0 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -104,6 +104,7 @@ static struct sys_timer imx51_timer = {
104 104
105static const char *imx51_dt_board_compat[] __initdata = { 105static const char *imx51_dt_board_compat[] __initdata = {
106 "fsl,imx51-babbage", 106 "fsl,imx51-babbage",
107 "fsl,imx51",
107 NULL 108 NULL
108}; 109};
109 110
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index fd5be0f20fbb..4172279b3900 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -114,6 +114,7 @@ static const char *imx53_dt_board_compat[] __initdata = {
114 "fsl,imx53-evk", 114 "fsl,imx53-evk",
115 "fsl,imx53-qsb", 115 "fsl,imx53-qsb",
116 "fsl,imx53-smd", 116 "fsl,imx53-smd",
117 "fsl,imx53",
117 NULL 118 NULL
118}; 119};
119 120
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h
deleted file mode 100644
index ac6fd713828a..000000000000
--- a/arch/arm/mach-imx/include/mach/dma-v1.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * linux/arch/arm/mach-imx/include/mach/dma-v1.h
3 *
4 * i.MX DMA registration and IRQ dispatching
5 *
6 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
7 * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
8 * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#ifndef __MACH_DMA_V1_H__
26#define __MACH_DMA_V1_H__
27
28#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
29
30#include <mach/dma.h>
31
32#define IMX_DMA_CHANNELS 16
33
34#define DMA_MODE_READ 0
35#define DMA_MODE_WRITE 1
36#define DMA_MODE_MASK 1
37
38#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
39
40/* DMA Interrupt Mask Register */
41#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
42
43/* Channel Control Register */
44#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
45
46#define IMX_DMA_MEMSIZE_32 (0 << 4)
47#define IMX_DMA_MEMSIZE_8 (1 << 4)
48#define IMX_DMA_MEMSIZE_16 (2 << 4)
49#define IMX_DMA_TYPE_LINEAR (0 << 10)
50#define IMX_DMA_TYPE_2D (1 << 10)
51#define IMX_DMA_TYPE_FIFO (2 << 10)
52
53#define IMX_DMA_ERR_BURST (1 << 0)
54#define IMX_DMA_ERR_REQUEST (1 << 1)
55#define IMX_DMA_ERR_TRANSFER (1 << 2)
56#define IMX_DMA_ERR_BUFFER (1 << 3)
57#define IMX_DMA_ERR_TIMEOUT (1 << 4)
58
59int
60imx_dma_config_channel(int channel, unsigned int config_port,
61 unsigned int config_mem, unsigned int dmareq, int hw_chaining);
62
63void
64imx_dma_config_burstlen(int channel, unsigned int burstlen);
65
66int
67imx_dma_setup_single(int channel, dma_addr_t dma_address,
68 unsigned int dma_length, unsigned int dev_addr,
69 unsigned int dmamode);
70
71
72/*
73 * Use this flag as the dma_length argument to imx_dma_setup_sg()
74 * to create an endless running dma loop. The end of the scatterlist
75 * must be linked to the beginning for this to work.
76 */
77#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
78
79int
80imx_dma_setup_sg(int channel, struct scatterlist *sg,
81 unsigned int sgcount, unsigned int dma_length,
82 unsigned int dev_addr, unsigned int dmamode);
83
84int
85imx_dma_setup_handlers(int channel,
86 void (*irq_handler) (int, void *),
87 void (*err_handler) (int, void *, int), void *data);
88
89int
90imx_dma_setup_progression_handler(int channel,
91 void (*prog_handler) (int, void*, struct scatterlist*));
92
93void imx_dma_enable(int channel);
94
95void imx_dma_disable(int channel);
96
97int imx_dma_request(int channel, const char *name);
98
99void imx_dma_free(int channel);
100
101int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
102
103#endif /* __MACH_DMA_V1_H__ */
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
index d4ab6f29a766..0213f8dcee81 100644
--- a/arch/arm/mach-imx/lluart.c
+++ b/arch/arm/mach-imx/lluart.c
@@ -17,7 +17,7 @@
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18 18
19static struct map_desc imx_lluart_desc = { 19static struct map_desc imx_lluart_desc = {
20#ifdef CONFIG_DEBUG_IMX6Q_UART 20#ifdef CONFIG_DEBUG_IMX6Q_UART4
21 .virtual = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR), 21 .virtual = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
22 .pfn = __phys_to_pfn(MX6Q_UART4_BASE_ADDR), 22 .pfn = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
23 .length = MX6Q_UART4_SIZE, 23 .length = MX6Q_UART4_SIZE,
diff --git a/arch/arm/mach-imx/localtimer.c b/arch/arm/mach-imx/localtimer.c
deleted file mode 100644
index 3a163515d41f..000000000000
--- a/arch/arm/mach-imx/localtimer.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/clockchips.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <asm/smp_twd.h>
18
19/*
20 * Setup the local clock events for a CPU.
21 */
22int __cpuinit local_timer_setup(struct clock_event_device *evt)
23{
24 struct device_node *np;
25
26 np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
27 if (!twd_base) {
28 twd_base = of_iomap(np, 0);
29 WARN_ON(!twd_base);
30 }
31 evt->irq = irq_of_parse_and_map(np, 0);
32 twd_timer_setup(evt);
33
34 return 0;
35}
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index e4f426a09899..27bc27e6ea41 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -51,7 +51,7 @@
51#include <mach/ulpi.h> 51#include <mach/ulpi.h>
52 52
53#include "devices-imx31.h" 53#include "devices-imx31.h"
54#include "crmregs-imx31.h" 54#include "crmregs-imx3.h"
55 55
56static int armadillo5x0_pins[] = { 56static int armadillo5x0_pins[] = {
57 /* UART1 */ 57 /* UART1 */
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 428459fbca4b..f7b074f496f0 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -30,6 +30,10 @@
30#include <linux/input.h> 30#include <linux/input.h>
31#include <linux/gpio.h> 31#include <linux/gpio.h>
32#include <linux/delay.h> 32#include <linux/delay.h>
33#include <linux/dma-mapping.h>
34#include <linux/leds.h>
35#include <linux/memblock.h>
36#include <media/soc_camera.h>
33#include <sound/tlv320aic32x4.h> 37#include <sound/tlv320aic32x4.h>
34#include <asm/mach-types.h> 38#include <asm/mach-types.h>
35#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
@@ -39,6 +43,8 @@
39 43
40#include "devices-imx27.h" 44#include "devices-imx27.h"
41 45
46#define TVP5150_RSTN (GPIO_PORTC + 18)
47#define TVP5150_PWDN (GPIO_PORTC + 19)
42#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) 48#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
43#define SDHC1_IRQ IRQ_GPIOB(25) 49#define SDHC1_IRQ IRQ_GPIOB(25)
44 50
@@ -100,8 +106,99 @@ static const int visstrim_m10_pins[] __initconst = {
100 PE1_PF_USBOTG_STP, 106 PE1_PF_USBOTG_STP,
101 PB23_PF_USB_PWR, 107 PB23_PF_USB_PWR,
102 PB24_PF_USB_OC, 108 PB24_PF_USB_OC,
109 /* CSI */
110 PB10_PF_CSI_D0,
111 PB11_PF_CSI_D1,
112 PB12_PF_CSI_D2,
113 PB13_PF_CSI_D3,
114 PB14_PF_CSI_D4,
115 PB15_PF_CSI_MCLK,
116 PB16_PF_CSI_PIXCLK,
117 PB17_PF_CSI_D5,
118 PB18_PF_CSI_D6,
119 PB19_PF_CSI_D7,
120 PB20_PF_CSI_VSYNC,
121 PB21_PF_CSI_HSYNC,
103}; 122};
104 123
124/* Camera */
125static int visstrim_camera_power(struct device *dev, int on)
126{
127 gpio_set_value(TVP5150_PWDN, on);
128
129 return 0;
130};
131
132static int visstrim_camera_reset(struct device *dev)
133{
134 gpio_set_value(TVP5150_RSTN, 0);
135 ndelay(500);
136 gpio_set_value(TVP5150_RSTN, 1);
137
138 return 0;
139};
140
141static struct i2c_board_info visstrim_i2c_camera = {
142 I2C_BOARD_INFO("tvp5150", 0x5d),
143};
144
145static struct soc_camera_link iclink_tvp5150 = {
146 .bus_id = 0,
147 .board_info = &visstrim_i2c_camera,
148 .i2c_adapter_id = 0,
149 .power = visstrim_camera_power,
150 .reset = visstrim_camera_reset,
151};
152
153static struct mx2_camera_platform_data visstrim_camera = {
154 .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE |
155 MX2_CAMERA_SWAP16 | MX2_CAMERA_PCLK_SAMPLE_RISING,
156 .clk = 100000,
157};
158
159static phys_addr_t mx2_camera_base __initdata;
160#define MX2_CAMERA_BUF_SIZE SZ_8M
161
162static void __init visstrim_camera_init(void)
163{
164 struct platform_device *pdev;
165 int dma;
166
167 /* Initialize tvp5150 gpios */
168 mxc_gpio_mode(TVP5150_RSTN | GPIO_GPIO | GPIO_OUT);
169 mxc_gpio_mode(TVP5150_PWDN | GPIO_GPIO | GPIO_OUT);
170 gpio_set_value(TVP5150_RSTN, 1);
171 gpio_set_value(TVP5150_PWDN, 0);
172 ndelay(1);
173
174 gpio_set_value(TVP5150_PWDN, 1);
175 ndelay(1);
176 gpio_set_value(TVP5150_RSTN, 0);
177 ndelay(500);
178 gpio_set_value(TVP5150_RSTN, 1);
179 ndelay(200000);
180
181 pdev = imx27_add_mx2_camera(&visstrim_camera);
182 if (IS_ERR(pdev))
183 return;
184
185 dma = dma_declare_coherent_memory(&pdev->dev,
186 mx2_camera_base, mx2_camera_base,
187 MX2_CAMERA_BUF_SIZE,
188 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
189 if (!(dma & DMA_MEMORY_MAP))
190 return;
191}
192
193static void __init visstrim_reserve(void)
194{
195 /* reserve 4 MiB for mx2-camera */
196 mx2_camera_base = memblock_alloc(MX2_CAMERA_BUF_SIZE,
197 MX2_CAMERA_BUF_SIZE);
198 memblock_free(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
199 memblock_remove(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
200}
201
105/* GPIOs used as events for applications */ 202/* GPIOs used as events for applications */
106static struct gpio_keys_button visstrim_gpio_keys[] = { 203static struct gpio_keys_button visstrim_gpio_keys[] = {
107 { 204 {
@@ -136,6 +233,35 @@ static const struct gpio_keys_platform_data
136 .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), 233 .nbuttons = ARRAY_SIZE(visstrim_gpio_keys),
137}; 234};
138 235
236/* led */
237static const struct gpio_led visstrim_m10_leds[] __initconst = {
238 {
239 .name = "visstrim:ld0",
240 .default_trigger = "nand-disk",
241 .gpio = (GPIO_PORTC + 29),
242 },
243 {
244 .name = "visstrim:ld1",
245 .default_trigger = "nand-disk",
246 .gpio = (GPIO_PORTC + 24),
247 },
248 {
249 .name = "visstrim:ld2",
250 .default_trigger = "nand-disk",
251 .gpio = (GPIO_PORTC + 28),
252 },
253 {
254 .name = "visstrim:ld3",
255 .default_trigger = "nand-disk",
256 .gpio = (GPIO_PORTC + 25),
257 },
258};
259
260static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = {
261 .leds = visstrim_m10_leds,
262 .num_leds = ARRAY_SIZE(visstrim_m10_leds),
263};
264
139/* Visstrim_SM10 has a microSD slot connected to sdhc1 */ 265/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
140static int visstrim_m10_sdhc1_init(struct device *dev, 266static int visstrim_m10_sdhc1_init(struct device *dev,
141 irq_handler_t detect_irq, void *data) 267 irq_handler_t detect_irq, void *data)
@@ -216,6 +342,9 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
216 { 342 {
217 I2C_BOARD_INFO("tlv320aic32x4", 0x18), 343 I2C_BOARD_INFO("tlv320aic32x4", 0x18),
218 .platform_data = &visstrim_m10_aic32x4_pdata, 344 .platform_data = &visstrim_m10_aic32x4_pdata,
345 },
346 {
347 I2C_BOARD_INFO("m41t00", 0x68),
219 } 348 }
220}; 349};
221 350
@@ -254,16 +383,21 @@ static void __init visstrim_m10_board_init(void)
254 imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata); 383 imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
255 imx27_add_imx_uart0(&uart_pdata); 384 imx27_add_imx_uart0(&uart_pdata);
256 385
257 i2c_register_board_info(0, visstrim_m10_i2c_devices,
258 ARRAY_SIZE(visstrim_m10_i2c_devices));
259 imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); 386 imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
260 imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); 387 imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
388 i2c_register_board_info(0, visstrim_m10_i2c_devices,
389 ARRAY_SIZE(visstrim_m10_i2c_devices));
390
261 imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); 391 imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
262 imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); 392 imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
263 imx27_add_fec(NULL); 393 imx27_add_fec(NULL);
264 imx_add_gpio_keys(&visstrim_gpio_keys_platform_data); 394 imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
265 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 395 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
266 imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0); 396 imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0);
397 platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
398 &iclink_tvp5150, sizeof(iclink_tvp5150));
399 gpio_led_register_device(0, &visstrim_m10_led_data);
400 visstrim_camera_init();
267} 401}
268 402
269static void __init visstrim_m10_timer_init(void) 403static void __init visstrim_m10_timer_init(void)
@@ -277,6 +411,7 @@ static struct sys_timer visstrim_m10_timer = {
277 411
278MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") 412MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
279 .atag_offset = 0x100, 413 .atag_offset = 0x100,
414 .reserve = visstrim_reserve,
280 .map_io = mx27_map_io, 415 .map_io = mx27_map_io,
281 .init_early = imx27_init_early, 416 .init_early = imx27_init_early,
282 .init_irq = mx27_init_irq, 417 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 6075d4d62dd6..da6c1d9af768 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -21,10 +21,12 @@
21#include <linux/of_platform.h> 21#include <linux/of_platform.h>
22#include <linux/phy.h> 22#include <linux/phy.h>
23#include <linux/micrel_phy.h> 23#include <linux/micrel_phy.h>
24#include <asm/smp_twd.h>
24#include <asm/hardware/cache-l2x0.h> 25#include <asm/hardware/cache-l2x0.h>
25#include <asm/hardware/gic.h> 26#include <asm/hardware/gic.h>
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
27#include <asm/mach/time.h> 28#include <asm/mach/time.h>
29#include <asm/system_misc.h>
28#include <mach/common.h> 30#include <mach/common.h>
29#include <mach/hardware.h> 31#include <mach/hardware.h>
30 32
@@ -120,6 +122,7 @@ static void __init imx6q_init_irq(void)
120static void __init imx6q_timer_init(void) 122static void __init imx6q_timer_init(void)
121{ 123{
122 mx6q_clocks_init(); 124 mx6q_clocks_init();
125 twd_local_timer_of_register();
123} 126}
124 127
125static struct sys_timer imx6q_timer = { 128static struct sys_timer imx6q_timer = {
@@ -129,6 +132,7 @@ static struct sys_timer imx6q_timer = {
129static const char *imx6q_dt_compat[] __initdata = { 132static const char *imx6q_dt_compat[] __initdata = {
130 "fsl,imx6q-arm2", 133 "fsl,imx6q-arm2",
131 "fsl,imx6q-sabrelite", 134 "fsl,imx6q-sabrelite",
135 "fsl,imx6q",
132 NULL, 136 NULL,
133}; 137};
134 138
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 8d9f95514b1f..e432d4acee1f 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -37,8 +37,8 @@
37#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ 37#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
38 (MX21ADS_MMIO_BASE_ADDR + (offset)) 38 (MX21ADS_MMIO_BASE_ADDR + (offset))
39 39
40#define MX21ADS_CS8900A_MMIO_SIZE 0x200000
40#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11) 41#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
41#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
42#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) 42#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
43#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) 43#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
44#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) 44#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
@@ -159,6 +159,18 @@ static struct platform_device mx21ads_nor_mtd_device = {
159 .resource = &mx21ads_flash_resource, 159 .resource = &mx21ads_flash_resource,
160}; 160};
161 161
162static const struct resource mx21ads_cs8900_resources[] __initconst = {
163 DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
164 DEFINE_RES_IRQ(MX21ADS_CS8900A_IRQ),
165};
166
167static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
168 .name = "cs89x0",
169 .id = 0,
170 .res = mx21ads_cs8900_resources,
171 .num_res = ARRAY_SIZE(mx21ads_cs8900_resources),
172};
173
162static const struct imxuart_platform_data uart_pdata_rts __initconst = { 174static const struct imxuart_platform_data uart_pdata_rts __initconst = {
163 .flags = IMXUART_HAVE_RTSCTS, 175 .flags = IMXUART_HAVE_RTSCTS,
164}; 176};
@@ -292,6 +304,8 @@ static void __init mx21ads_board_init(void)
292 imx21_add_mxc_nand(&mx21ads_nand_board_info); 304 imx21_add_mxc_nand(&mx21ads_nand_board_info);
293 305
294 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 306 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
307 platform_device_register_full(
308 (struct platform_device_info *)&mx21ads_cs8900_devinfo);
295} 309}
296 310
297static void __init mx21ads_timer_init(void) 311static void __init mx21ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 18f35816706a..c6d385c52257 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -31,6 +31,8 @@
31#include <linux/regulator/machine.h> 31#include <linux/regulator/machine.h>
32#include <linux/spi/l4f00242t03.h> 32#include <linux/spi/l4f00242t03.h>
33 33
34#include <media/soc_camera.h>
35
34#include <asm/mach-types.h> 36#include <asm/mach-types.h>
35#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
36#include <asm/mach/time.h> 38#include <asm/mach/time.h>
@@ -52,6 +54,8 @@
52#define SD1_CD IMX_GPIO_NR(2, 26) 54#define SD1_CD IMX_GPIO_NR(2, 26)
53#define LCD_RESET IMX_GPIO_NR(1, 3) 55#define LCD_RESET IMX_GPIO_NR(1, 3)
54#define LCD_ENABLE IMX_GPIO_NR(1, 31) 56#define LCD_ENABLE IMX_GPIO_NR(1, 31)
57#define CSI_PWRDWN IMX_GPIO_NR(4, 19)
58#define CSI_RESET IMX_GPIO_NR(3, 6)
55 59
56static const int mx27pdk_pins[] __initconst = { 60static const int mx27pdk_pins[] __initconst = {
57 /* UART1 */ 61 /* UART1 */
@@ -141,6 +145,26 @@ static const int mx27pdk_pins[] __initconst = {
141 PA30_PF_CONTRAST, 145 PA30_PF_CONTRAST,
142 LCD_ENABLE | GPIO_GPIO | GPIO_OUT, 146 LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
143 LCD_RESET | GPIO_GPIO | GPIO_OUT, 147 LCD_RESET | GPIO_GPIO | GPIO_OUT,
148 /* CSI */
149 PB10_PF_CSI_D0,
150 PB11_PF_CSI_D1,
151 PB12_PF_CSI_D2,
152 PB13_PF_CSI_D3,
153 PB14_PF_CSI_D4,
154 PB15_PF_CSI_MCLK,
155 PB16_PF_CSI_PIXCLK,
156 PB17_PF_CSI_D5,
157 PB18_PF_CSI_D6,
158 PB19_PF_CSI_D7,
159 PB20_PF_CSI_VSYNC,
160 PB21_PF_CSI_HSYNC,
161 CSI_PWRDWN | GPIO_GPIO | GPIO_OUT,
162 CSI_RESET | GPIO_GPIO | GPIO_OUT,
163};
164
165static struct gpio mx27_3ds_camera_gpios[] = {
166 { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" },
167 { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" },
144}; 168};
145 169
146static const struct imxuart_platform_data uart_pdata __initconst = { 170static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -242,6 +266,7 @@ static struct regulator_init_data gpo_init = {
242 266
243static struct regulator_consumer_supply vmmc1_consumers[] = { 267static struct regulator_consumer_supply vmmc1_consumers[] = {
244 REGULATOR_SUPPLY("vcore", "spi0.0"), 268 REGULATOR_SUPPLY("vcore", "spi0.0"),
269 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
245}; 270};
246 271
247static struct regulator_init_data vmmc1_init = { 272static struct regulator_init_data vmmc1_init = {
@@ -270,6 +295,22 @@ static struct regulator_init_data vgen_init = {
270 .consumer_supplies = vgen_consumers, 295 .consumer_supplies = vgen_consumers,
271}; 296};
272 297
298static struct regulator_consumer_supply vvib_consumers[] = {
299 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
300};
301
302static struct regulator_init_data vvib_init = {
303 .constraints = {
304 .min_uV = 1300000,
305 .max_uV = 1300000,
306 .apply_uV = 1,
307 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
308 REGULATOR_CHANGE_STATUS,
309 },
310 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
311 .consumer_supplies = vvib_consumers,
312};
313
273static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = { 314static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
274 { 315 {
275 .id = MC13783_REG_VMMC1, 316 .id = MC13783_REG_VMMC1,
@@ -283,6 +324,9 @@ static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
283 }, { 324 }, {
284 .id = MC13783_REG_GPO3, /* Turn on 3.3V */ 325 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
285 .init_data = &gpo_init, 326 .init_data = &gpo_init,
327 }, {
328 .id = MC13783_REG_VVIB, /* Power OV2640 */
329 .init_data = &vvib_init,
286 }, 330 },
287}; 331};
288 332
@@ -311,6 +355,51 @@ static const struct spi_imx_master spi2_pdata __initconst = {
311 .num_chipselect = ARRAY_SIZE(spi2_chipselect), 355 .num_chipselect = ARRAY_SIZE(spi2_chipselect),
312}; 356};
313 357
358static int mx27_3ds_camera_power(struct device *dev, int on)
359{
360 /* enable or disable the camera */
361 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
362 gpio_set_value(CSI_PWRDWN, on ? 0 : 1);
363
364 if (!on)
365 goto out;
366
367 /* If enabled, give a reset impulse */
368 gpio_set_value(CSI_RESET, 0);
369 msleep(20);
370 gpio_set_value(CSI_RESET, 1);
371 msleep(100);
372
373out:
374 return 0;
375}
376
377static struct i2c_board_info mx27_3ds_i2c_camera = {
378 I2C_BOARD_INFO("ov2640", 0x30),
379};
380
381static struct regulator_bulk_data mx27_3ds_camera_regs[] = {
382 { .supply = "cmos_vcore" },
383 { .supply = "cmos_2v8" },
384};
385
386static struct soc_camera_link iclink_ov2640 = {
387 .bus_id = 0,
388 .board_info = &mx27_3ds_i2c_camera,
389 .i2c_adapter_id = 0,
390 .power = mx27_3ds_camera_power,
391 .regulators = mx27_3ds_camera_regs,
392 .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs),
393};
394
395static struct platform_device mx27_3ds_ov2640 = {
396 .name = "soc-camera-pdrv",
397 .id = 0,
398 .dev = {
399 .platform_data = &iclink_ov2640,
400 },
401};
402
314static struct imx_fb_videomode mx27_3ds_modes[] = { 403static struct imx_fb_videomode mx27_3ds_modes[] = {
315 { /* 480x640 @ 60 Hz */ 404 { /* 480x640 @ 60 Hz */
316 .mode = { 405 .mode = {
@@ -367,12 +456,21 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
367 }, 456 },
368}; 457};
369 458
459static struct platform_device *devices[] __initdata = {
460 &mx27_3ds_ov2640,
461};
462
463static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = {
464 .clk = 26000000,
465};
466
370static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = { 467static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
371 .bitrate = 100000, 468 .bitrate = 100000,
372}; 469};
373 470
374static void __init mx27pdk_init(void) 471static void __init mx27pdk_init(void)
375{ 472{
473 int ret;
376 imx27_soc_init(); 474 imx27_soc_init();
377 475
378 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), 476 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
@@ -404,7 +502,17 @@ static void __init mx27pdk_init(void)
404 if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) 502 if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
405 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); 503 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
406 imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); 504 imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
505 platform_add_devices(devices, ARRAY_SIZE(devices));
407 imx27_add_imx_fb(&mx27_3ds_fb_data); 506 imx27_add_imx_fb(&mx27_3ds_fb_data);
507
508 ret = gpio_request_array(mx27_3ds_camera_gpios,
509 ARRAY_SIZE(mx27_3ds_camera_gpios));
510 if (ret) {
511 pr_err("Failed to request camera gpios");
512 iclink_ov2640.power = NULL;
513 }
514
515 imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
408} 516}
409 517
410static void __init mx27pdk_timer_init(void) 518static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 4917aab0e253..4518e5448227 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -28,7 +28,6 @@
28#include <asm/memory.h> 28#include <asm/memory.h>
29#include <asm/mach/map.h> 29#include <asm/mach/map.h>
30#include <mach/common.h> 30#include <mach/common.h>
31#include <mach/board-mx31ads.h>
32#include <mach/iomux-mx3.h> 31#include <mach/iomux-mx3.h>
33 32
34#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 33#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -39,6 +38,9 @@
39 38
40#include "devices-imx31.h" 39#include "devices-imx31.h"
41 40
41/* Base address of PBC controller */
42#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
43
42/* PBC Board interrupt status register */ 44/* PBC Board interrupt status register */
43#define PBC_INTSTATUS 0x000016 45#define PBC_INTSTATUS 0x000016
44 46
@@ -62,6 +64,7 @@
62#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) 64#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
63#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) 65#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
64 66
67#define MXC_EXP_IO_BASE MXC_BOARD_IRQ_START
65#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) 68#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
66 69
67#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) 70#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
@@ -69,6 +72,10 @@
69 72
70#define MXC_MAX_EXP_IO_LINES 16 73#define MXC_MAX_EXP_IO_LINES 16
71 74
75/* CS8900 */
76#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
77#define CS4_CS8900_MMIO_START 0x20000
78
72/* 79/*
73 * The serial port definition structure. 80 * The serial port definition structure.
74 */ 81 */
@@ -101,11 +108,29 @@ static struct platform_device serial_device = {
101 }, 108 },
102}; 109};
103 110
111static const struct resource mx31ads_cs8900_resources[] __initconst = {
112 DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
113 DEFINE_RES_IRQ(EXPIO_INT_ENET_INT),
114};
115
116static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
117 .name = "cs89x0",
118 .id = 0,
119 .res = mx31ads_cs8900_resources,
120 .num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
121};
122
104static int __init mxc_init_extuart(void) 123static int __init mxc_init_extuart(void)
105{ 124{
106 return platform_device_register(&serial_device); 125 return platform_device_register(&serial_device);
107} 126}
108 127
128static void __init mxc_init_ext_ethernet(void)
129{
130 platform_device_register_full(
131 (struct platform_device_info *)&mx31ads_cs8900_devinfo);
132}
133
109static const struct imxuart_platform_data uart_pdata __initconst = { 134static const struct imxuart_platform_data uart_pdata __initconst = {
110 .flags = IMXUART_HAVE_RTSCTS, 135 .flags = IMXUART_HAVE_RTSCTS,
111}; 136};
@@ -492,12 +517,15 @@ static void __init mxc_init_audio(void)
492 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); 517 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
493} 518}
494 519
495/* static mappings */ 520/*
521 * Static mappings, starting from the CS4 start address up to the start address
522 * of the CS8900.
523 */
496static struct map_desc mx31ads_io_desc[] __initdata = { 524static struct map_desc mx31ads_io_desc[] __initdata = {
497 { 525 {
498 .virtual = MX31_CS4_BASE_ADDR_VIRT, 526 .virtual = MX31_CS4_BASE_ADDR_VIRT,
499 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), 527 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
500 .length = MX31_CS4_SIZE / 2, 528 .length = CS4_CS8900_MMIO_START,
501 .type = MT_DEVICE 529 .type = MT_DEVICE
502 }, 530 },
503}; 531};
@@ -522,6 +550,7 @@ static void __init mx31ads_init(void)
522 mxc_init_imx_uart(); 550 mxc_init_imx_uart();
523 mxc_init_i2c(); 551 mxc_init_i2c();
524 mxc_init_audio(); 552 mxc_init_audio();
553 mxc_init_ext_ethernet();
525} 554}
526 555
527static void __init mx31ads_timer_init(void) 556static void __init mx31ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index f225262b5c38..f17a15f28316 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -507,7 +507,7 @@ static void mx31moboard_poweroff(void)
507 struct clk *clk = clk_get_sys("imx2-wdt.0", NULL); 507 struct clk *clk = clk_get_sys("imx2-wdt.0", NULL);
508 508
509 if (!IS_ERR(clk)) 509 if (!IS_ERR(clk))
510 clk_enable(clk); 510 clk_prepare_enable(clk);
511 511
512 mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST); 512 mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
513 513
@@ -530,6 +530,8 @@ static void __init mx31moboard_init(void)
530 platform_add_devices(devices, ARRAY_SIZE(devices)); 530 platform_add_devices(devices, ARRAY_SIZE(devices));
531 gpio_led_register_device(-1, &mx31moboard_led_pdata); 531 gpio_led_register_device(-1, &mx31moboard_led_pdata);
532 532
533 imx31_add_imx2_wdt(NULL);
534
533 imx31_add_imx_uart0(&uart0_pdata); 535 imx31_add_imx_uart0(&uart0_pdata);
534 imx31_add_imx_uart4(&uart4_pdata); 536 imx31_add_imx_uart4(&uart4_pdata);
535 537
@@ -590,7 +592,7 @@ static void __init mx31moboard_reserve(void)
590} 592}
591 593
592MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") 594MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
593 /* Maintainer: Valentin Longchamp, EPFL Mobots group */ 595 /* Maintainer: Philippe Retornaz, EPFL Mobots group */
594 .atag_offset = 0x100, 596 .atag_offset = 0x100,
595 .reserve = mx31moboard_reserve, 597 .reserve = mx31moboard_reserve,
596 .map_io = mx31_map_io, 598 .map_io = mx31_map_io,
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c5b3fd..e14291d89e4f 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -4,6 +4,11 @@
4 * 4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * 6 *
7 * Copyright (C) 2011 Meprolight, Ltd.
8 * Alex Gershgorin <alexg@meprolight.com>
9 *
10 * Modified from i.MX31 3-Stack Development System
11 *
7 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 13 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 14 * the Free Software Foundation; either version 2 of the License, or
@@ -34,15 +39,102 @@
34#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
35#include <asm/mach/time.h> 40#include <asm/mach/time.h>
36#include <asm/mach/map.h> 41#include <asm/mach/map.h>
42#include <asm/memblock.h>
37 43
38#include <mach/hardware.h> 44#include <mach/hardware.h>
39#include <mach/common.h> 45#include <mach/common.h>
40#include <mach/iomux-mx35.h> 46#include <mach/iomux-mx35.h>
41#include <mach/irqs.h> 47#include <mach/irqs.h>
42#include <mach/3ds_debugboard.h> 48#include <mach/3ds_debugboard.h>
49#include <video/platform_lcd.h>
50
51#include <media/soc_camera.h>
43 52
44#include "devices-imx35.h" 53#include "devices-imx35.h"
45 54
55#define GPIO_MC9S08DZ60_GPS_ENABLE 0
56#define GPIO_MC9S08DZ60_HDD_ENABLE 4
57#define GPIO_MC9S08DZ60_WIFI_ENABLE 5
58#define GPIO_MC9S08DZ60_LCD_ENABLE 6
59#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8
60
61static const struct fb_videomode fb_modedb[] = {
62 {
63 /* 800x480 @ 55 Hz */
64 .name = "Ceramate-CLAA070VC01",
65 .refresh = 55,
66 .xres = 800,
67 .yres = 480,
68 .pixclock = 40000,
69 .left_margin = 40,
70 .right_margin = 40,
71 .upper_margin = 5,
72 .lower_margin = 5,
73 .hsync_len = 20,
74 .vsync_len = 10,
75 .sync = FB_SYNC_OE_ACT_HIGH,
76 .vmode = FB_VMODE_NONINTERLACED,
77 .flag = 0,
78 },
79};
80
81static const struct ipu_platform_data mx3_ipu_data __initconst = {
82 .irq_base = MXC_IPU_IRQ_START,
83};
84
85static struct mx3fb_platform_data mx3fb_pdata __initdata = {
86 .name = "Ceramate-CLAA070VC01",
87 .mode = fb_modedb,
88 .num_modes = ARRAY_SIZE(fb_modedb),
89};
90
91static struct i2c_board_info __initdata i2c_devices_3ds[] = {
92 {
93 I2C_BOARD_INFO("mc9s08dz60", 0x69),
94 },
95};
96
97static int lcd_power_gpio = -ENXIO;
98
99static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
100 void *data)
101{
102 return !strcmp(chip->label, data);
103}
104
105static void mx35_3ds_lcd_set_power(
106 struct plat_lcd_data *pd, unsigned int power)
107{
108 struct gpio_chip *chip;
109
110 if (!gpio_is_valid(lcd_power_gpio)) {
111 chip = gpiochip_find(
112 "mc9s08dz60", mc9s08dz60_gpiochip_match);
113 if (chip) {
114 lcd_power_gpio =
115 chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
116 if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
117 pr_err("error: gpio already requested!\n");
118 lcd_power_gpio = -ENXIO;
119 }
120 } else {
121 pr_err("error: didn't find mc9s08dz60 gpio chip\n");
122 }
123 }
124
125 if (gpio_is_valid(lcd_power_gpio))
126 gpio_set_value_cansleep(lcd_power_gpio, power);
127}
128
129static struct plat_lcd_data mx35_3ds_lcd_data = {
130 .set_power = mx35_3ds_lcd_set_power,
131};
132
133static struct platform_device mx35_3ds_lcd = {
134 .name = "platform-lcd",
135 .dev.platform_data = &mx35_3ds_lcd_data,
136};
137
46#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 1)) 138#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 1))
47 139
48static const struct imxuart_platform_data uart_pdata __initconst = { 140static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -120,6 +212,109 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
120 /* I2C1 */ 212 /* I2C1 */
121 MX35_PAD_I2C1_CLK__I2C1_SCL, 213 MX35_PAD_I2C1_CLK__I2C1_SCL,
122 MX35_PAD_I2C1_DAT__I2C1_SDA, 214 MX35_PAD_I2C1_DAT__I2C1_SDA,
215 /* Display */
216 MX35_PAD_LD0__IPU_DISPB_DAT_0,
217 MX35_PAD_LD1__IPU_DISPB_DAT_1,
218 MX35_PAD_LD2__IPU_DISPB_DAT_2,
219 MX35_PAD_LD3__IPU_DISPB_DAT_3,
220 MX35_PAD_LD4__IPU_DISPB_DAT_4,
221 MX35_PAD_LD5__IPU_DISPB_DAT_5,
222 MX35_PAD_LD6__IPU_DISPB_DAT_6,
223 MX35_PAD_LD7__IPU_DISPB_DAT_7,
224 MX35_PAD_LD8__IPU_DISPB_DAT_8,
225 MX35_PAD_LD9__IPU_DISPB_DAT_9,
226 MX35_PAD_LD10__IPU_DISPB_DAT_10,
227 MX35_PAD_LD11__IPU_DISPB_DAT_11,
228 MX35_PAD_LD12__IPU_DISPB_DAT_12,
229 MX35_PAD_LD13__IPU_DISPB_DAT_13,
230 MX35_PAD_LD14__IPU_DISPB_DAT_14,
231 MX35_PAD_LD15__IPU_DISPB_DAT_15,
232 MX35_PAD_LD16__IPU_DISPB_DAT_16,
233 MX35_PAD_LD17__IPU_DISPB_DAT_17,
234 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
235 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
236 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
237 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
238 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
239 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
240 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
241 /* CSI */
242 MX35_PAD_TX1__IPU_CSI_D_6,
243 MX35_PAD_TX0__IPU_CSI_D_7,
244 MX35_PAD_CSI_D8__IPU_CSI_D_8,
245 MX35_PAD_CSI_D9__IPU_CSI_D_9,
246 MX35_PAD_CSI_D10__IPU_CSI_D_10,
247 MX35_PAD_CSI_D11__IPU_CSI_D_11,
248 MX35_PAD_CSI_D12__IPU_CSI_D_12,
249 MX35_PAD_CSI_D13__IPU_CSI_D_13,
250 MX35_PAD_CSI_D14__IPU_CSI_D_14,
251 MX35_PAD_CSI_D15__IPU_CSI_D_15,
252 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC,
253 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
254 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
255 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
256};
257
258/*
259 * Camera support
260*/
261static phys_addr_t mx3_camera_base __initdata;
262#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M
263
264static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = {
265 .flags = MX3_CAMERA_DATAWIDTH_8,
266 .mclk_10khz = 2000,
267};
268
269static int __init imx35_3ds_init_camera(void)
270{
271 int dma, ret = -ENOMEM;
272 struct platform_device *pdev =
273 imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata);
274
275 if (IS_ERR(pdev))
276 return PTR_ERR(pdev);
277
278 if (!mx3_camera_base)
279 goto err;
280
281 dma = dma_declare_coherent_memory(&pdev->dev,
282 mx3_camera_base, mx3_camera_base,
283 MX35_3DS_CAMERA_BUF_SIZE,
284 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
285
286 if (!(dma & DMA_MEMORY_MAP))
287 goto err;
288
289 ret = platform_device_add(pdev);
290 if (ret)
291err:
292 platform_device_put(pdev);
293
294 return ret;
295}
296
297static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
298 .irq_base = MXC_IPU_IRQ_START,
299};
300
301static struct i2c_board_info mx35_3ds_i2c_camera = {
302 I2C_BOARD_INFO("ov2640", 0x30),
303};
304
305static struct soc_camera_link iclink_ov2640 = {
306 .bus_id = 0,
307 .board_info = &mx35_3ds_i2c_camera,
308 .i2c_adapter_id = 0,
309 .power = NULL,
310};
311
312static struct platform_device mx35_3ds_ov2640 = {
313 .name = "soc-camera-pdrv",
314 .id = 0,
315 .dev = {
316 .platform_data = &iclink_ov2640,
317 },
123}; 318};
124 319
125static int mx35_3ds_otg_init(struct platform_device *pdev) 320static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -179,6 +374,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
179 */ 374 */
180static void __init mx35_3ds_init(void) 375static void __init mx35_3ds_init(void)
181{ 376{
377 struct platform_device *imx35_fb_pdev;
378
182 imx35_soc_init(); 379 imx35_soc_init();
183 380
184 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); 381 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
@@ -204,6 +401,17 @@ static void __init mx35_3ds_init(void)
204 pr_warn("Init of the debugboard failed, all " 401 pr_warn("Init of the debugboard failed, all "
205 "devices on the debugboard are unusable.\n"); 402 "devices on the debugboard are unusable.\n");
206 imx35_add_imx_i2c0(&mx35_3ds_i2c0_data); 403 imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
404
405 i2c_register_board_info(
406 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
407
408 imx35_add_ipu_core(&mx35_3ds_ipu_data);
409 platform_device_register(&mx35_3ds_ov2640);
410 imx35_3ds_init_camera();
411
412 imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
413 mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
414 platform_device_register(&mx35_3ds_lcd);
207} 415}
208 416
209static void __init mx35pdk_timer_init(void) 417static void __init mx35pdk_timer_init(void)
@@ -215,6 +423,13 @@ struct sys_timer mx35pdk_timer = {
215 .init = mx35pdk_timer_init, 423 .init = mx35pdk_timer_init,
216}; 424};
217 425
426static void __init mx35_3ds_reserve(void)
427{
428 /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
429 mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE,
430 MX35_3DS_CAMERA_BUF_SIZE);
431}
432
218MACHINE_START(MX35_3DS, "Freescale MX35PDK") 433MACHINE_START(MX35_3DS, "Freescale MX35PDK")
219 /* Maintainer: Freescale Semiconductor, Inc */ 434 /* Maintainer: Freescale Semiconductor, Inc */
220 .atag_offset = 0x100, 435 .atag_offset = 0x100,
@@ -224,5 +439,6 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
224 .handle_irq = imx35_handle_irq, 439 .handle_irq = imx35_handle_irq,
225 .timer = &mx35pdk_timer, 440 .timer = &mx35pdk_timer,
226 .init_machine = mx35_3ds_init, 441 .init_machine = mx35_3ds_init,
442 .reserve = mx35_3ds_reserve,
227 .restart = mxc_restart, 443 .restart = mxc_restart,
228MACHINE_END 444MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
index 3a5ed2dd885a..586e9f822124 100644
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ b/arch/arm/mach-imx/mach-mx51_efikamx.c
@@ -33,6 +33,7 @@
33#include <mach/iomux-mx51.h> 33#include <mach/iomux-mx51.h>
34 34
35#include <asm/setup.h> 35#include <asm/setup.h>
36#include <asm/system_info.h>
36#include <asm/mach-types.h> 37#include <asm/mach-types.h>
37#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
38#include <asm/mach/time.h> 39#include <asm/mach/time.h>
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
index ea5f65b0381a..24aded9e109f 100644
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ b/arch/arm/mach-imx/mach-mx51_efikasb.c
@@ -36,6 +36,7 @@
36#include <mach/iomux-mx51.h> 36#include <mach/iomux-mx51.h>
37 37
38#include <asm/setup.h> 38#include <asm/setup.h>
39#include <asm/system_info.h>
39#include <asm/mach-types.h> 40#include <asm/mach-types.h>
40#include <asm/mach/arch.h> 41#include <asm/mach/arch.h>
41#include <asm/mach/time.h> 42#include <asm/mach/time.h>
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 16f126da9f8f..2f3debe2a113 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -233,7 +233,7 @@ static struct regulator_init_data sdhc1_data = {
233 233
234static struct regulator_consumer_supply cam_consumers[] = { 234static struct regulator_consumer_supply cam_consumers[] = {
235 { 235 {
236 .dev = NULL, 236 .dev_name = NULL,
237 .supply = "imx_cam_vcc", 237 .supply = "imx_cam_vcc",
238 }, 238 },
239}; 239};
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 9c9b7f9f43dc..d534d7f988e0 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -34,6 +34,8 @@ static void imx3_idle(void)
34{ 34{
35 unsigned long reg = 0; 35 unsigned long reg = 0;
36 36
37 mx3_cpu_lp_set(MX3_WAIT);
38
37 __asm__ __volatile__( 39 __asm__ __volatile__(
38 /* disable I and D cache */ 40 /* disable I and D cache */
39 "mrc p15, 0, %0, c1, c0, 0\n" 41 "mrc p15, 0, %0, c1, c0, 0\n"
@@ -59,8 +61,8 @@ static void imx3_idle(void)
59 : "=r" (reg)); 61 : "=r" (reg));
60} 62}
61 63
62static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size, 64static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
63 unsigned int mtype) 65 unsigned int mtype, void *caller)
64{ 66{
65 if (mtype == MT_DEVICE) { 67 if (mtype == MT_DEVICE) {
66 /* 68 /*
@@ -73,10 +75,10 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
73 mtype = MT_DEVICE_NONSHARED; 75 mtype = MT_DEVICE_NONSHARED;
74 } 76 }
75 77
76 return __arm_ioremap(phys_addr, size, mtype); 78 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
77} 79}
78 80
79void imx3_init_l2x0(void) 81void __init imx3_init_l2x0(void)
80{ 82{
81 void __iomem *l2x0_base; 83 void __iomem *l2x0_base;
82 void __iomem *clkctl_base; 84 void __iomem *clkctl_base;
@@ -132,7 +134,7 @@ void __init imx31_init_early(void)
132{ 134{
133 mxc_set_cpu_type(MXC_CPU_MX31); 135 mxc_set_cpu_type(MXC_CPU_MX31);
134 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); 136 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
135 imx_ioremap = imx3_ioremap; 137 arch_ioremap_caller = imx3_ioremap_caller;
136 arm_pm_idle = imx3_idle; 138 arm_pm_idle = imx3_idle;
137} 139}
138 140
@@ -177,6 +179,10 @@ void __init imx31_soc_init(void)
177 } 179 }
178 180
179 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); 181 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
182
183 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
184 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
185
180 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, 186 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
181 ARRAY_SIZE(imx31_audmux_res)); 187 ARRAY_SIZE(imx31_audmux_res));
182} 188}
@@ -202,7 +208,7 @@ void __init imx35_init_early(void)
202 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 208 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
203 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); 209 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
204 arm_pm_idle = imx3_idle; 210 arm_pm_idle = imx3_idle;
205 imx_ioremap = imx3_ioremap; 211 arch_ioremap_caller = imx3_ioremap_caller;
206} 212}
207 213
208void __init mx35_init_irq(void) 214void __init mx35_init_irq(void)
@@ -267,6 +273,11 @@ void __init imx35_soc_init(void)
267 } 273 }
268 274
269 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); 275 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
276
277 /* Setup AIPS registers */
278 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
279 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
280
270 /* i.mx35 has the i.mx31 type audmux */ 281 /* i.mx35 has the i.mx31 type audmux */
271 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, 282 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
272 ARRAY_SIZE(imx35_audmux_res)); 283 ARRAY_SIZE(imx35_audmux_res));
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index dc7c4ed81531..51af9fa56944 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -201,6 +201,11 @@ void __init imx51_soc_init(void)
201 201
202 /* i.mx51 has the i.mx35 type sdma */ 202 /* i.mx51 has the i.mx35 type sdma */
203 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); 203 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
204
205 /* Setup AIPS registers */
206 imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
207 imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
208
204 /* i.mx51 has the i.mx31 type audmux */ 209 /* i.mx51 has the i.mx31 type audmux */
205 platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res, 210 platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
206 ARRAY_SIZE(imx51_audmux_res)); 211 ARRAY_SIZE(imx51_audmux_res));
@@ -219,6 +224,11 @@ void __init imx53_soc_init(void)
219 224
220 /* i.mx53 has the i.mx35 type sdma */ 225 /* i.mx53 has the i.mx35 type sdma */
221 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); 226 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
227
228 /* Setup AIPS registers */
229 imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
230 imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
231
222 /* i.mx53 has the i.mx31 type audmux */ 232 /* i.mx53 has the i.mx31 type audmux */
223 platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res, 233 platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
224 ARRAY_SIZE(imx53_audmux_res)); 234 ARRAY_SIZE(imx53_audmux_res));
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
new file mode 100644
index 000000000000..b3752439632e
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx3.c
@@ -0,0 +1,37 @@
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#include <linux/io.h>
12#include <mach/common.h>
13#include <mach/hardware.h>
14#include <mach/devices-common.h>
15#include "crmregs-imx3.h"
16
17/*
18 * Set cpu low power mode before WFI instruction. This function is called
19 * mx3 because it can be used for mx31 and mx35.
20 * Currently only WAIT_MODE is supported.
21 */
22void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
23{
24 int reg = __raw_readl(MXC_CCM_CCMR);
25 reg &= ~MXC_CCM_CCMR_LPM_MASK;
26
27 switch (mode) {
28 case MX3_WAIT:
29 if (cpu_is_mx35())
30 reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
31 __raw_writel(reg, MXC_CCM_CCMR);
32 break;
33 default:
34 pr_err("Unknown cpu power mode: %d\n", mode);
35 return;
36 }
37}
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 6dc093448057..e26a9cb05ed8 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -89,7 +89,7 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
89 89
90static int mx5_suspend_prepare(void) 90static int mx5_suspend_prepare(void)
91{ 91{
92 return clk_enable(gpc_dvfs_clk); 92 return clk_prepare_enable(gpc_dvfs_clk);
93} 93}
94 94
95static int mx5_suspend_enter(suspend_state_t state) 95static int mx5_suspend_enter(suspend_state_t state)
@@ -119,7 +119,7 @@ static int mx5_suspend_enter(suspend_state_t state)
119 119
120static void mx5_suspend_finish(void) 120static void mx5_suspend_finish(void)
121{ 121{
122 clk_disable(gpc_dvfs_clk); 122 clk_disable_unprepare(gpc_dvfs_clk);
123} 123}
124 124
125static int mx5_pm_valid(suspend_state_t state) 125static int mx5_pm_valid(suspend_state_t state)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 18:05:39 -0500