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-rw-r--r--arch/arm/mach-imx/Kconfig106
-rw-r--r--arch/arm/mach-imx/Makefile11
-rw-r--r--arch/arm/mach-imx/Makefile.boot7
-rw-r--r--arch/arm/mach-imx/clk-imx21.c1
-rw-r--r--arch/arm/mach-imx/clk-imx25.c6
-rw-r--r--arch/arm/mach-imx/clk-imx35.c17
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c18
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c51
-rw-r--r--arch/arm/mach-imx/clk-pllv1.c49
-rw-r--r--arch/arm/mach-imx/clk.c3
-rw-r--r--arch/arm/mach-imx/clk.h3
-rw-r--r--arch/arm/mach-imx/devices-imx53.h48
-rw-r--r--arch/arm/mach-imx/efika.h10
-rw-r--r--arch/arm/mach-imx/imx51-dt.c21
-rw-r--r--arch/arm/mach-imx/mach-imx53.c (renamed from arch/arm/mach-imx/imx53-dt.c)27
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c11
-rw-r--r--arch/arm/mach-imx/mach-kzm_arm11_01.c1
-rw-r--r--arch/arm/mach-imx/mach-mx51_efikamx.c300
-rw-r--r--arch/arm/mach-imx/mach-mx51_efikasb.c296
-rw-r--r--arch/arm/mach-imx/mach-mx53_ard.c272
-rw-r--r--arch/arm/mach-imx/mach-mx53_evk.c179
-rw-r--r--arch/arm/mach-imx/mach-mx53_loco.c321
-rw-r--r--arch/arm/mach-imx/mach-mx53_smd.c168
-rw-r--r--arch/arm/mach-imx/mm-imx5.c47
-rw-r--r--arch/arm/mach-imx/mx51_efika.c633
25 files changed, 104 insertions, 2502 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542ad6f97..7ca5fe45945f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -101,13 +101,8 @@ config SOC_IMX51
101 select SOC_IMX5 101 select SOC_IMX5
102 select ARCH_MX5 102 select ARCH_MX5
103 select ARCH_MX51 103 select ARCH_MX51
104 104 select PINCTRL
105config SOC_IMX53 105 select PINCTRL_IMX51
106 bool
107 select SOC_IMX5
108 select ARCH_MX5
109 select ARCH_MX53
110 select HAVE_CAN_FLEXCAN if CAN
111 106
112if ARCH_IMX_V4_V5 107if ARCH_IMX_V4_V5
113 108
@@ -561,7 +556,6 @@ config MACH_BUG
561config MACH_IMX31_DT 556config MACH_IMX31_DT
562 bool "Support i.MX31 platforms from device tree" 557 bool "Support i.MX31 platforms from device tree"
563 select SOC_IMX31 558 select SOC_IMX31
564 select USE_OF
565 help 559 help
566 Include support for Freescale i.MX31 based platforms 560 Include support for Freescale i.MX31 based platforms
567 using the device tree for discovery. 561 using the device tree for discovery.
@@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
737 731
738endchoice 732endchoice
739 733
740config MX51_EFIKA_COMMON 734comment "Device tree only"
741 bool
742 select SOC_IMX51
743 select IMX_HAVE_PLATFORM_IMX_UART
744 select IMX_HAVE_PLATFORM_MXC_EHCI
745 select IMX_HAVE_PLATFORM_PATA_IMX
746 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
747 select IMX_HAVE_PLATFORM_SPI_IMX
748 select MXC_ULPI if USB_ULPI
749
750config MACH_MX51_EFIKAMX
751 bool "Support MX51 Genesi Efika MX nettop"
752 select LEDS_GPIO_REGISTER
753 select MX51_EFIKA_COMMON
754 help
755 Include support for Genesi Efika MX nettop. This includes specific
756 configurations for the board and its peripherals.
757
758config MACH_MX51_EFIKASB
759 bool "Support MX51 Genesi Efika Smartbook"
760 select LEDS_GPIO_REGISTER
761 select MX51_EFIKA_COMMON
762 help
763 Include support for Genesi Efika Smartbook. This includes specific
764 configurations for the board and its peripherals.
765
766comment "i.MX53 machines:"
767
768config MACH_IMX53_DT
769 bool "Support i.MX53 platforms from device tree"
770 select SOC_IMX53
771 select MACH_MX53_ARD
772 select MACH_MX53_EVK
773 select MACH_MX53_LOCO
774 select MACH_MX53_SMD
775 help
776 Include support for Freescale i.MX53 based platforms
777 using the device tree for discovery
778
779config MACH_MX53_EVK
780 bool "Support MX53 EVK platforms"
781 select SOC_IMX53
782 select IMX_HAVE_PLATFORM_IMX2_WDT
783 select IMX_HAVE_PLATFORM_IMX_UART
784 select IMX_HAVE_PLATFORM_IMX_I2C
785 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
786 select IMX_HAVE_PLATFORM_SPI_IMX
787 select LEDS_GPIO_REGISTER
788 help
789 Include support for MX53 EVK platform. This includes specific
790 configurations for the board and its peripherals.
791
792config MACH_MX53_SMD
793 bool "Support MX53 SMD platforms"
794 select SOC_IMX53
795 select IMX_HAVE_PLATFORM_IMX2_WDT
796 select IMX_HAVE_PLATFORM_IMX_I2C
797 select IMX_HAVE_PLATFORM_IMX_UART
798 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
799 help
800 Include support for MX53 SMD platform. This includes specific
801 configurations for the board and its peripherals.
802 735
803config MACH_MX53_LOCO 736config SOC_IMX53
804 bool "Support MX53 LOCO platforms" 737 bool "i.MX53 support"
805 select SOC_IMX53 738 select SOC_IMX5
806 select IMX_HAVE_PLATFORM_IMX2_WDT 739 select ARCH_MX5
807 select IMX_HAVE_PLATFORM_IMX_I2C 740 select ARCH_MX53
808 select IMX_HAVE_PLATFORM_IMX_UART 741 select HAVE_CAN_FLEXCAN if CAN
809 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 742 select PINCTRL
810 select IMX_HAVE_PLATFORM_GPIO_KEYS 743 select PINCTRL_IMX53
811 select LEDS_GPIO_REGISTER
812 help
813 Include support for MX53 LOCO platform. This includes specific
814 configurations for the board and its peripherals.
815 744
816config MACH_MX53_ARD
817 bool "Support MX53 ARD platforms"
818 select SOC_IMX53
819 select IMX_HAVE_PLATFORM_IMX2_WDT
820 select IMX_HAVE_PLATFORM_IMX_I2C
821 select IMX_HAVE_PLATFORM_IMX_UART
822 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
823 select IMX_HAVE_PLATFORM_GPIO_KEYS
824 help 745 help
825 Include support for MX53 ARD platform. This includes specific 746 This enables support for Freescale i.MX53 processor.
826 configurations for the board and its peripherals.
827
828comment "i.MX6 family:"
829 747
830config SOC_IMX6Q 748config SOC_IMX6Q
831 bool "i.MX6 Quad support" 749 bool "i.MX6 Quad support"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d004d37ad9d8..895754aeb4f3 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -13,7 +13,7 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o
13obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o 13obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
14 14
15obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ 15obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
16 clk-pfd.o clk-busy.o 16 clk-pfd.o clk-busy.o clk.o
17 17
18# Support for CMOS sensor interface 18# Support for CMOS sensor interface
19obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o 19obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -83,16 +83,9 @@ endif
83# i.MX5 based machines 83# i.MX5 based machines
84obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o 84obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
85obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o 85obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
86obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
87obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
88obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
89obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
90obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o 86obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
91obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o 87obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
92obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
93obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
94obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
95obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o 88obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
96 89
97obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o 90obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
98obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o 91obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 05541cf4a878..b27815de8473 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -37,10 +37,3 @@ initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
37zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000 37zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
38params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 38params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
39initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 39initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
40
41dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
42dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
43 imx53-qsb.dtb imx53-smd.dtb
44dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
45 imx6q-sabrelite.dtb \
46 imx6q-sabresd.dtb \
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index ea13e61bd5f3..cf65148bc519 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -23,7 +23,6 @@
23#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/clkdev.h>
27#include <linux/err.h> 26#include <linux/err.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index fdd8cc87c9fe..4431a62fff5b 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -222,10 +222,8 @@ int __init mx25_clocks_init(void)
222 clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0"); 222 clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
223 clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0"); 223 clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
224 clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0"); 224 clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
225 clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0"); 225 clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
226 clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0"); 226 clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
227 clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
228 clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
229 clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0"); 227 clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
230 clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0"); 228 clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
231 clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0"); 229 clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index c6422fb10bae..177259b523cd 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -62,8 +62,8 @@ enum mx35_clks {
62 kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, 62 kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
63 rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, 63 rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
64 ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, 64 ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
65 wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate, 65 wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
66 clk_max 66 gpu2d_gate, clk_max
67}; 67};
68 68
69static struct clk *clk[clk_max]; 69static struct clk *clk[clk_max];
@@ -142,6 +142,9 @@ int __init mx35_clocks_init()
142 142
143 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); 143 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
144 144
145 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
146 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
147
145 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); 148 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0);
146 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); 149 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2);
147 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); 150 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4);
@@ -192,7 +195,7 @@ int __init mx35_clocks_init()
192 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); 195 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
193 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); 196 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
194 197
195 clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3, 0); 198 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0);
196 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); 199 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
197 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); 200 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
198 201
@@ -228,12 +231,11 @@ int __init mx35_clocks_init()
228 clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2"); 231 clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
229 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); 232 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
230 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); 233 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
234 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
231 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); 235 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
232 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); 236 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
233 clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0"); 237 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
234 clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0"); 238 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
235 clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
236 clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
237 /* i.mx35 has the i.mx21 type uart */ 239 /* i.mx35 has the i.mx21 type uart */
238 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); 240 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
239 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); 241 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
@@ -255,6 +257,7 @@ int __init mx35_clocks_init()
255 clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc"); 257 clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
256 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); 258 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
257 clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0"); 259 clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
260 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
258 261
259 clk_prepare_enable(clk[spba_gate]); 262 clk_prepare_enable(clk[spba_gate]);
260 clk_prepare_enable(clk[gpio1_gate]); 263 clk_prepare_enable(clk[gpio1_gate]);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa97bd98..e5165a84f93f 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -39,16 +39,17 @@ static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
39static const char *emi_slow_sel[] = { "main_bus", "ahb", }; 39static const char *emi_slow_sel[] = { "main_bus", "ahb", };
40static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", }; 40static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
41static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", }; 41static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
42static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", }; 42static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
43static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", }; 43static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
44static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", }; 44static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
45static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", }; 45static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
46static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", }; 46static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
47static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; 47static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
48static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; 48static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
49static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", }; 49static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
50static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; 50static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
51static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; 51static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
52static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
52 53
53enum imx5_clks { 54enum imx5_clks {
54 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, 55 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -82,6 +83,7 @@ enum imx5_clks {
82 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, 83 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
83 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, 84 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
84 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, 85 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
86 can_sel, can1_serial_gate, can1_ipg_gate,
85 clk_max 87 clk_max
86}; 88};
87 89
@@ -421,8 +423,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
421 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); 423 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
422 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); 424 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
423 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); 425 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
424 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6); 426 clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
425 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8); 427 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
428 clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
429 clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
430 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
431 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
426 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); 432 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
427 433
428 for (i = 0; i < ARRAY_SIZE(clk); i++) 434 for (i = 0; i < ARRAY_SIZE(clk); i++)
@@ -455,6 +461,10 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
455 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi"); 461 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
456 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi"); 462 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
457 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi"); 463 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
464 clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
465 clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
466 clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
467 clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
458 468
459 /* set SDHC root clock to 200MHZ*/ 469 /* set SDHC root clock to 200MHZ*/
460 clk_set_rate(clk[esdhc_a_podf], 200000000); 470 clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4233d9e3531d..3ec242f3341e 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -157,6 +157,7 @@ enum mx6q_clks {
157}; 157};
158 158
159static struct clk *clk[clk_max]; 159static struct clk *clk[clk_max];
160static struct clk_onecell_data clk_data;
160 161
161static enum mx6q_clks const clks_init_on[] __initconst = { 162static enum mx6q_clks const clks_init_on[] __initconst = {
162 mmdc_ch0_axi, rom, 163 mmdc_ch0_axi, rom,
@@ -394,52 +395,24 @@ int __init mx6q_clocks_init(void)
394 pr_err("i.MX6q clk %d: register failed with %ld\n", 395 pr_err("i.MX6q clk %d: register failed with %ld\n",
395 i, PTR_ERR(clk[i])); 396 i, PTR_ERR(clk[i]));
396 397
398 clk_data.clks = clk;
399 clk_data.clk_num = ARRAY_SIZE(clk);
400 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
401
397 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); 402 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
398 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 403 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
399 clk_register_clkdev(clk[twd], NULL, "smp_twd"); 404 clk_register_clkdev(clk[twd], NULL, "smp_twd");
400 clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
401 clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
402 clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
403 clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
404 clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
405 clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
406 clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
407 clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
408 clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
409 clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
410 clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
411 clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
412 clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
413 clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
414 clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
415 clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
416 clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
417 clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
418 clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
419 clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
420 clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
421 clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
422 clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
423 clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
424 clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
425 clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
426 clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
427 clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
428 clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
429 clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
430 clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
431 clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
432 clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
433 clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
434 clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
435 clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
436 clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
437 clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
438 clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
439 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); 405 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
440 clk_register_clkdev(clk[ahb], "ahb", NULL); 406 clk_register_clkdev(clk[ahb], "ahb", NULL);
441 clk_register_clkdev(clk[cko1], "cko1", NULL); 407 clk_register_clkdev(clk[cko1], "cko1", NULL);
442 408
409 /*
410 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
411 * We can not get the 100MHz from the pll2_pfd0_352m.
412 * So choose pll2_pfd2_396m as enfc_sel's parent.
413 */
414 clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
415
443 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 416 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
444 clk_prepare_enable(clk[clks_init_on[i]]); 417 clk_prepare_enable(clk[clks_init_on[i]]);
445 418
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 2d856f9ccf59..02be73178912 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -6,7 +6,7 @@
6#include <linux/err.h> 6#include <linux/err.h>
7#include <mach/common.h> 7#include <mach/common.h>
8#include <mach/hardware.h> 8#include <mach/hardware.h>
9#include <mach/clock.h> 9
10#include "clk.h" 10#include "clk.h"
11 11
12/** 12/**
@@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
29 unsigned long parent_rate) 29 unsigned long parent_rate)
30{ 30{
31 struct clk_pllv1 *pll = to_clk_pllv1(hw); 31 struct clk_pllv1 *pll = to_clk_pllv1(hw);
32 long long ll;
33 int mfn_abs;
34 unsigned int mfi, mfn, mfd, pd;
35 u32 reg;
36 unsigned long rate;
37
38 reg = readl(pll->base);
39
40 /*
41 * Get the resulting clock rate from a PLL register value and the input
42 * frequency. PLLs with this register layout can be found on i.MX1,
43 * i.MX21, i.MX27 and i,MX31
44 *
45 * mfi + mfn / (mfd + 1)
46 * f = 2 * f_ref * --------------------
47 * pd + 1
48 */
49
50 mfi = (reg >> 10) & 0xf;
51 mfn = reg & 0x3ff;
52 mfd = (reg >> 16) & 0x3ff;
53 pd = (reg >> 26) & 0xf;
54
55 mfi = mfi <= 5 ? 5 : mfi;
56
57 mfn_abs = mfn;
58
59 /*
60 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
61 * 2's complements number
62 */
63 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
64 mfn_abs = 0x400 - mfn;
65
66 rate = parent_rate * 2;
67 rate /= pd + 1;
68
69 ll = (unsigned long long)rate * mfn_abs;
70
71 do_div(ll, mfd + 1);
72
73 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
74 ll = -ll;
75
76 ll = (rate * mfi) + ll;
32 77
33 return mxc_decode_pll(readl(pll->base), parent_rate); 78 return ll;
34} 79}
35 80
36struct clk_ops clk_pllv1_ops = { 81struct clk_ops clk_pllv1_ops = {
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
new file mode 100644
index 000000000000..f5e8be8e7f11
--- /dev/null
+++ b/arch/arm/mach-imx/clk.c
@@ -0,0 +1,3 @@
1#include <linux/spinlock.h>
2
3DEFINE_SPINLOCK(imx_ccm_lock);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 1bf64fe2523c..5f2d8acca25f 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -3,7 +3,8 @@
3 3
4#include <linux/spinlock.h> 4#include <linux/spinlock.h>
5#include <linux/clk-provider.h> 5#include <linux/clk-provider.h>
6#include <mach/clock.h> 6
7extern spinlock_t imx_ccm_lock;
7 8
8struct clk *imx_clk_pllv1(const char *name, const char *parent, 9struct clk *imx_clk_pllv1(const char *name, const char *parent,
9 void __iomem *base); 10 void __iomem *base);
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
deleted file mode 100644
index 77e0db96c448..000000000000
--- a/arch/arm/mach-imx/devices-imx53.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <mach/mx53.h>
9#include <mach/devices-common.h>
10
11extern const struct imx_fec_data imx53_fec_data;
12#define imx53_add_fec(pdata) \
13 imx_add_fec(&imx53_fec_data, pdata)
14
15extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
16#define imx53_add_imx_uart(id, pdata) \
17 imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
18
19
20extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
21#define imx53_add_imx_i2c(id, pdata) \
22 imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
23
24extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
25#define imx53_add_sdhci_esdhc_imx(id, pdata) \
26 imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
27
28extern const struct imx_spi_imx_data imx53_ecspi_data[];
29#define imx53_add_ecspi(id, pdata) \
30 imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
31
32extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
33#define imx53_add_imx2_wdt(id) \
34 imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
35
36extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
37#define imx53_add_imx_ssi(id, pdata) \
38 imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
39
40extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
41#define imx53_add_imx_keypad(pdata) \
42 imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
43
44extern const struct imx_pata_imx_data imx53_pata_imx_data;
45#define imx53_add_pata_imx() \
46 imx_add_pata_imx(&imx53_pata_imx_data)
47
48extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h
deleted file mode 100644
index 014aa985faae..000000000000
--- a/arch/arm/mach-imx/efika.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef _EFIKA_H
2#define _EFIKA_H
3
4#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16)
5#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10)
6#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9)
7
8void __init efika_board_common_init(void);
9
10#endif
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index d4067fe36357..f233b4bb2342 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -13,7 +13,6 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/of_irq.h> 14#include <linux/of_irq.h>
15#include <linux/of_platform.h> 15#include <linux/of_platform.h>
16#include <linux/pinctrl/machine.h>
17#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
18#include <asm/mach/time.h> 17#include <asm/mach/time.h>
19#include <mach/common.h> 18#include <mach/common.h>
@@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
44 { /* sentinel */ } 43 { /* sentinel */ }
45}; 44};
46 45
47static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
48 { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
49 { /* sentinel */ }
50};
51
52static void __init imx51_dt_init(void) 46static void __init imx51_dt_init(void)
53{ 47{
54 struct device_node *node;
55 const struct of_device_id *of_id;
56 void (*func)(void);
57
58 pinctrl_provide_dummies();
59
60 node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
61 if (node) {
62 of_id = of_match_node(imx51_iomuxc_of_match, node);
63 func = of_id->data;
64 func();
65 of_node_put(node);
66 }
67
68 of_platform_populate(NULL, of_default_bus_match_table, 48 of_platform_populate(NULL, of_default_bus_match_table,
69 imx51_auxdata_lookup, NULL); 49 imx51_auxdata_lookup, NULL);
70} 50}
@@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = {
79}; 59};
80 60
81static const char *imx51_dt_board_compat[] __initdata = { 61static const char *imx51_dt_board_compat[] __initdata = {
82 "fsl,imx51-babbage",
83 "fsl,imx51", 62 "fsl,imx51",
84 NULL 63 NULL
85}; 64};
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/mach-imx53.c
index 1b7a2fc36591..29711e95579f 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -17,7 +17,6 @@
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/of_irq.h> 18#include <linux/of_irq.h>
19#include <linux/of_platform.h> 19#include <linux/of_platform.h>
20#include <linux/pinctrl/machine.h>
21#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
22#include <asm/mach/time.h> 21#include <asm/mach/time.h>
23#include <mach/common.h> 22#include <mach/common.h>
@@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
51 { /* sentinel */ } 50 { /* sentinel */ }
52}; 51};
53 52
54static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
55 { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
56 { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
57 { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
58 { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
59 { /* sentinel */ }
60};
61
62static void __init imx53_qsb_init(void) 53static void __init imx53_qsb_init(void)
63{ 54{
64 struct clk *clk; 55 struct clk *clk;
@@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void)
74 65
75static void __init imx53_dt_init(void) 66static void __init imx53_dt_init(void)
76{ 67{
77 struct device_node *node;
78 const struct of_device_id *of_id;
79 void (*func)(void);
80
81 pinctrl_provide_dummies();
82
83 node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
84 if (node) {
85 of_id = of_match_node(imx53_iomuxc_of_match, node);
86 func = of_id->data;
87 func();
88 of_node_put(node);
89 }
90
91 if (of_machine_is_compatible("fsl,imx53-qsb")) 68 if (of_machine_is_compatible("fsl,imx53-qsb"))
92 imx53_qsb_init(); 69 imx53_qsb_init();
93 70
@@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = {
105}; 82};
106 83
107static const char *imx53_dt_board_compat[] __initdata = { 84static const char *imx53_dt_board_compat[] __initdata = {
108 "fsl,imx53-ard",
109 "fsl,imx53-evk",
110 "fsl,imx53-qsb",
111 "fsl,imx53-smd",
112 "fsl,imx53", 85 "fsl,imx53",
113 NULL 86 NULL
114}; 87};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9591b4d6df12..36979d3dfe34 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -22,7 +22,6 @@
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/of_irq.h> 23#include <linux/of_irq.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/pinctrl/machine.h>
26#include <linux/phy.h> 25#include <linux/phy.h>
27#include <linux/micrel_phy.h> 26#include <linux/micrel_phy.h>
28#include <linux/mfd/anatop.h> 27#include <linux/mfd/anatop.h>
@@ -100,7 +99,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
100 clk_set_parent(cko1_sel, ahb); 99 clk_set_parent(cko1_sel, ahb);
101 rate = clk_round_rate(cko1, 16000000); 100 rate = clk_round_rate(cko1, 16000000);
102 clk_set_rate(cko1, rate); 101 clk_set_rate(cko1, rate);
103 clk_register_clkdev(cko1, NULL, "0-000a");
104put_clk: 102put_clk:
105 if (!IS_ERR(cko1_sel)) 103 if (!IS_ERR(cko1_sel))
106 clk_put(cko1_sel); 104 clk_put(cko1_sel);
@@ -159,12 +157,6 @@ static void __init imx6q_usb_init(void)
159 157
160static void __init imx6q_init_machine(void) 158static void __init imx6q_init_machine(void)
161{ 159{
162 /*
163 * This should be removed when all imx6q boards have pinctrl
164 * states for devices defined in device tree.
165 */
166 pinctrl_provide_dummies();
167
168 if (of_machine_is_compatible("fsl,imx6q-sabrelite")) 160 if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
169 imx6q_sabrelite_init(); 161 imx6q_sabrelite_init();
170 162
@@ -218,9 +210,6 @@ static struct sys_timer imx6q_timer = {
218}; 210};
219 211
220static const char *imx6q_dt_compat[] __initdata = { 212static const char *imx6q_dt_compat[] __initdata = {
221 "fsl,imx6q-arm2",
222 "fsl,imx6q-sabrelite",
223 "fsl,imx6q-sabresd",
224 "fsl,imx6q", 213 "fsl,imx6q",
225 NULL, 214 NULL,
226}; 215};
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 5d08533ab2c7..8dc9d3edf17a 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -36,7 +36,6 @@
36#include <asm/mach/map.h> 36#include <asm/mach/map.h>
37#include <asm/mach/time.h> 37#include <asm/mach/time.h>
38 38
39#include <mach/clock.h>
40#include <mach/common.h> 39#include <mach/common.h>
41#include <mach/hardware.h> 40#include <mach/hardware.h>
42#include <mach/iomux-mx3.h> 41#include <mach/iomux-mx3.h>
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
deleted file mode 100644
index 8d09c0126cab..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ /dev/null
@@ -1,300 +0,0 @@
1/*
2 * Copyright (C) 2010 Linaro Limited
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/spi/flash.h>
26#include <linux/spi/spi.h>
27#include <linux/mfd/mc13892.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/consumer.h>
30
31#include <mach/common.h>
32#include <mach/hardware.h>
33#include <mach/iomux-mx51.h>
34
35#include <asm/setup.h>
36#include <asm/system_info.h>
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40
41#include "devices-imx51.h"
42#include "efika.h"
43
44#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
45#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
46#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11)
47
48#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13)
49#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14)
50#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15)
51
52#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
53
54/* board 1.1 doesn't have same reset gpio */
55#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
56#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
57
58#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13)
59
60#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
61
62/* the pci ids pin have pull up. they're driven low according to board id */
63#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
64#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
65#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
66#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
67
68static iomux_v3_cfg_t mx51efikamx_pads[] = {
69 /* board id */
70 MX51_PAD_PCBID0,
71 MX51_PAD_PCBID1,
72 MX51_PAD_PCBID2,
73
74 /* leds */
75 MX51_PAD_CSI1_D9__GPIO3_13,
76 MX51_PAD_CSI1_VSYNC__GPIO3_14,
77 MX51_PAD_CSI1_HSYNC__GPIO3_15,
78
79 /* power key */
80 MX51_PAD_PWRKEY,
81
82 /* reset */
83 MX51_PAD_DI1_PIN13__GPIO3_2,
84 MX51_PAD_GPIO1_4__GPIO1_4,
85
86 /* power off */
87 MX51_PAD_CSI2_VSYNC__GPIO4_13,
88};
89
90/* PCBID2 PCBID1 PCBID0 STATE
91 1 1 1 ER1:rev1.1
92 1 1 0 ER2:rev1.2
93 1 0 1 ER3:rev1.3
94 1 0 0 ER4:rev1.4
95*/
96static void __init mx51_efikamx_board_id(void)
97{
98 int id;
99
100 /* things are taking time to settle */
101 msleep(150);
102
103 gpio_request(EFIKAMX_PCBID0, "pcbid0");
104 gpio_direction_input(EFIKAMX_PCBID0);
105 gpio_request(EFIKAMX_PCBID1, "pcbid1");
106 gpio_direction_input(EFIKAMX_PCBID1);
107 gpio_request(EFIKAMX_PCBID2, "pcbid2");
108 gpio_direction_input(EFIKAMX_PCBID2);
109
110 id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
111 id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
112 id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
113
114 switch (id) {
115 case 7:
116 system_rev = 0x11;
117 break;
118 case 6:
119 system_rev = 0x12;
120 break;
121 case 5:
122 system_rev = 0x13;
123 break;
124 case 4:
125 system_rev = 0x14;
126 break;
127 default:
128 system_rev = 0x10;
129 break;
130 }
131
132 if ((system_rev == 0x10)
133 || (system_rev == 0x12)
134 || (system_rev == 0x14)) {
135 printk(KERN_WARNING
136 "EfikaMX: Unsupported board revision 1.%u!\n",
137 system_rev & 0xf);
138 }
139}
140
141static struct gpio_led mx51_efikamx_leds[] __initdata = {
142 {
143 .name = "efikamx:green",
144 .default_trigger = "default-on",
145 .gpio = EFIKAMX_GREEN_LED,
146 },
147 {
148 .name = "efikamx:red",
149 .default_trigger = "ide-disk",
150 .gpio = EFIKAMX_RED_LED,
151 },
152 {
153 .name = "efikamx:blue",
154 .default_trigger = "mmc0",
155 .gpio = EFIKAMX_BLUE_LED,
156 },
157};
158
159static const struct gpio_led_platform_data
160 mx51_efikamx_leds_data __initconst = {
161 .leds = mx51_efikamx_leds,
162 .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
163};
164
165static struct esdhc_platform_data sd_pdata = {
166 .cd_type = ESDHC_CD_CONTROLLER,
167 .wp_type = ESDHC_WP_CONTROLLER,
168};
169
170static struct gpio_keys_button mx51_efikamx_powerkey[] = {
171 {
172 .code = KEY_POWER,
173 .gpio = EFIKAMX_POWER_KEY,
174 .type = EV_PWR,
175 .desc = "Power Button (CM)",
176 .wakeup = 1,
177 .debounce_interval = 10, /* ms */
178 },
179};
180
181static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
182 .buttons = mx51_efikamx_powerkey,
183 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
184};
185
186static void mx51_efikamx_restart(char mode, const char *cmd)
187{
188 if (system_rev == 0x11)
189 gpio_direction_output(EFIKAMX_RESET1_1, 0);
190 else
191 gpio_direction_output(EFIKAMX_RESET, 0);
192}
193
194static struct regulator *pwgt1, *pwgt2, *coincell;
195
196static void mx51_efikamx_power_off(void)
197{
198 if (!IS_ERR(coincell))
199 regulator_disable(coincell);
200
201 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
202 regulator_disable(pwgt2);
203 regulator_disable(pwgt1);
204 }
205 gpio_direction_output(EFIKAMX_POWEROFF, 1);
206}
207
208static int __init mx51_efikamx_power_init(void)
209{
210 pwgt1 = regulator_get(NULL, "pwgt1");
211 pwgt2 = regulator_get(NULL, "pwgt2");
212 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
213 regulator_enable(pwgt1);
214 regulator_enable(pwgt2);
215 }
216 gpio_request(EFIKAMX_POWEROFF, "poweroff");
217 pm_power_off = mx51_efikamx_power_off;
218
219 /* enable coincell charger. maybe need a small power driver ? */
220 coincell = regulator_get(NULL, "coincell");
221 if (!IS_ERR(coincell)) {
222 regulator_set_voltage(coincell, 3000000, 3000000);
223 regulator_enable(coincell);
224 }
225
226 regulator_has_full_constraints();
227
228 return 0;
229}
230
231static void __init mx51_efikamx_init_late(void)
232{
233 imx51_init_late();
234 mx51_efikamx_power_init();
235}
236
237static void __init mx51_efikamx_init(void)
238{
239 imx51_soc_init();
240
241 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
242 ARRAY_SIZE(mx51efikamx_pads));
243 efika_board_common_init();
244
245 mx51_efikamx_board_id();
246
247 /* on < 1.2 boards both SD controllers are used */
248 if (system_rev < 0x12) {
249 imx51_add_sdhci_esdhc_imx(0, NULL);
250 imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
251 mx51_efikamx_leds[2].default_trigger = "mmc1";
252 } else
253 imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
254
255 gpio_led_register_device(-1, &mx51_efikamx_leds_data);
256 imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
257
258 if (system_rev == 0x11) {
259 gpio_request(EFIKAMX_RESET1_1, "reset");
260 gpio_direction_output(EFIKAMX_RESET1_1, 1);
261 } else {
262 gpio_request(EFIKAMX_RESET, "reset");
263 gpio_direction_output(EFIKAMX_RESET, 1);
264 }
265
266 /*
267 * enable wifi by default only on mx
268 * sb and mx have same wlan pin but the value to enable it are
269 * different :/
270 */
271 gpio_request(EFIKA_WLAN_EN, "wlan_en");
272 gpio_direction_output(EFIKA_WLAN_EN, 0);
273 msleep(10);
274
275 gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
276 gpio_direction_output(EFIKA_WLAN_RESET, 0);
277 msleep(10);
278 gpio_set_value(EFIKA_WLAN_RESET, 1);
279}
280
281static void __init mx51_efikamx_timer_init(void)
282{
283 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
284}
285
286static struct sys_timer mx51_efikamx_timer = {
287 .init = mx51_efikamx_timer_init,
288};
289
290MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
291 .atag_offset = 0x100,
292 .map_io = mx51_map_io,
293 .init_early = imx51_init_early,
294 .init_irq = mx51_init_irq,
295 .handle_irq = imx51_handle_irq,
296 .timer = &mx51_efikamx_timer,
297 .init_machine = mx51_efikamx_init,
298 .init_late = mx51_efikamx_init_late,
299 .restart = mx51_efikamx_restart,
300MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
deleted file mode 100644
index fdbd181b97ef..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/spi/flash.h>
26#include <linux/spi/spi.h>
27#include <linux/mfd/mc13892.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/consumer.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h>
32#include <mach/ulpi.h>
33
34#include <mach/common.h>
35#include <mach/hardware.h>
36#include <mach/iomux-mx51.h>
37
38#include <asm/setup.h>
39#include <asm/system_info.h>
40#include <asm/mach-types.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/time.h>
43
44#include "devices-imx51.h"
45#include "efika.h"
46
47#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20)
48#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3)
49#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25)
50#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28)
51#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29)
52#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31)
53#define EFIKASB_LID IMX_GPIO_NR(3, 14)
54#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13)
55#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1)
56
57#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
58#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
59
60static iomux_v3_cfg_t mx51efikasb_pads[] = {
61 /* USB HOST2 */
62 MX51_PAD_EIM_D16__USBH2_DATA0,
63 MX51_PAD_EIM_D17__USBH2_DATA1,
64 MX51_PAD_EIM_D18__USBH2_DATA2,
65 MX51_PAD_EIM_D19__USBH2_DATA3,
66 MX51_PAD_EIM_D20__USBH2_DATA4,
67 MX51_PAD_EIM_D21__USBH2_DATA5,
68 MX51_PAD_EIM_D22__USBH2_DATA6,
69 MX51_PAD_EIM_D23__USBH2_DATA7,
70 MX51_PAD_EIM_A24__USBH2_CLK,
71 MX51_PAD_EIM_A25__USBH2_DIR,
72 MX51_PAD_EIM_A26__USBH2_STP,
73 MX51_PAD_EIM_A27__USBH2_NXT,
74
75 /* leds */
76 MX51_PAD_EIM_CS0__GPIO2_25,
77 MX51_PAD_GPIO1_3__GPIO1_3,
78
79 /* pcb id */
80 MX51_PAD_EIM_CS3__GPIO2_28,
81 MX51_PAD_EIM_CS4__GPIO2_29,
82
83 /* lid */
84 MX51_PAD_CSI1_VSYNC__GPIO3_14,
85
86 /* power key*/
87 MX51_PAD_PWRKEY,
88
89 /* wifi/bt button */
90 MX51_PAD_DI1_PIN12__GPIO3_1,
91
92 /* power off */
93 MX51_PAD_CSI2_VSYNC__GPIO4_13,
94
95 /* wdog reset */
96 MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
97
98 /* BT */
99 MX51_PAD_EIM_A17__GPIO2_11,
100
101 MX51_PAD_SD1_CD,
102};
103
104static int initialize_usbh2_port(struct platform_device *pdev)
105{
106 iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
107 iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
108
109 mxc_iomux_v3_setup_pad(usbh2gpio);
110 gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
111 gpio_direction_output(EFIKASB_USBH2_STP, 0);
112 msleep(1);
113 gpio_set_value(EFIKASB_USBH2_STP, 1);
114 msleep(1);
115
116 gpio_free(EFIKASB_USBH2_STP);
117 mxc_iomux_v3_setup_pad(usbh2stp);
118
119 mdelay(10);
120
121 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
122}
123
124static struct mxc_usbh_platform_data usbh2_config __initdata = {
125 .init = initialize_usbh2_port,
126 .portsc = MXC_EHCI_MODE_ULPI,
127};
128
129static void __init mx51_efikasb_usb(void)
130{
131 usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
132 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
133 if (usbh2_config.otg)
134 imx51_add_mxc_ehci_hs(2, &usbh2_config);
135}
136
137static const struct gpio_led mx51_efikasb_leds[] __initconst = {
138 {
139 .name = "efikasb:green",
140 .default_trigger = "default-on",
141 .gpio = EFIKASB_GREEN_LED,
142 .active_low = 1,
143 },
144 {
145 .name = "efikasb:white",
146 .default_trigger = "caps",
147 .gpio = EFIKASB_WHITE_LED,
148 },
149};
150
151static const struct gpio_led_platform_data
152 mx51_efikasb_leds_data __initconst = {
153 .leds = mx51_efikasb_leds,
154 .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
155};
156
157static struct gpio_keys_button mx51_efikasb_keys[] = {
158 {
159 .code = KEY_POWER,
160 .gpio = EFIKASB_PWRKEY,
161 .type = EV_KEY,
162 .desc = "Power Button",
163 .wakeup = 1,
164 .active_low = 1,
165 },
166 {
167 .code = SW_LID,
168 .gpio = EFIKASB_LID,
169 .type = EV_SW,
170 .desc = "Lid Switch",
171 .active_low = 1,
172 },
173 {
174 .code = KEY_RFKILL,
175 .gpio = EFIKASB_RFKILL,
176 .type = EV_KEY,
177 .desc = "rfkill",
178 .active_low = 1,
179 },
180};
181
182static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
183 .buttons = mx51_efikasb_keys,
184 .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
185};
186
187static struct esdhc_platform_data sd0_pdata = {
188#define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27)
189 .cd_gpio = EFIKASB_SD1_CD,
190 .cd_type = ESDHC_CD_GPIO,
191 .wp_type = ESDHC_WP_CONTROLLER,
192};
193
194static struct esdhc_platform_data sd1_pdata = {
195 .cd_type = ESDHC_CD_CONTROLLER,
196 .wp_type = ESDHC_WP_CONTROLLER,
197};
198
199static struct regulator *pwgt1, *pwgt2;
200
201static void mx51_efikasb_power_off(void)
202{
203 gpio_set_value(EFIKA_USB_PHY_RESET, 0);
204
205 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
206 regulator_disable(pwgt2);
207 regulator_disable(pwgt1);
208 }
209 gpio_direction_output(EFIKASB_POWEROFF, 1);
210}
211
212static int __init mx51_efikasb_power_init(void)
213{
214 pwgt1 = regulator_get(NULL, "pwgt1");
215 pwgt2 = regulator_get(NULL, "pwgt2");
216 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
217 regulator_enable(pwgt1);
218 regulator_enable(pwgt2);
219 }
220 gpio_request(EFIKASB_POWEROFF, "poweroff");
221 pm_power_off = mx51_efikasb_power_off;
222
223 regulator_has_full_constraints();
224
225 return 0;
226}
227
228static void __init mx51_efikasb_init_late(void)
229{
230 imx51_init_late();
231 mx51_efikasb_power_init();
232}
233
234/* 01 R1.3 board
235 10 R2.0 board */
236static void __init mx51_efikasb_board_id(void)
237{
238 int id;
239
240 gpio_request(EFIKASB_PCBID0, "pcb id0");
241 gpio_direction_input(EFIKASB_PCBID0);
242 gpio_request(EFIKASB_PCBID1, "pcb id1");
243 gpio_direction_input(EFIKASB_PCBID1);
244
245 id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
246 id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
247
248 switch (id) {
249 default:
250 break;
251 case 1:
252 system_rev = 0x13;
253 break;
254 case 2:
255 system_rev = 0x20;
256 break;
257 }
258}
259
260static void __init efikasb_board_init(void)
261{
262 imx51_soc_init();
263
264 mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
265 ARRAY_SIZE(mx51efikasb_pads));
266 efika_board_common_init();
267
268 mx51_efikasb_board_id();
269 mx51_efikasb_usb();
270 imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
271 imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
272
273 gpio_led_register_device(-1, &mx51_efikasb_leds_data);
274 imx_add_gpio_keys(&mx51_efikasb_keys_data);
275}
276
277static void __init mx51_efikasb_timer_init(void)
278{
279 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
280}
281
282static struct sys_timer mx51_efikasb_timer = {
283 .init = mx51_efikasb_timer_init,
284};
285
286MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
287 .atag_offset = 0x100,
288 .map_io = mx51_map_io,
289 .init_early = imx51_init_early,
290 .init_irq = mx51_init_irq,
291 .handle_irq = imx51_handle_irq,
292 .init_machine = efikasb_board_init,
293 .init_late = mx51_efikasb_init_late,
294 .timer = &mx51_efikasb_timer,
295 .restart = mxc_restart,
296MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
deleted file mode 100644
index 6c28e65f424d..000000000000
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ /dev/null
@@ -1,272 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/smsc911x.h>
26#include <linux/regulator/machine.h>
27#include <linux/regulator/fixed.h>
28
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx53.h>
32
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36
37#include "devices-imx53.h"
38
39#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
40#define ARD_SD1_CD IMX_GPIO_NR(1, 1)
41#define ARD_SD1_WP IMX_GPIO_NR(1, 9)
42#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3)
43#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0)
44#define ARD_HOME IMX_GPIO_NR(5, 10)
45#define ARD_BACK IMX_GPIO_NR(5, 11)
46#define ARD_PROG IMX_GPIO_NR(5, 12)
47#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13)
48
49static iomux_v3_cfg_t mx53_ard_pads[] = {
50 /* UART1 */
51 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
52 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
53 /* WEIM for CS1 */
54 MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
55 MX53_PAD_EIM_D16__EMI_WEIM_D_16,
56 MX53_PAD_EIM_D17__EMI_WEIM_D_17,
57 MX53_PAD_EIM_D18__EMI_WEIM_D_18,
58 MX53_PAD_EIM_D19__EMI_WEIM_D_19,
59 MX53_PAD_EIM_D20__EMI_WEIM_D_20,
60 MX53_PAD_EIM_D21__EMI_WEIM_D_21,
61 MX53_PAD_EIM_D22__EMI_WEIM_D_22,
62 MX53_PAD_EIM_D23__EMI_WEIM_D_23,
63 MX53_PAD_EIM_D24__EMI_WEIM_D_24,
64 MX53_PAD_EIM_D25__EMI_WEIM_D_25,
65 MX53_PAD_EIM_D26__EMI_WEIM_D_26,
66 MX53_PAD_EIM_D27__EMI_WEIM_D_27,
67 MX53_PAD_EIM_D28__EMI_WEIM_D_28,
68 MX53_PAD_EIM_D29__EMI_WEIM_D_29,
69 MX53_PAD_EIM_D30__EMI_WEIM_D_30,
70 MX53_PAD_EIM_D31__EMI_WEIM_D_31,
71 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
72 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
73 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
74 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
75 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
76 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
77 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
78 MX53_PAD_EIM_OE__EMI_WEIM_OE,
79 MX53_PAD_EIM_RW__EMI_WEIM_RW,
80 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
81 /* SDHC1 */
82 MX53_PAD_SD1_CMD__ESDHC1_CMD,
83 MX53_PAD_SD1_CLK__ESDHC1_CLK,
84 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
85 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
86 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
87 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
88 MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
89 MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
90 MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
91 MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
92 MX53_PAD_GPIO_1__GPIO1_1,
93 MX53_PAD_GPIO_9__GPIO1_9,
94 /* I2C2 */
95 MX53_PAD_EIM_EB2__I2C2_SCL,
96 MX53_PAD_KEY_ROW3__I2C2_SDA,
97 /* I2C3 */
98 MX53_PAD_GPIO_3__I2C3_SCL,
99 MX53_PAD_GPIO_16__I2C3_SDA,
100 /* GPIO */
101 MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
102 MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
103 MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
104 MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
105 MX53_PAD_GPIO_10__GPIO4_0, /* vol down */
106};
107
108#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
109{ \
110 .gpio = gpio_num, \
111 .type = EV_KEY, \
112 .code = ev_code, \
113 .active_low = act_low, \
114 .desc = "btn " descr, \
115 .wakeup = wake, \
116}
117
118static struct gpio_keys_button ard_buttons[] = {
119 GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
120 GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
121 GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
122 GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
123 GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
124};
125
126static const struct gpio_keys_platform_data ard_button_data __initconst = {
127 .buttons = ard_buttons,
128 .nbuttons = ARRAY_SIZE(ard_buttons),
129};
130
131static struct resource ard_smsc911x_resources[] = {
132 {
133 .start = MX53_CS1_64MB_BASE_ADDR,
134 .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
135 .flags = IORESOURCE_MEM,
136 },
137 {
138 /* irq number is run-time assigned */
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143struct smsc911x_platform_config ard_smsc911x_config = {
144 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
145 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
146 .flags = SMSC911X_USE_32BIT,
147};
148
149static struct platform_device ard_smsc_lan9220_device = {
150 .name = "smsc911x",
151 .id = -1,
152 .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
153 .resource = ard_smsc911x_resources,
154 .dev = {
155 .platform_data = &ard_smsc911x_config,
156 },
157};
158
159static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
160 .cd_gpio = ARD_SD1_CD,
161 .wp_gpio = ARD_SD1_WP,
162};
163
164static struct imxi2c_platform_data mx53_ard_i2c2_data = {
165 .bitrate = 50000,
166};
167
168static struct imxi2c_platform_data mx53_ard_i2c3_data = {
169 .bitrate = 400000,
170};
171
172static void __init mx53_ard_io_init(void)
173{
174 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
175 gpio_direction_input(ARD_ETHERNET_INT_B);
176
177 gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
178 gpio_direction_output(ARD_I2CPORTEXP_B, 1);
179}
180
181/* Config CS1 settings for ethernet controller */
182static int weim_cs_config(void)
183{
184 u32 reg;
185 void __iomem *weim_base, *iomuxc_base;
186
187 weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
188 if (!weim_base)
189 return -ENOMEM;
190
191 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
192 if (!iomuxc_base) {
193 iounmap(weim_base);
194 return -ENOMEM;
195 }
196
197 /* CS1 timings for LAN9220 */
198 writel(0x20001, (weim_base + 0x18));
199 writel(0x0, (weim_base + 0x1C));
200 writel(0x16000202, (weim_base + 0x20));
201 writel(0x00000002, (weim_base + 0x24));
202 writel(0x16002082, (weim_base + 0x28));
203 writel(0x00000000, (weim_base + 0x2C));
204 writel(0x00000000, (weim_base + 0x90));
205
206 /* specify 64 MB on CS1 and CS0 on GPR1 */
207 reg = readl(iomuxc_base + 0x4);
208 reg &= ~0x3F;
209 reg |= 0x1B;
210 writel(reg, (iomuxc_base + 0x4));
211
212 iounmap(iomuxc_base);
213 iounmap(weim_base);
214
215 return 0;
216}
217
218static struct regulator_consumer_supply dummy_supplies[] = {
219 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
220 REGULATOR_SUPPLY("vddvario", "smsc911x"),
221};
222
223void __init imx53_ard_common_init(void)
224{
225 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
226 ARRAY_SIZE(mx53_ard_pads));
227 weim_cs_config();
228}
229
230static struct platform_device *devices[] __initdata = {
231 &ard_smsc_lan9220_device,
232};
233
234static void __init mx53_ard_board_init(void)
235{
236 imx53_soc_init();
237 imx53_add_imx_uart(0, NULL);
238
239 imx53_ard_common_init();
240 mx53_ard_io_init();
241 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
242 ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
243 ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
244 platform_add_devices(devices, ARRAY_SIZE(devices));
245
246 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
247 imx53_add_imx2_wdt(0);
248 imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
249 imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
250 imx_add_gpio_keys(&ard_button_data);
251 imx53_add_ahci_imx();
252}
253
254static void __init mx53_ard_timer_init(void)
255{
256 mx53_clocks_init(32768, 24000000, 22579200, 0);
257}
258
259static struct sys_timer mx53_ard_timer = {
260 .init = mx53_ard_timer_init,
261};
262
263MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
264 .map_io = mx53_map_io,
265 .init_early = imx53_init_early,
266 .init_irq = mx53_init_irq,
267 .handle_irq = imx53_handle_irq,
268 .timer = &mx53_ard_timer,
269 .init_machine = mx53_ard_board_init,
270 .init_late = imx53_init_late,
271 .restart = mxc_restart,
272MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
deleted file mode 100644
index 09fe2197b491..000000000000
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include <linux/init.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/gpio.h>
26#include <linux/spi/flash.h>
27#include <linux/spi/spi.h>
28#include <mach/common.h>
29#include <mach/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <mach/iomux-mx53.h>
34
35#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
36#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
37#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
38#define MX53EVK_LED IMX_GPIO_NR(7, 7)
39
40#include "devices-imx53.h"
41
42static iomux_v3_cfg_t mx53_evk_pads[] = {
43 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
44 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
45
46 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
47 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
48 MX53_PAD_PATA_DIOR__UART2_RTS,
49 MX53_PAD_PATA_INTRQ__UART2_CTS,
50
51 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
52 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
53
54 MX53_PAD_EIM_D16__ECSPI1_SCLK,
55 MX53_PAD_EIM_D17__ECSPI1_MISO,
56 MX53_PAD_EIM_D18__ECSPI1_MOSI,
57
58 /* ecspi chip select lines */
59 MX53_PAD_EIM_EB2__GPIO2_30,
60 MX53_PAD_EIM_D19__GPIO3_19,
61 /* LED */
62 MX53_PAD_PATA_DA_1__GPIO7_7,
63};
64
65static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
66 .flags = IMXUART_HAVE_RTSCTS,
67};
68
69static const struct gpio_led mx53evk_leds[] __initconst = {
70 {
71 .name = "green",
72 .default_trigger = "heartbeat",
73 .gpio = MX53EVK_LED,
74 },
75};
76
77static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
78 .leds = mx53evk_leds,
79 .num_leds = ARRAY_SIZE(mx53evk_leds),
80};
81
82static inline void mx53_evk_init_uart(void)
83{
84 imx53_add_imx_uart(0, NULL);
85 imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
86 imx53_add_imx_uart(2, NULL);
87}
88
89static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
90 .bitrate = 100000,
91};
92
93static inline void mx53_evk_fec_reset(void)
94{
95 int ret;
96
97 /* reset FEC PHY */
98 ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
99 "fec-phy-reset");
100 if (ret) {
101 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
102 return;
103 }
104 msleep(1);
105 gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
106}
107
108static const struct fec_platform_data mx53_evk_fec_pdata __initconst = {
109 .phy = PHY_INTERFACE_MODE_RMII,
110};
111
112static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
113 {
114 .modalias = "mtd_dataflash",
115 .max_speed_hz = 25000000,
116 .bus_num = 0,
117 .chip_select = 1,
118 .mode = SPI_MODE_0,
119 .platform_data = NULL,
120 },
121};
122
123static int mx53_evk_spi_cs[] = {
124 EVK_ECSPI1_CS0,
125 EVK_ECSPI1_CS1,
126};
127
128static const struct spi_imx_master mx53_evk_spi_data __initconst = {
129 .chipselect = mx53_evk_spi_cs,
130 .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
131};
132
133void __init imx53_evk_common_init(void)
134{
135 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
136 ARRAY_SIZE(mx53_evk_pads));
137}
138
139static void __init mx53_evk_board_init(void)
140{
141 imx53_soc_init();
142 imx53_evk_common_init();
143
144 mx53_evk_init_uart();
145 mx53_evk_fec_reset();
146 imx53_add_fec(&mx53_evk_fec_pdata);
147
148 imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
149 imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
150
151 imx53_add_sdhci_esdhc_imx(0, NULL);
152 imx53_add_sdhci_esdhc_imx(1, NULL);
153
154 spi_register_board_info(mx53_evk_spi_board_info,
155 ARRAY_SIZE(mx53_evk_spi_board_info));
156 imx53_add_ecspi(0, &mx53_evk_spi_data);
157 imx53_add_imx2_wdt(0);
158 gpio_led_register_device(-1, &mx53evk_leds_data);
159}
160
161static void __init mx53_evk_timer_init(void)
162{
163 mx53_clocks_init(32768, 24000000, 22579200, 0);
164}
165
166static struct sys_timer mx53_evk_timer = {
167 .init = mx53_evk_timer_init,
168};
169
170MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
171 .map_io = mx53_map_io,
172 .init_early = imx53_init_early,
173 .init_irq = mx53_init_irq,
174 .handle_irq = imx53_handle_irq,
175 .timer = &mx53_evk_timer,
176 .init_machine = mx53_evk_board_init,
177 .init_late = imx53_init_late,
178 .restart = mxc_restart,
179MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
deleted file mode 100644
index 8abe23c1d3c8..000000000000
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ /dev/null
@@ -1,321 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/i2c.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-mx53.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/time.h>
34
35#include "devices-imx53.h"
36
37#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
38#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
39#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
40#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
41#define LOCO_LED IMX_GPIO_NR(7, 7)
42#define LOCO_SD3_CD IMX_GPIO_NR(3, 11)
43#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
44#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
45#define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14)
46
47static iomux_v3_cfg_t mx53_loco_pads[] = {
48 /* FEC */
49 MX53_PAD_FEC_MDC__FEC_MDC,
50 MX53_PAD_FEC_MDIO__FEC_MDIO,
51 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
52 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
53 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
54 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
55 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
56 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
57 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
58 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
59 /* FEC_nRST */
60 MX53_PAD_PATA_DA_0__GPIO7_6,
61 /* FEC_nINT */
62 MX53_PAD_PATA_DATA4__GPIO2_4,
63 /* AUDMUX5 */
64 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
65 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
66 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
67 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
68 /* I2C1 */
69 MX53_PAD_CSI0_DAT8__I2C1_SDA,
70 MX53_PAD_CSI0_DAT9__I2C1_SCL,
71 MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */
72 /* I2C2 */
73 MX53_PAD_KEY_COL3__I2C2_SCL,
74 MX53_PAD_KEY_ROW3__I2C2_SDA,
75 /* SD1 */
76 MX53_PAD_SD1_CMD__ESDHC1_CMD,
77 MX53_PAD_SD1_CLK__ESDHC1_CLK,
78 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
79 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
80 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
81 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
82 /* SD1_CD */
83 MX53_PAD_EIM_DA13__GPIO3_13,
84 /* SD3 */
85 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
86 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
87 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
88 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
89 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
90 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
91 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
92 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
93 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
94 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
95 /* SD3_CD */
96 MX53_PAD_EIM_DA11__GPIO3_11,
97 /* SD3_WP */
98 MX53_PAD_EIM_DA12__GPIO3_12,
99 /* VGA */
100 MX53_PAD_EIM_OE__IPU_DI1_PIN7,
101 MX53_PAD_EIM_RW__IPU_DI1_PIN8,
102 /* DISPLB */
103 MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
104 MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
105 MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
106 MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
107 /* DISP0_POWER_EN */
108 MX53_PAD_EIM_D24__GPIO3_24,
109 /* DISP0 DET INT */
110 MX53_PAD_EIM_D31__GPIO3_31,
111 /* LVDS */
112 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
113 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
114 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
115 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
116 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
117 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
118 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
119 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
120 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
121 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
122 /* I2C1 */
123 MX53_PAD_CSI0_DAT8__I2C1_SDA,
124 MX53_PAD_CSI0_DAT9__I2C1_SCL,
125 /* UART1 */
126 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
127 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
128 /* CSI0 */
129 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
130 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
131 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
132 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
133 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
134 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
135 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
136 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
137 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
138 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
139 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
140 /* DISPLAY */
141 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
142 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
143 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
144 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
145 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
146 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
147 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
148 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
149 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
150 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
151 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
152 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
153 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
154 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
155 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
156 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
157 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
158 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
159 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
160 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
161 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
162 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
163 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
164 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
165 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
166 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
167 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
168 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
169 /* Audio CLK*/
170 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
171 /* PWM */
172 MX53_PAD_GPIO_1__PWM2_PWMO,
173 /* SPDIF */
174 MX53_PAD_GPIO_7__SPDIF_PLOCK,
175 MX53_PAD_GPIO_17__SPDIF_OUT1,
176 /* GPIO */
177 MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */
178 MX53_PAD_PATA_DA_2__GPIO7_8,
179 MX53_PAD_PATA_DATA5__GPIO2_5,
180 MX53_PAD_PATA_DATA6__GPIO2_6,
181 MX53_PAD_PATA_DATA14__GPIO2_14,
182 MX53_PAD_PATA_DATA15__GPIO2_15,
183 MX53_PAD_PATA_INTRQ__GPIO7_2,
184 MX53_PAD_EIM_WAIT__GPIO5_0,
185 MX53_PAD_NANDF_WP_B__GPIO6_9,
186 MX53_PAD_NANDF_RB0__GPIO6_10,
187 MX53_PAD_NANDF_CS1__GPIO6_14,
188 MX53_PAD_NANDF_CS2__GPIO6_15,
189 MX53_PAD_NANDF_CS3__GPIO6_16,
190 MX53_PAD_GPIO_5__GPIO1_5,
191 MX53_PAD_GPIO_16__GPIO7_11,
192 MX53_PAD_GPIO_8__GPIO1_8,
193};
194
195#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
196{ \
197 .gpio = gpio_num, \
198 .type = EV_KEY, \
199 .code = ev_code, \
200 .active_low = act_low, \
201 .desc = "btn " descr, \
202 .wakeup = wake, \
203}
204
205static struct gpio_keys_button loco_buttons[] = {
206 GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
207 GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
208 GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
209};
210
211static const struct gpio_keys_platform_data loco_button_data __initconst = {
212 .buttons = loco_buttons,
213 .nbuttons = ARRAY_SIZE(loco_buttons),
214};
215
216static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
217 .cd_gpio = LOCO_SD1_CD,
218 .cd_type = ESDHC_CD_GPIO,
219 .wp_type = ESDHC_WP_NONE,
220};
221
222static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
223 .cd_gpio = LOCO_SD3_CD,
224 .wp_gpio = LOCO_SD3_WP,
225 .cd_type = ESDHC_CD_GPIO,
226 .wp_type = ESDHC_WP_GPIO,
227};
228
229static inline void mx53_loco_fec_reset(void)
230{
231 int ret;
232
233 /* reset FEC PHY */
234 ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
235 if (ret) {
236 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
237 return;
238 }
239 gpio_direction_output(LOCO_FEC_PHY_RST, 0);
240 msleep(1);
241 gpio_set_value(LOCO_FEC_PHY_RST, 1);
242}
243
244static const struct fec_platform_data mx53_loco_fec_data __initconst = {
245 .phy = PHY_INTERFACE_MODE_RMII,
246};
247
248static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
249 .bitrate = 100000,
250};
251
252static const struct gpio_led mx53loco_leds[] __initconst = {
253 {
254 .name = "green",
255 .default_trigger = "heartbeat",
256 .gpio = LOCO_LED,
257 },
258};
259
260static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
261 .leds = mx53loco_leds,
262 .num_leds = ARRAY_SIZE(mx53loco_leds),
263};
264
265void __init imx53_qsb_common_init(void)
266{
267 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
268 ARRAY_SIZE(mx53_loco_pads));
269}
270
271static struct i2c_board_info mx53loco_i2c_devices[] = {
272 {
273 I2C_BOARD_INFO("mma8450", 0x1C),
274 },
275};
276
277static void __init mx53_loco_board_init(void)
278{
279 int ret;
280 imx53_soc_init();
281 imx53_qsb_common_init();
282
283 imx53_add_imx_uart(0, NULL);
284 mx53_loco_fec_reset();
285 imx53_add_fec(&mx53_loco_fec_data);
286 imx53_add_imx2_wdt(0);
287
288 ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
289 if (ret)
290 pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
291
292 i2c_register_board_info(0, mx53loco_i2c_devices,
293 ARRAY_SIZE(mx53loco_i2c_devices));
294 imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
295 imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
296 imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
297 imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
298 imx_add_gpio_keys(&loco_button_data);
299 gpio_led_register_device(-1, &mx53loco_leds_data);
300 imx53_add_ahci_imx();
301}
302
303static void __init mx53_loco_timer_init(void)
304{
305 mx53_clocks_init(32768, 24000000, 0, 0);
306}
307
308static struct sys_timer mx53_loco_timer = {
309 .init = mx53_loco_timer_init,
310};
311
312MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
313 .map_io = mx53_map_io,
314 .init_early = imx53_init_early,
315 .init_irq = mx53_init_irq,
316 .handle_irq = imx53_handle_irq,
317 .timer = &mx53_loco_timer,
318 .init_machine = mx53_loco_board_init,
319 .init_late = imx53_init_late,
320 .restart = mxc_restart,
321MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
deleted file mode 100644
index b15d6a6d3b68..000000000000
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ /dev/null
@@ -1,168 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/gpio.h>
25
26#include <mach/common.h>
27#include <mach/hardware.h>
28#include <mach/iomux-mx53.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33
34#include "devices-imx53.h"
35
36#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
37#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3)
38
39static iomux_v3_cfg_t mx53_smd_pads[] = {
40 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
41 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
42
43 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
44 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
45
46 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
47 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
48 MX53_PAD_PATA_DA_1__UART3_CTS,
49 MX53_PAD_PATA_DA_2__UART3_RTS,
50 /* I2C1 */
51 MX53_PAD_CSI0_DAT8__I2C1_SDA,
52 MX53_PAD_CSI0_DAT9__I2C1_SCL,
53 /* SD1 */
54 MX53_PAD_SD1_CMD__ESDHC1_CMD,
55 MX53_PAD_SD1_CLK__ESDHC1_CLK,
56 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
57 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
58 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
59 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
60 /* SD2 */
61 MX53_PAD_SD2_CMD__ESDHC2_CMD,
62 MX53_PAD_SD2_CLK__ESDHC2_CLK,
63 MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
64 MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
65 MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
66 MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
67 /* SD3 */
68 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
69 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
70 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
71 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
72 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
73 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
74 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
75 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
76 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
77 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
78};
79
80static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
81 .flags = IMXUART_HAVE_RTSCTS,
82};
83
84static inline void mx53_smd_init_uart(void)
85{
86 imx53_add_imx_uart(0, NULL);
87 imx53_add_imx_uart(1, NULL);
88 imx53_add_imx_uart(2, &mx53_smd_uart_data);
89}
90
91static inline void mx53_smd_fec_reset(void)
92{
93 int ret;
94
95 /* reset FEC PHY */
96 ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
97 if (ret) {
98 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
99 return;
100 }
101 gpio_direction_output(SMD_FEC_PHY_RST, 0);
102 msleep(1);
103 gpio_set_value(SMD_FEC_PHY_RST, 1);
104}
105
106static const struct fec_platform_data mx53_smd_fec_data __initconst = {
107 .phy = PHY_INTERFACE_MODE_RMII,
108};
109
110static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
111 .bitrate = 100000,
112};
113
114static inline void mx53_smd_ahci_pwr_on(void)
115{
116 int ret;
117
118 /* Enable SATA PWR */
119 ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
120 GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
121 if (ret) {
122 pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
123 return;
124 }
125}
126
127void __init imx53_smd_common_init(void)
128{
129 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
130 ARRAY_SIZE(mx53_smd_pads));
131}
132
133static void __init mx53_smd_board_init(void)
134{
135 imx53_soc_init();
136 imx53_smd_common_init();
137
138 mx53_smd_init_uart();
139 mx53_smd_fec_reset();
140 imx53_add_fec(&mx53_smd_fec_data);
141 imx53_add_imx2_wdt(0);
142 imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
143 imx53_add_sdhci_esdhc_imx(0, NULL);
144 imx53_add_sdhci_esdhc_imx(1, NULL);
145 imx53_add_sdhci_esdhc_imx(2, NULL);
146 mx53_smd_ahci_pwr_on();
147 imx53_add_ahci_imx();
148}
149
150static void __init mx53_smd_timer_init(void)
151{
152 mx53_clocks_init(32768, 24000000, 22579200, 0);
153}
154
155static struct sys_timer mx53_smd_timer = {
156 .init = mx53_smd_timer_init,
157};
158
159MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
160 .map_io = mx53_map_io,
161 .init_early = imx53_init_early,
162 .init_irq = mx53_init_irq,
163 .handle_irq = imx53_handle_irq,
164 .timer = &mx53_smd_timer,
165 .init_machine = mx53_smd_board_init,
166 .init_late = imx53_init_late,
167 .restart = mxc_restart,
168MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 52d8f534be10..acb0aadb4255 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
128 .script_addrs = &imx51_sdma_script, 128 .script_addrs = &imx51_sdma_script,
129}; 129};
130 130
131static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
132 .ap_2_ap_addr = 642,
133 .app_2_mcu_addr = 683,
134 .mcu_2_app_addr = 747,
135 .uart_2_mcu_addr = 817,
136 .shp_2_mcu_addr = 891,
137 .mcu_2_shp_addr = 960,
138 .uartsh_2_mcu_addr = 1032,
139 .spdif_2_mcu_addr = 1100,
140 .mcu_2_spdif_addr = 1134,
141 .firi_2_mcu_addr = 1193,
142 .mcu_2_firi_addr = 1290,
143};
144
145static struct sdma_platform_data imx53_sdma_pdata __initdata = {
146 .fw_name = "sdma-imx53.bin",
147 .script_addrs = &imx53_sdma_script,
148};
149
150static const struct resource imx50_audmux_res[] __initconst = { 131static const struct resource imx50_audmux_res[] __initconst = {
151 DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), 132 DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
152}; 133};
@@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = {
155 DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), 136 DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
156}; 137};
157 138
158static const struct resource imx53_audmux_res[] __initconst = {
159 DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
160};
161
162void __init imx50_soc_init(void) 139void __init imx50_soc_init(void)
163{ 140{
164 /* i.mx50 has the i.mx35 type gpio */ 141 /* i.mx50 has the i.mx35 type gpio */
@@ -196,30 +173,6 @@ void __init imx51_soc_init(void)
196 ARRAY_SIZE(imx51_audmux_res)); 173 ARRAY_SIZE(imx51_audmux_res));
197} 174}
198 175
199void __init imx53_soc_init(void)
200{
201 /* i.mx53 has the i.mx35 type gpio */
202 mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
203 mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
204 mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
205 mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
206 mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
207 mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
208 mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
209
210 pinctrl_provide_dummies();
211 /* i.mx53 has the i.mx35 type sdma */
212 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
213
214 /* Setup AIPS registers */
215 imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
216 imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
217
218 /* i.mx53 has the i.mx31 type audmux */
219 platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
220 ARRAY_SIZE(imx53_audmux_res));
221}
222
223void __init imx51_init_late(void) 176void __init imx51_init_late(void)
224{ 177{
225 mx51_neon_fixup(); 178 mx51_neon_fixup();
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
deleted file mode 100644
index ee870c49bc63..000000000000
--- a/arch/arm/mach-imx/mx51_efika.c
+++ /dev/null
@@ -1,633 +0,0 @@
1/*
2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/i2c.h>
18#include <linux/gpio.h>
19#include <linux/leds.h>
20#include <linux/input.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/spi/flash.h>
24#include <linux/spi/spi.h>
25#include <linux/mfd/mc13892.h>
26#include <linux/regulator/machine.h>
27#include <linux/regulator/consumer.h>
28
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx51.h>
32
33#include <linux/usb/otg.h>
34#include <linux/usb/ulpi.h>
35#include <mach/ulpi.h>
36
37#include <asm/setup.h>
38#include <asm/mach-types.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/time.h>
41
42#include "devices-imx51.h"
43#include "efika.h"
44#include "cpu_op-mx51.h"
45
46#define MX51_USB_CTRL_1_OFFSET 0x10
47#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
48#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
49
50#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
51#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
52
53#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
54#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
55
56#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
57
58static iomux_v3_cfg_t mx51efika_pads[] = {
59 /* UART1 */
60 MX51_PAD_UART1_RXD__UART1_RXD,
61 MX51_PAD_UART1_TXD__UART1_TXD,
62 MX51_PAD_UART1_RTS__UART1_RTS,
63 MX51_PAD_UART1_CTS__UART1_CTS,
64
65 /* SD 1 */
66 MX51_PAD_SD1_CMD__SD1_CMD,
67 MX51_PAD_SD1_CLK__SD1_CLK,
68 MX51_PAD_SD1_DATA0__SD1_DATA0,
69 MX51_PAD_SD1_DATA1__SD1_DATA1,
70 MX51_PAD_SD1_DATA2__SD1_DATA2,
71 MX51_PAD_SD1_DATA3__SD1_DATA3,
72
73 /* SD 2 */
74 MX51_PAD_SD2_CMD__SD2_CMD,
75 MX51_PAD_SD2_CLK__SD2_CLK,
76 MX51_PAD_SD2_DATA0__SD2_DATA0,
77 MX51_PAD_SD2_DATA1__SD2_DATA1,
78 MX51_PAD_SD2_DATA2__SD2_DATA2,
79 MX51_PAD_SD2_DATA3__SD2_DATA3,
80
81 /* SD/MMC WP/CD */
82 MX51_PAD_GPIO1_0__SD1_CD,
83 MX51_PAD_GPIO1_1__SD1_WP,
84 MX51_PAD_GPIO1_7__SD2_WP,
85 MX51_PAD_GPIO1_8__SD2_CD,
86
87 /* spi */
88 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
89 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
90 MX51_PAD_CSPI1_SS0__GPIO4_24,
91 MX51_PAD_CSPI1_SS1__GPIO4_25,
92 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
93 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
94 MX51_PAD_GPIO1_6__GPIO1_6,
95
96 /* USB HOST1 */
97 MX51_PAD_USBH1_CLK__USBH1_CLK,
98 MX51_PAD_USBH1_DIR__USBH1_DIR,
99 MX51_PAD_USBH1_NXT__USBH1_NXT,
100 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
101 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
102 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
103 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
104 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
105 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
106 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
107 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
108
109 /* USB HUB RESET */
110 MX51_PAD_GPIO1_5__GPIO1_5,
111
112 /* WLAN */
113 MX51_PAD_EIM_A22__GPIO2_16,
114 MX51_PAD_EIM_A16__GPIO2_10,
115
116 /* USB PHY RESET */
117 MX51_PAD_EIM_D27__GPIO2_9,
118};
119
120/* Serial ports */
121static const struct imxuart_platform_data uart_pdata = {
122 .flags = IMXUART_HAVE_RTSCTS,
123};
124
125/* This function is board specific as the bit mask for the plldiv will also
126 * be different for other Freescale SoCs, thus a common bitmask is not
127 * possible and cannot get place in /plat-mxc/ehci.c.
128 */
129static int initialize_otg_port(struct platform_device *pdev)
130{
131 u32 v;
132 void __iomem *usb_base;
133 void __iomem *usbother_base;
134 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
135 if (!usb_base)
136 return -ENOMEM;
137 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
138
139 /* Set the PHY clock to 19.2MHz */
140 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
141 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
142 v |= MX51_USB_PLL_DIV_19_2_MHZ;
143 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
144 iounmap(usb_base);
145
146 mdelay(10);
147
148 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
149}
150
151static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
152 .init = initialize_otg_port,
153 .portsc = MXC_EHCI_UTMI_16BIT,
154};
155
156static int initialize_usbh1_port(struct platform_device *pdev)
157{
158 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
159 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
160 u32 v;
161 void __iomem *usb_base;
162 void __iomem *socregs_base;
163
164 mxc_iomux_v3_setup_pad(usbh1gpio);
165 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
166 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
167 msleep(1);
168 gpio_set_value(EFIKAMX_USBH1_STP, 1);
169 msleep(1);
170
171 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
172 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
173
174 /* The clock for the USBH1 ULPI port will come externally */
175 /* from the PHY. */
176 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
177 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
178 socregs_base + MX51_USB_CTRL_1_OFFSET);
179
180 iounmap(usb_base);
181
182 gpio_free(EFIKAMX_USBH1_STP);
183 mxc_iomux_v3_setup_pad(usbh1stp);
184
185 mdelay(10);
186
187 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
188}
189
190static struct mxc_usbh_platform_data usbh1_config __initdata = {
191 .init = initialize_usbh1_port,
192 .portsc = MXC_EHCI_MODE_ULPI,
193};
194
195static void mx51_efika_hubreset(void)
196{
197 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
198 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
199 msleep(1);
200 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
201 msleep(1);
202 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
203}
204
205static void __init mx51_efika_usb(void)
206{
207 mx51_efika_hubreset();
208
209 /* pulling it low, means no USB at all... */
210 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
211 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
212 msleep(1);
213 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
214
215 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
216 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
217
218 imx51_add_mxc_ehci_otg(&dr_utmi_config);
219 if (usbh1_config.otg)
220 imx51_add_mxc_ehci_hs(1, &usbh1_config);
221}
222
223static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
224 {
225 .name = "u-boot",
226 .offset = 0,
227 .size = SZ_256K,
228 },
229 {
230 .name = "config",
231 .offset = MTDPART_OFS_APPEND,
232 .size = SZ_64K,
233 },
234};
235
236static struct flash_platform_data mx51_efika_spi_flash_data = {
237 .name = "spi_flash",
238 .parts = mx51_efika_spi_nor_partitions,
239 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
240 .type = "sst25vf032b",
241};
242
243static struct regulator_consumer_supply sw1_consumers[] = {
244 {
245 .supply = "cpu_vcc",
246 }
247};
248
249static struct regulator_consumer_supply vdig_consumers[] = {
250 /* sgtl5000 */
251 REGULATOR_SUPPLY("VDDA", "1-000a"),
252 REGULATOR_SUPPLY("VDDD", "1-000a"),
253};
254
255static struct regulator_consumer_supply vvideo_consumers[] = {
256 /* sgtl5000 */
257 REGULATOR_SUPPLY("VDDIO", "1-000a"),
258};
259
260static struct regulator_consumer_supply vsd_consumers[] = {
261 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
262 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
263};
264
265static struct regulator_consumer_supply pwgt1_consumer[] = {
266 {
267 .supply = "pwgt1",
268 }
269};
270
271static struct regulator_consumer_supply pwgt2_consumer[] = {
272 {
273 .supply = "pwgt2",
274 }
275};
276
277static struct regulator_consumer_supply coincell_consumer[] = {
278 {
279 .supply = "coincell",
280 }
281};
282
283static struct regulator_init_data sw1_init = {
284 .constraints = {
285 .name = "SW1",
286 .min_uV = 600000,
287 .max_uV = 1375000,
288 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
289 .valid_modes_mask = 0,
290 .always_on = 1,
291 .boot_on = 1,
292 .state_mem = {
293 .uV = 850000,
294 .mode = REGULATOR_MODE_NORMAL,
295 .enabled = 1,
296 },
297 },
298 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
299 .consumer_supplies = sw1_consumers,
300};
301
302static struct regulator_init_data sw2_init = {
303 .constraints = {
304 .name = "SW2",
305 .min_uV = 900000,
306 .max_uV = 1850000,
307 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
308 .always_on = 1,
309 .boot_on = 1,
310 .state_mem = {
311 .uV = 950000,
312 .mode = REGULATOR_MODE_NORMAL,
313 .enabled = 1,
314 },
315 }
316};
317
318static struct regulator_init_data sw3_init = {
319 .constraints = {
320 .name = "SW3",
321 .min_uV = 1100000,
322 .max_uV = 1850000,
323 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
324 .always_on = 1,
325 .boot_on = 1,
326 }
327};
328
329static struct regulator_init_data sw4_init = {
330 .constraints = {
331 .name = "SW4",
332 .min_uV = 1100000,
333 .max_uV = 1850000,
334 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
335 .always_on = 1,
336 .boot_on = 1,
337 }
338};
339
340static struct regulator_init_data viohi_init = {
341 .constraints = {
342 .name = "VIOHI",
343 .boot_on = 1,
344 .always_on = 1,
345 }
346};
347
348static struct regulator_init_data vusb_init = {
349 .constraints = {
350 .name = "VUSB",
351 .boot_on = 1,
352 .always_on = 1,
353 }
354};
355
356static struct regulator_init_data swbst_init = {
357 .constraints = {
358 .name = "SWBST",
359 }
360};
361
362static struct regulator_init_data vdig_init = {
363 .constraints = {
364 .name = "VDIG",
365 .min_uV = 1050000,
366 .max_uV = 1800000,
367 .valid_ops_mask =
368 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
369 .boot_on = 1,
370 .always_on = 1,
371 },
372 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
373 .consumer_supplies = vdig_consumers,
374};
375
376static struct regulator_init_data vpll_init = {
377 .constraints = {
378 .name = "VPLL",
379 .min_uV = 1050000,
380 .max_uV = 1800000,
381 .valid_ops_mask =
382 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
383 .boot_on = 1,
384 .always_on = 1,
385 }
386};
387
388static struct regulator_init_data vusb2_init = {
389 .constraints = {
390 .name = "VUSB2",
391 .min_uV = 2400000,
392 .max_uV = 2775000,
393 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
394 .boot_on = 1,
395 .always_on = 1,
396 }
397};
398
399static struct regulator_init_data vvideo_init = {
400 .constraints = {
401 .name = "VVIDEO",
402 .min_uV = 2775000,
403 .max_uV = 2775000,
404 .valid_ops_mask =
405 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
406 .boot_on = 1,
407 .apply_uV = 1,
408 },
409 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
410 .consumer_supplies = vvideo_consumers,
411};
412
413static struct regulator_init_data vaudio_init = {
414 .constraints = {
415 .name = "VAUDIO",
416 .min_uV = 2300000,
417 .max_uV = 3000000,
418 .valid_ops_mask =
419 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
420 .boot_on = 1,
421 }
422};
423
424static struct regulator_init_data vsd_init = {
425 .constraints = {
426 .name = "VSD",
427 .min_uV = 1800000,
428 .max_uV = 3150000,
429 .valid_ops_mask =
430 REGULATOR_CHANGE_VOLTAGE,
431 .boot_on = 1,
432 },
433 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
434 .consumer_supplies = vsd_consumers,
435};
436
437static struct regulator_init_data vcam_init = {
438 .constraints = {
439 .name = "VCAM",
440 .min_uV = 2500000,
441 .max_uV = 3000000,
442 .valid_ops_mask =
443 REGULATOR_CHANGE_VOLTAGE |
444 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
445 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
446 .boot_on = 1,
447 }
448};
449
450static struct regulator_init_data vgen1_init = {
451 .constraints = {
452 .name = "VGEN1",
453 .min_uV = 1200000,
454 .max_uV = 3150000,
455 .valid_ops_mask =
456 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
457 .boot_on = 1,
458 .always_on = 1,
459 }
460};
461
462static struct regulator_init_data vgen2_init = {
463 .constraints = {
464 .name = "VGEN2",
465 .min_uV = 1200000,
466 .max_uV = 3150000,
467 .valid_ops_mask =
468 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
469 .boot_on = 1,
470 .always_on = 1,
471 }
472};
473
474static struct regulator_init_data vgen3_init = {
475 .constraints = {
476 .name = "VGEN3",
477 .min_uV = 1800000,
478 .max_uV = 2900000,
479 .valid_ops_mask =
480 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
481 .boot_on = 1,
482 .always_on = 1,
483 }
484};
485
486static struct regulator_init_data gpo1_init = {
487 .constraints = {
488 .name = "GPO1",
489 }
490};
491
492static struct regulator_init_data gpo2_init = {
493 .constraints = {
494 .name = "GPO2",
495 }
496};
497
498static struct regulator_init_data gpo3_init = {
499 .constraints = {
500 .name = "GPO3",
501 }
502};
503
504static struct regulator_init_data gpo4_init = {
505 .constraints = {
506 .name = "GPO4",
507 }
508};
509
510static struct regulator_init_data pwgt1_init = {
511 .constraints = {
512 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
513 .boot_on = 1,
514 },
515 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
516 .consumer_supplies = pwgt1_consumer,
517};
518
519static struct regulator_init_data pwgt2_init = {
520 .constraints = {
521 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
522 .boot_on = 1,
523 },
524 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
525 .consumer_supplies = pwgt2_consumer,
526};
527
528static struct regulator_init_data vcoincell_init = {
529 .constraints = {
530 .name = "COINCELL",
531 .min_uV = 3000000,
532 .max_uV = 3000000,
533 .valid_ops_mask =
534 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
535 },
536 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
537 .consumer_supplies = coincell_consumer,
538};
539
540static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
541 { .id = MC13892_SW1, .init_data = &sw1_init },
542 { .id = MC13892_SW2, .init_data = &sw2_init },
543 { .id = MC13892_SW3, .init_data = &sw3_init },
544 { .id = MC13892_SW4, .init_data = &sw4_init },
545 { .id = MC13892_SWBST, .init_data = &swbst_init },
546 { .id = MC13892_VIOHI, .init_data = &viohi_init },
547 { .id = MC13892_VPLL, .init_data = &vpll_init },
548 { .id = MC13892_VDIG, .init_data = &vdig_init },
549 { .id = MC13892_VSD, .init_data = &vsd_init },
550 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
551 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
552 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
553 { .id = MC13892_VCAM, .init_data = &vcam_init },
554 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
555 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
556 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
557 { .id = MC13892_VUSB, .init_data = &vusb_init },
558 { .id = MC13892_GPO1, .init_data = &gpo1_init },
559 { .id = MC13892_GPO2, .init_data = &gpo2_init },
560 { .id = MC13892_GPO3, .init_data = &gpo3_init },
561 { .id = MC13892_GPO4, .init_data = &gpo4_init },
562 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
563 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
564 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
565};
566
567static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
568 .flags = MC13XXX_USE_RTC,
569 .regulators = {
570 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
571 .regulators = mx51_efika_regulators,
572 },
573};
574
575static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
576 {
577 .modalias = "m25p80",
578 .max_speed_hz = 25000000,
579 .bus_num = 0,
580 .chip_select = 1,
581 .platform_data = &mx51_efika_spi_flash_data,
582 .irq = -1,
583 },
584 {
585 .modalias = "mc13892",
586 .max_speed_hz = 1000000,
587 .bus_num = 0,
588 .chip_select = 0,
589 .platform_data = &mx51_efika_mc13892_data,
590 /* irq number is run-time assigned */
591 },
592};
593
594static int mx51_efika_spi_cs[] = {
595 EFIKAMX_SPI_CS0,
596 EFIKAMX_SPI_CS1,
597};
598
599static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
600 .chipselect = mx51_efika_spi_cs,
601 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
602};
603
604void __init efika_board_common_init(void)
605{
606 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
607 ARRAY_SIZE(mx51efika_pads));
608 imx51_add_imx_uart(0, &uart_pdata);
609 mx51_efika_usb();
610
611 /* FIXME: comes from original code. check this. */
612 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
613 sw2_init.constraints.state_mem.uV = 1100000;
614 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
615 sw2_init.constraints.state_mem.uV = 1250000;
616 sw1_init.constraints.state_mem.uV = 1000000;
617 }
618 if (machine_is_mx51_efikasb())
619 vgen1_init.constraints.max_uV = 1200000;
620
621 gpio_request(EFIKAMX_PMIC, "pmic irq");
622 gpio_direction_input(EFIKAMX_PMIC);
623 mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
624 spi_register_board_info(mx51_efika_spi_board_info,
625 ARRAY_SIZE(mx51_efika_spi_board_info));
626 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
627
628 imx51_add_pata_imx();
629
630#if defined(CONFIG_CPU_FREQ_IMX)
631 get_cpu_op = mx51_get_cpu_op;
632#endif
633}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 07:32:51 -0500