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-rw-r--r--arch/arm/mach-imx/3ds_debugboard.c213
-rw-r--r--arch/arm/mach-imx/Kconfig80
-rw-r--r--arch/arm/mach-imx/Makefile17
-rw-r--r--arch/arm/mach-imx/avic.c225
-rw-r--r--arch/arm/mach-imx/cpu.c44
-rw-r--r--arch/arm/mach-imx/cpufreq.c205
-rw-r--r--arch/arm/mach-imx/cpuidle.c80
-rw-r--r--arch/arm/mach-imx/epit.c234
-rw-r--r--arch/arm/mach-imx/include/mach/common.h162
-rw-r--r--arch/arm/mach-imx/include/mach/cpuidle.h22
-rw-r--r--arch/arm/mach-imx/include/mach/debug-macro.S51
-rw-r--r--arch/arm/mach-imx/include/mach/hardware.h134
-rw-r--r--arch/arm/mach-imx/include/mach/iim.h77
-rw-r--r--arch/arm/mach-imx/include/mach/ipu.h177
-rw-r--r--arch/arm/mach-imx/include/mach/iram.h41
-rw-r--r--arch/arm/mach-imx/include/mach/irqs.h21
-rw-r--r--arch/arm/mach-imx/include/mach/mx1.h172
-rw-r--r--arch/arm/mach-imx/include/mach/mx21.h189
-rw-r--r--arch/arm/mach-imx/include/mach/mx25.h117
-rw-r--r--arch/arm/mach-imx/include/mach/mx27.h238
-rw-r--r--arch/arm/mach-imx/include/mach/mx2x.h145
-rw-r--r--arch/arm/mach-imx/include/mach/mx31.h196
-rw-r--r--arch/arm/mach-imx/include/mach/mx35.h190
-rw-r--r--arch/arm/mach-imx/include/mach/mx3x.h195
-rw-r--r--arch/arm/mach-imx/include/mach/mx50.h290
-rw-r--r--arch/arm/mach-imx/include/mach/mx51.h346
-rw-r--r--arch/arm/mach-imx/include/mach/mx53.h342
-rw-r--r--arch/arm/mach-imx/include/mach/mx6q.h35
-rw-r--r--arch/arm/mach-imx/include/mach/mxc.h179
-rw-r--r--arch/arm/mach-imx/include/mach/timex.h22
-rw-r--r--arch/arm/mach-imx/include/mach/ulpi.h16
-rw-r--r--arch/arm/mach-imx/include/mach/uncompress.h132
-rw-r--r--arch/arm/mach-imx/iram_alloc.c73
-rw-r--r--arch/arm/mach-imx/irq-common.c60
-rw-r--r--arch/arm/mach-imx/irq-common.h28
-rw-r--r--arch/arm/mach-imx/ssi-fiq-ksym.c20
-rw-r--r--arch/arm/mach-imx/ssi-fiq.S147
-rw-r--r--arch/arm/mach-imx/system.c69
-rw-r--r--arch/arm/mach-imx/time.c325
-rw-r--r--arch/arm/mach-imx/tzic.c224
-rw-r--r--arch/arm/mach-imx/ulpi.c118
41 files changed, 5651 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/3ds_debugboard.c b/arch/arm/mach-imx/3ds_debugboard.c
new file mode 100644
index 000000000000..5c10ad05df74
--- /dev/null
+++ b/arch/arm/mach-imx/3ds_debugboard.c
@@ -0,0 +1,213 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
19#include <linux/module.h>
20#include <linux/smsc911x.h>
21#include <linux/regulator/machine.h>
22#include <linux/regulator/fixed.h>
23
24#include <mach/hardware.h>
25
26/* LAN9217 ethernet base address */
27#define LAN9217_BASE_ADDR(n) (n + 0x0)
28/* External UART */
29#define UARTA_BASE_ADDR(n) (n + 0x8000)
30#define UARTB_BASE_ADDR(n) (n + 0x10000)
31
32#define BOARD_IO_ADDR(n) (n + 0x20000)
33/* LED switchs */
34#define LED_SWITCH_REG 0x00
35/* buttons */
36#define SWITCH_BUTTONS_REG 0x08
37/* status, interrupt */
38#define INTR_STATUS_REG 0x10
39#define INTR_MASK_REG 0x38
40#define INTR_RESET_REG 0x20
41/* magic word for debug CPLD */
42#define MAGIC_NUMBER1_REG 0x40
43#define MAGIC_NUMBER2_REG 0x48
44/* CPLD code version */
45#define CPLD_CODE_VER_REG 0x50
46/* magic word for debug CPLD */
47#define MAGIC_NUMBER3_REG 0x58
48/* module reset register*/
49#define MODULE_RESET_REG 0x60
50/* CPU ID and Personality ID */
51#define MCU_BOARD_ID_REG 0x68
52
53#define MXC_MAX_EXP_IO_LINES 16
54
55/* interrupts like external uart , external ethernet etc*/
56#define EXPIO_INT_ENET 0
57#define EXPIO_INT_XUART_A 1
58#define EXPIO_INT_XUART_B 2
59#define EXPIO_INT_BUTTON_A 3
60#define EXPIO_INT_BUTTON_B 4
61
62static void __iomem *brd_io;
63static struct irq_domain *domain;
64
65static struct resource smsc911x_resources[] = {
66 {
67 .flags = IORESOURCE_MEM,
68 } , {
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73static struct smsc911x_platform_config smsc911x_config = {
74 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
75 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
76};
77
78static struct platform_device smsc_lan9217_device = {
79 .name = "smsc911x",
80 .id = -1,
81 .dev = {
82 .platform_data = &smsc911x_config,
83 },
84 .num_resources = ARRAY_SIZE(smsc911x_resources),
85 .resource = smsc911x_resources,
86};
87
88static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
89{
90 u32 imr_val;
91 u32 int_valid;
92 u32 expio_irq;
93
94 /* irq = gpio irq number */
95 desc->irq_data.chip->irq_mask(&desc->irq_data);
96
97 imr_val = __raw_readw(brd_io + INTR_MASK_REG);
98 int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
99
100 expio_irq = 0;
101 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
102 if ((int_valid & 1) == 0)
103 continue;
104 generic_handle_irq(irq_find_mapping(domain, expio_irq));
105 }
106
107 desc->irq_data.chip->irq_ack(&desc->irq_data);
108 desc->irq_data.chip->irq_unmask(&desc->irq_data);
109}
110
111/*
112 * Disable an expio pin's interrupt by setting the bit in the imr.
113 * Irq is an expio virtual irq number
114 */
115static void expio_mask_irq(struct irq_data *d)
116{
117 u16 reg;
118 u32 expio = d->hwirq;
119
120 reg = __raw_readw(brd_io + INTR_MASK_REG);
121 reg |= (1 << expio);
122 __raw_writew(reg, brd_io + INTR_MASK_REG);
123}
124
125static void expio_ack_irq(struct irq_data *d)
126{
127 u32 expio = d->hwirq;
128
129 __raw_writew(1 << expio, brd_io + INTR_RESET_REG);
130 __raw_writew(0, brd_io + INTR_RESET_REG);
131 expio_mask_irq(d);
132}
133
134static void expio_unmask_irq(struct irq_data *d)
135{
136 u16 reg;
137 u32 expio = d->hwirq;
138
139 reg = __raw_readw(brd_io + INTR_MASK_REG);
140 reg &= ~(1 << expio);
141 __raw_writew(reg, brd_io + INTR_MASK_REG);
142}
143
144static struct irq_chip expio_irq_chip = {
145 .irq_ack = expio_ack_irq,
146 .irq_mask = expio_mask_irq,
147 .irq_unmask = expio_unmask_irq,
148};
149
150static struct regulator_consumer_supply dummy_supplies[] = {
151 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
152 REGULATOR_SUPPLY("vddvario", "smsc911x"),
153};
154
155int __init mxc_expio_init(u32 base, u32 intr_gpio)
156{
157 u32 p_irq = gpio_to_irq(intr_gpio);
158 int irq_base;
159 int i;
160
161 brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
162 if (brd_io == NULL)
163 return -ENOMEM;
164
165 if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
166 (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
167 (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
168 pr_info("3-Stack Debug board not detected\n");
169 iounmap(brd_io);
170 brd_io = NULL;
171 return -ENODEV;
172 }
173
174 pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
175 readw(brd_io + CPLD_CODE_VER_REG));
176
177 /*
178 * Configure INT line as GPIO input
179 */
180 gpio_request(intr_gpio, "expio_pirq");
181 gpio_direction_input(intr_gpio);
182
183 /* disable the interrupt and clear the status */
184 __raw_writew(0, brd_io + INTR_MASK_REG);
185 __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
186 __raw_writew(0, brd_io + INTR_RESET_REG);
187 __raw_writew(0x1F, brd_io + INTR_MASK_REG);
188
189 irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
190 WARN_ON(irq_base < 0);
191
192 domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
193 &irq_domain_simple_ops, NULL);
194 WARN_ON(!domain);
195
196 for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
197 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
198 set_irq_flags(i, IRQF_VALID);
199 }
200 irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
201 irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
202
203 /* Register Lan device on the debugboard */
204 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
205
206 smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
207 smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
208 smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET);
209 smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET);
210 platform_device_register(&smsc_lan9217_device);
211
212 return 0;
213}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index dffa273b124e..05ded3748d78 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,3 +1,54 @@
1if ARCH_MXC
2
3config MXC_IRQ_PRIOR
4 bool "Use IRQ priority"
5 help
6 Select this if you want to use prioritized IRQ handling.
7 This feature prevents higher priority ISR to be interrupted
8 by lower priority IRQ even IRQF_DISABLED flag is not set.
9 This may be useful in embedded applications, where are strong
10 requirements for timing.
11 Say N here, unless you have a specialized requirement.
12
13config MXC_TZIC
14 bool
15
16config MXC_AVIC
17 bool
18
19config MXC_DEBUG_BOARD
20 bool "Enable MXC debug board(for 3-stack)"
21 help
22 The debug board is an integral part of the MXC 3-stack(PDK)
23 platforms, it can be attached or removed from the peripheral
24 board. On debug board, several debug devices(ethernet, UART,
25 buttons, LEDs and JTAG) are implemented. Between the MCU and
26 these devices, a CPLD is added as a bridge which performs
27 data/address de-multiplexing and decode, signal level shift,
28 interrupt control and various board functions.
29
30config HAVE_EPIT
31 bool
32
33config MXC_USE_EPIT
34 bool "Use EPIT instead of GPT"
35 depends on HAVE_EPIT
36 help
37 Use EPIT as the system timer on systems that have it. Normally you
38 don't have a reason to do so as the EPIT has the same features and
39 uses the same clocks as the GPT. Anyway, on some systems the GPT
40 may be in use for other purposes.
41
42config MXC_ULPI
43 bool
44
45config ARCH_HAS_RNGA
46 bool
47
48config IRAM_ALLOC
49 bool
50 select GENERIC_ALLOCATOR
51
1config HAVE_IMX_GPC 52config HAVE_IMX_GPC
2 bool 53 bool
3 54
@@ -110,6 +161,20 @@ config SOC_IMX51
110 select PINCTRL_IMX51 161 select PINCTRL_IMX51
111 select SOC_IMX5 162 select SOC_IMX5
112 163
164menu "Freescale MXC Implementations"
165
166choice
167 prompt "Freescale CPU family:"
168 default ARCH_IMX_V6_V7
169
170config ARCH_IMX_V4_V5
171 bool "i.MX1, i.MX21, i.MX25, i.MX27"
172 select ARM_PATCH_PHYS_VIRT
173 select AUTO_ZRELADDR if !ZBOOT_ROM
174 help
175 This enables support for systems based on the Freescale i.MX ARMv4
176 and ARMv5 SoCs
177
113if ARCH_IMX_V4_V5 178if ARCH_IMX_V4_V5
114 179
115comment "MX1 platforms:" 180comment "MX1 platforms:"
@@ -390,6 +455,15 @@ config MACH_IMX27_DT
390 455
391endif 456endif
392 457
458config ARCH_IMX_V6_V7
459 bool "i.MX3, i.MX5, i.MX6"
460 select ARM_PATCH_PHYS_VIRT
461 select AUTO_ZRELADDR if !ZBOOT_ROM
462 select MIGHT_HAVE_CACHE_L2X0
463 help
464 This enables support for systems based on the Freescale i.MX3, i.MX5
465 and i.MX6 family.
466
393if ARCH_IMX_V6_V7 467if ARCH_IMX_V6_V7
394 468
395comment "MX31 platforms:" 469comment "MX31 platforms:"
@@ -773,4 +847,10 @@ config SOC_IMX6Q
773 847
774endif 848endif
775 849
850endchoice
851
852endmenu
853
776source "arch/arm/mach-imx/devices/Kconfig" 854source "arch/arm/mach-imx/devices/Kconfig"
855
856endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 257893e6db93..fe47b71469c9 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,3 +1,5 @@
1obj-y := time.o cpu.o system.o irq-common.o
2
1obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o 3obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
2obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o 4obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
3 5
@@ -18,6 +20,21 @@ obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
18obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 20obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
19obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 21obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
20 22
23obj-$(CONFIG_MXC_TZIC) += tzic.o
24obj-$(CONFIG_MXC_AVIC) += avic.o
25
26obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
27obj-$(CONFIG_MXC_ULPI) += ulpi.o
28obj-$(CONFIG_MXC_USE_EPIT) += epit.o
29obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
30obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
31obj-$(CONFIG_CPU_IDLE) += cpuidle.o
32
33ifdef CONFIG_SND_IMX_SOC
34obj-y += ssi-fiq.o
35obj-y += ssi-fiq-ksym.o
36endif
37
21# Support for CMOS sensor interface 38# Support for CMOS sensor interface
22obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o 39obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
23 40
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
new file mode 100644
index 000000000000..cbd55c36def3
--- /dev/null
+++ b/arch/arm/mach-imx/avic.c
@@ -0,0 +1,225 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/irq.h>
22#include <linux/irqdomain.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <mach/common.h>
26#include <asm/mach/irq.h>
27#include <asm/exception.h>
28#include <mach/hardware.h>
29#include <mach/irqs.h>
30
31#include "irq-common.h"
32
33#define AVIC_INTCNTL 0x00 /* int control reg */
34#define AVIC_NIMASK 0x04 /* int mask reg */
35#define AVIC_INTENNUM 0x08 /* int enable number reg */
36#define AVIC_INTDISNUM 0x0C /* int disable number reg */
37#define AVIC_INTENABLEH 0x10 /* int enable reg high */
38#define AVIC_INTENABLEL 0x14 /* int enable reg low */
39#define AVIC_INTTYPEH 0x18 /* int type reg high */
40#define AVIC_INTTYPEL 0x1C /* int type reg low */
41#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */
42#define AVIC_NIVECSR 0x40 /* norm int vector/status */
43#define AVIC_FIVECSR 0x44 /* fast int vector/status */
44#define AVIC_INTSRCH 0x48 /* int source reg high */
45#define AVIC_INTSRCL 0x4C /* int source reg low */
46#define AVIC_INTFRCH 0x50 /* int force reg high */
47#define AVIC_INTFRCL 0x54 /* int force reg low */
48#define AVIC_NIPNDH 0x58 /* norm int pending high */
49#define AVIC_NIPNDL 0x5C /* norm int pending low */
50#define AVIC_FIPNDH 0x60 /* fast int pending high */
51#define AVIC_FIPNDL 0x64 /* fast int pending low */
52
53#define AVIC_NUM_IRQS 64
54
55void __iomem *avic_base;
56static struct irq_domain *domain;
57
58static u32 avic_saved_mask_reg[2];
59
60#ifdef CONFIG_MXC_IRQ_PRIOR
61static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
62{
63 struct irq_data *d = irq_get_irq_data(irq);
64 unsigned int temp;
65 unsigned int mask = 0x0F << irq % 8 * 4;
66
67 irq = d->hwirq;
68
69 if (irq >= AVIC_NUM_IRQS)
70 return -EINVAL;
71
72 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
73 temp &= ~mask;
74 temp |= prio & mask;
75
76 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
77
78 return 0;
79}
80#endif
81
82#ifdef CONFIG_FIQ
83static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
84{
85 struct irq_data *d = irq_get_irq_data(irq);
86 unsigned int irqt;
87
88 irq = d->hwirq;
89
90 if (irq >= AVIC_NUM_IRQS)
91 return -EINVAL;
92
93 if (irq < AVIC_NUM_IRQS / 2) {
94 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
95 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
96 } else {
97 irq -= AVIC_NUM_IRQS / 2;
98 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
99 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
100 }
101
102 return 0;
103}
104#endif /* CONFIG_FIQ */
105
106
107static struct mxc_extra_irq avic_extra_irq = {
108#ifdef CONFIG_MXC_IRQ_PRIOR
109 .set_priority = avic_irq_set_priority,
110#endif
111#ifdef CONFIG_FIQ
112 .set_irq_fiq = avic_set_irq_fiq,
113#endif
114};
115
116#ifdef CONFIG_PM
117static void avic_irq_suspend(struct irq_data *d)
118{
119 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
120 struct irq_chip_type *ct = gc->chip_types;
121 int idx = d->hwirq >> 5;
122
123 avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
124 __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
125}
126
127static void avic_irq_resume(struct irq_data *d)
128{
129 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
130 struct irq_chip_type *ct = gc->chip_types;
131 int idx = d->hwirq >> 5;
132
133 __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
134}
135
136#else
137#define avic_irq_suspend NULL
138#define avic_irq_resume NULL
139#endif
140
141static __init void avic_init_gc(int idx, unsigned int irq_start)
142{
143 struct irq_chip_generic *gc;
144 struct irq_chip_type *ct;
145
146 gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
147 handle_level_irq);
148 gc->private = &avic_extra_irq;
149 gc->wake_enabled = IRQ_MSK(32);
150
151 ct = gc->chip_types;
152 ct->chip.irq_mask = irq_gc_mask_clr_bit;
153 ct->chip.irq_unmask = irq_gc_mask_set_bit;
154 ct->chip.irq_ack = irq_gc_mask_clr_bit;
155 ct->chip.irq_set_wake = irq_gc_set_wake;
156 ct->chip.irq_suspend = avic_irq_suspend;
157 ct->chip.irq_resume = avic_irq_resume;
158 ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
159 ct->regs.ack = ct->regs.mask;
160
161 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
162}
163
164asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
165{
166 u32 nivector;
167
168 do {
169 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
170 if (nivector == 0xffff)
171 break;
172
173 handle_IRQ(irq_find_mapping(domain, nivector), regs);
174 } while (1);
175}
176
177/*
178 * This function initializes the AVIC hardware and disables all the
179 * interrupts. It registers the interrupt enable and disable functions
180 * to the kernel for each interrupt source.
181 */
182void __init mxc_init_irq(void __iomem *irqbase)
183{
184 struct device_node *np;
185 int irq_base;
186 int i;
187
188 avic_base = irqbase;
189
190 /* put the AVIC into the reset value with
191 * all interrupts disabled
192 */
193 __raw_writel(0, avic_base + AVIC_INTCNTL);
194 __raw_writel(0x1f, avic_base + AVIC_NIMASK);
195
196 /* disable all interrupts */
197 __raw_writel(0, avic_base + AVIC_INTENABLEH);
198 __raw_writel(0, avic_base + AVIC_INTENABLEL);
199
200 /* all IRQ no FIQ */
201 __raw_writel(0, avic_base + AVIC_INTTYPEH);
202 __raw_writel(0, avic_base + AVIC_INTTYPEL);
203
204 irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
205 WARN_ON(irq_base < 0);
206
207 np = of_find_compatible_node(NULL, NULL, "fsl,avic");
208 domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
209 &irq_domain_simple_ops, NULL);
210 WARN_ON(!domain);
211
212 for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
213 avic_init_gc(i, irq_base);
214
215 /* Set default priority value (0) for all IRQ's */
216 for (i = 0; i < 8; i++)
217 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
218
219#ifdef CONFIG_FIQ
220 /* Initialize FIQ */
221 init_FIQ(FIQ_START);
222#endif
223
224 printk(KERN_INFO "MXC IRQ initialized\n");
225}
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
new file mode 100644
index 000000000000..220dd6f93126
--- /dev/null
+++ b/arch/arm/mach-imx/cpu.c
@@ -0,0 +1,44 @@
1
2#include <linux/module.h>
3#include <linux/io.h>
4#include <mach/hardware.h>
5
6unsigned int __mxc_cpu_type;
7EXPORT_SYMBOL(__mxc_cpu_type);
8
9void mxc_set_cpu_type(unsigned int type)
10{
11 __mxc_cpu_type = type;
12}
13
14void imx_print_silicon_rev(const char *cpu, int srev)
15{
16 if (srev == IMX_CHIP_REVISION_UNKNOWN)
17 pr_info("CPU identified as %s, unknown revision\n", cpu);
18 else
19 pr_info("CPU identified as %s, silicon rev %d.%d\n",
20 cpu, (srev >> 4) & 0xf, srev & 0xf);
21}
22
23void __init imx_set_aips(void __iomem *base)
24{
25 unsigned int reg;
26/*
27 * Set all MPROTx to be non-bufferable, trusted for R/W,
28 * not forced to user-mode.
29 */
30 __raw_writel(0x77777777, base + 0x0);
31 __raw_writel(0x77777777, base + 0x4);
32
33/*
34 * Set all OPACRx to be non-bufferable, to not require
35 * supervisor privilege level for access, allow for
36 * write access and untrusted master access.
37 */
38 __raw_writel(0x0, base + 0x40);
39 __raw_writel(0x0, base + 0x44);
40 __raw_writel(0x0, base + 0x48);
41 __raw_writel(0x0, base + 0x4C);
42 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
43 __raw_writel(reg, base + 0x50);
44}
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
new file mode 100644
index 000000000000..b5b6f8083130
--- /dev/null
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -0,0 +1,205 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/*
15 * A driver for the Freescale Semiconductor i.MXC CPUfreq module.
16 * The CPUFREQ driver is for controlling CPU frequency. It allows you to change
17 * the CPU clock speed on the fly.
18 */
19
20#include <linux/module.h>
21#include <linux/cpufreq.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/slab.h>
25#include <mach/hardware.h>
26
27#define CLK32_FREQ 32768
28#define NANOSECOND (1000 * 1000 * 1000)
29
30struct cpu_op *(*get_cpu_op)(int *op);
31
32static int cpu_freq_khz_min;
33static int cpu_freq_khz_max;
34
35static struct clk *cpu_clk;
36static struct cpufreq_frequency_table *imx_freq_table;
37
38static int cpu_op_nr;
39static struct cpu_op *cpu_op_tbl;
40
41static int set_cpu_freq(int freq)
42{
43 int ret = 0;
44 int org_cpu_rate;
45
46 org_cpu_rate = clk_get_rate(cpu_clk);
47 if (org_cpu_rate == freq)
48 return ret;
49
50 ret = clk_set_rate(cpu_clk, freq);
51 if (ret != 0) {
52 printk(KERN_DEBUG "cannot set CPU clock rate\n");
53 return ret;
54 }
55
56 return ret;
57}
58
59static int mxc_verify_speed(struct cpufreq_policy *policy)
60{
61 if (policy->cpu != 0)
62 return -EINVAL;
63
64 return cpufreq_frequency_table_verify(policy, imx_freq_table);
65}
66
67static unsigned int mxc_get_speed(unsigned int cpu)
68{
69 if (cpu)
70 return 0;
71
72 return clk_get_rate(cpu_clk) / 1000;
73}
74
75static int mxc_set_target(struct cpufreq_policy *policy,
76 unsigned int target_freq, unsigned int relation)
77{
78 struct cpufreq_freqs freqs;
79 int freq_Hz;
80 int ret = 0;
81 unsigned int index;
82
83 cpufreq_frequency_table_target(policy, imx_freq_table,
84 target_freq, relation, &index);
85 freq_Hz = imx_freq_table[index].frequency * 1000;
86
87 freqs.old = clk_get_rate(cpu_clk) / 1000;
88 freqs.new = freq_Hz / 1000;
89 freqs.cpu = 0;
90 freqs.flags = 0;
91 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
92
93 ret = set_cpu_freq(freq_Hz);
94
95 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
96
97 return ret;
98}
99
100static int mxc_cpufreq_init(struct cpufreq_policy *policy)
101{
102 int ret;
103 int i;
104
105 printk(KERN_INFO "i.MXC CPU frequency driver\n");
106
107 if (policy->cpu != 0)
108 return -EINVAL;
109
110 if (!get_cpu_op)
111 return -EINVAL;
112
113 cpu_clk = clk_get(NULL, "cpu_clk");
114 if (IS_ERR(cpu_clk)) {
115 printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
116 return PTR_ERR(cpu_clk);
117 }
118
119 cpu_op_tbl = get_cpu_op(&cpu_op_nr);
120
121 cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
122 cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
123
124 imx_freq_table = kmalloc(
125 sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
126 GFP_KERNEL);
127 if (!imx_freq_table) {
128 ret = -ENOMEM;
129 goto err1;
130 }
131
132 for (i = 0; i < cpu_op_nr; i++) {
133 imx_freq_table[i].index = i;
134 imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
135
136 if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
137 cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
138
139 if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
140 cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
141 }
142
143 imx_freq_table[i].index = i;
144 imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
145
146 policy->cur = clk_get_rate(cpu_clk) / 1000;
147 policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
148 policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
149
150 /* Manual states, that PLL stabilizes in two CLK32 periods */
151 policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
152
153 ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
154
155 if (ret < 0) {
156 printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n",
157 __func__, ret);
158 goto err;
159 }
160
161 cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
162 return 0;
163err:
164 kfree(imx_freq_table);
165err1:
166 clk_put(cpu_clk);
167 return ret;
168}
169
170static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
171{
172 cpufreq_frequency_table_put_attr(policy->cpu);
173
174 set_cpu_freq(cpu_freq_khz_max * 1000);
175 clk_put(cpu_clk);
176 kfree(imx_freq_table);
177 return 0;
178}
179
180static struct cpufreq_driver mxc_driver = {
181 .flags = CPUFREQ_STICKY,
182 .verify = mxc_verify_speed,
183 .target = mxc_set_target,
184 .get = mxc_get_speed,
185 .init = mxc_cpufreq_init,
186 .exit = mxc_cpufreq_exit,
187 .name = "imx",
188};
189
190static int __devinit mxc_cpufreq_driver_init(void)
191{
192 return cpufreq_register_driver(&mxc_driver);
193}
194
195static void mxc_cpufreq_driver_exit(void)
196{
197 cpufreq_unregister_driver(&mxc_driver);
198}
199
200module_init(mxc_cpufreq_driver_init);
201module_exit(mxc_cpufreq_driver_exit);
202
203MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
204MODULE_DESCRIPTION("CPUfreq driver for i.MX");
205MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-imx/cpuidle.c b/arch/arm/mach-imx/cpuidle.c
new file mode 100644
index 000000000000..d4cb511a44a8
--- /dev/null
+++ b/arch/arm/mach-imx/cpuidle.c
@@ -0,0 +1,80 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/cpuidle.h>
14#include <linux/err.h>
15#include <linux/hrtimer.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19
20static struct cpuidle_device __percpu * imx_cpuidle_devices;
21
22static void __init imx_cpuidle_devices_uninit(void)
23{
24 int cpu_id;
25 struct cpuidle_device *dev;
26
27 for_each_possible_cpu(cpu_id) {
28 dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
29 cpuidle_unregister_device(dev);
30 }
31
32 free_percpu(imx_cpuidle_devices);
33}
34
35int __init imx_cpuidle_init(struct cpuidle_driver *drv)
36{
37 struct cpuidle_device *dev;
38 int cpu_id, ret;
39
40 if (drv->state_count > CPUIDLE_STATE_MAX) {
41 pr_err("%s: state_count exceeds maximum\n", __func__);
42 return -EINVAL;
43 }
44
45 ret = cpuidle_register_driver(drv);
46 if (ret) {
47 pr_err("%s: Failed to register cpuidle driver with error: %d\n",
48 __func__, ret);
49 return ret;
50 }
51
52 imx_cpuidle_devices = alloc_percpu(struct cpuidle_device);
53 if (imx_cpuidle_devices == NULL) {
54 ret = -ENOMEM;
55 goto unregister_drv;
56 }
57
58 /* initialize state data for each cpuidle_device */
59 for_each_possible_cpu(cpu_id) {
60 dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
61 dev->cpu = cpu_id;
62 dev->state_count = drv->state_count;
63
64 ret = cpuidle_register_device(dev);
65 if (ret) {
66 pr_err("%s: Failed to register cpu %u, error: %d\n",
67 __func__, cpu_id, ret);
68 goto uninit;
69 }
70 }
71
72 return 0;
73
74uninit:
75 imx_cpuidle_devices_uninit();
76
77unregister_drv:
78 cpuidle_unregister_driver(drv);
79 return ret;
80}
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c
new file mode 100644
index 000000000000..88726f4dbbfa
--- /dev/null
+++ b/arch/arm/mach-imx/epit.c
@@ -0,0 +1,234 @@
1/*
2 * linux/arch/arm/plat-mxc/epit.c
3 *
4 * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#define EPITCR 0x00
22#define EPITSR 0x04
23#define EPITLR 0x08
24#define EPITCMPR 0x0c
25#define EPITCNR 0x10
26
27#define EPITCR_EN (1 << 0)
28#define EPITCR_ENMOD (1 << 1)
29#define EPITCR_OCIEN (1 << 2)
30#define EPITCR_RLD (1 << 3)
31#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
32#define EPITCR_SWR (1 << 16)
33#define EPITCR_IOVW (1 << 17)
34#define EPITCR_DBGEN (1 << 18)
35#define EPITCR_WAITEN (1 << 19)
36#define EPITCR_RES (1 << 20)
37#define EPITCR_STOPEN (1 << 21)
38#define EPITCR_OM_DISCON (0 << 22)
39#define EPITCR_OM_TOGGLE (1 << 22)
40#define EPITCR_OM_CLEAR (2 << 22)
41#define EPITCR_OM_SET (3 << 22)
42#define EPITCR_CLKSRC_OFF (0 << 24)
43#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
44#define EPITCR_CLKSRC_REF_HIGH (1 << 24)
45#define EPITCR_CLKSRC_REF_LOW (3 << 24)
46
47#define EPITSR_OCIF (1 << 0)
48
49#include <linux/interrupt.h>
50#include <linux/irq.h>
51#include <linux/clockchips.h>
52#include <linux/clk.h>
53#include <linux/err.h>
54
55#include <mach/hardware.h>
56#include <asm/mach/time.h>
57#include <mach/common.h>
58
59static struct clock_event_device clockevent_epit;
60static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
61
62static void __iomem *timer_base;
63
64static inline void epit_irq_disable(void)
65{
66 u32 val;
67
68 val = __raw_readl(timer_base + EPITCR);
69 val &= ~EPITCR_OCIEN;
70 __raw_writel(val, timer_base + EPITCR);
71}
72
73static inline void epit_irq_enable(void)
74{
75 u32 val;
76
77 val = __raw_readl(timer_base + EPITCR);
78 val |= EPITCR_OCIEN;
79 __raw_writel(val, timer_base + EPITCR);
80}
81
82static void epit_irq_acknowledge(void)
83{
84 __raw_writel(EPITSR_OCIF, timer_base + EPITSR);
85}
86
87static int __init epit_clocksource_init(struct clk *timer_clk)
88{
89 unsigned int c = clk_get_rate(timer_clk);
90
91 return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32,
92 clocksource_mmio_readl_down);
93}
94
95/* clock event */
96
97static int epit_set_next_event(unsigned long evt,
98 struct clock_event_device *unused)
99{
100 unsigned long tcmp;
101
102 tcmp = __raw_readl(timer_base + EPITCNR);
103
104 __raw_writel(tcmp - evt, timer_base + EPITCMPR);
105
106 return 0;
107}
108
109static void epit_set_mode(enum clock_event_mode mode,
110 struct clock_event_device *evt)
111{
112 unsigned long flags;
113
114 /*
115 * The timer interrupt generation is disabled at least
116 * for enough time to call epit_set_next_event()
117 */
118 local_irq_save(flags);
119
120 /* Disable interrupt in GPT module */
121 epit_irq_disable();
122
123 if (mode != clockevent_mode) {
124 /* Set event time into far-far future */
125
126 /* Clear pending interrupt */
127 epit_irq_acknowledge();
128 }
129
130 /* Remember timer mode */
131 clockevent_mode = mode;
132 local_irq_restore(flags);
133
134 switch (mode) {
135 case CLOCK_EVT_MODE_PERIODIC:
136 printk(KERN_ERR "epit_set_mode: Periodic mode is not "
137 "supported for i.MX EPIT\n");
138 break;
139 case CLOCK_EVT_MODE_ONESHOT:
140 /*
141 * Do not put overhead of interrupt enable/disable into
142 * epit_set_next_event(), the core has about 4 minutes
143 * to call epit_set_next_event() or shutdown clock after
144 * mode switching
145 */
146 local_irq_save(flags);
147 epit_irq_enable();
148 local_irq_restore(flags);
149 break;
150 case CLOCK_EVT_MODE_SHUTDOWN:
151 case CLOCK_EVT_MODE_UNUSED:
152 case CLOCK_EVT_MODE_RESUME:
153 /* Left event sources disabled, no more interrupts appear */
154 break;
155 }
156}
157
158/*
159 * IRQ handler for the timer
160 */
161static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
162{
163 struct clock_event_device *evt = &clockevent_epit;
164
165 epit_irq_acknowledge();
166
167 evt->event_handler(evt);
168
169 return IRQ_HANDLED;
170}
171
172static struct irqaction epit_timer_irq = {
173 .name = "i.MX EPIT Timer Tick",
174 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
175 .handler = epit_timer_interrupt,
176};
177
178static struct clock_event_device clockevent_epit = {
179 .name = "epit",
180 .features = CLOCK_EVT_FEAT_ONESHOT,
181 .shift = 32,
182 .set_mode = epit_set_mode,
183 .set_next_event = epit_set_next_event,
184 .rating = 200,
185};
186
187static int __init epit_clockevent_init(struct clk *timer_clk)
188{
189 unsigned int c = clk_get_rate(timer_clk);
190
191 clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
192 clockevent_epit.shift);
193 clockevent_epit.max_delta_ns =
194 clockevent_delta2ns(0xfffffffe, &clockevent_epit);
195 clockevent_epit.min_delta_ns =
196 clockevent_delta2ns(0x800, &clockevent_epit);
197
198 clockevent_epit.cpumask = cpumask_of(0);
199
200 clockevents_register_device(&clockevent_epit);
201
202 return 0;
203}
204
205void __init epit_timer_init(void __iomem *base, int irq)
206{
207 struct clk *timer_clk;
208
209 timer_clk = clk_get_sys("imx-epit.0", NULL);
210 if (IS_ERR(timer_clk)) {
211 pr_err("i.MX epit: unable to get clk\n");
212 return;
213 }
214
215 clk_prepare_enable(timer_clk);
216
217 timer_base = base;
218
219 /*
220 * Initialise to a known state (all timers off, and timing reset)
221 */
222 __raw_writel(0x0, timer_base + EPITCR);
223
224 __raw_writel(0xffffffff, timer_base + EPITLR);
225 __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
226 timer_base + EPITCR);
227
228 /* init and register the timer to the framework */
229 epit_clocksource_init(timer_clk);
230 epit_clockevent_init(timer_clk);
231
232 /* Make irqs happen */
233 setup_irq(irq, &epit_timer_irq);
234}
diff --git a/arch/arm/mach-imx/include/mach/common.h b/arch/arm/mach-imx/include/mach/common.h
new file mode 100644
index 000000000000..ead901814c0d
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/common.h
@@ -0,0 +1,162 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
14struct platform_device;
15struct clk;
16enum mxc_cpu_pwr_mode;
17
18extern void mx1_map_io(void);
19extern void mx21_map_io(void);
20extern void mx25_map_io(void);
21extern void mx27_map_io(void);
22extern void mx31_map_io(void);
23extern void mx35_map_io(void);
24extern void mx50_map_io(void);
25extern void mx51_map_io(void);
26extern void mx53_map_io(void);
27extern void imx1_init_early(void);
28extern void imx21_init_early(void);
29extern void imx25_init_early(void);
30extern void imx27_init_early(void);
31extern void imx31_init_early(void);
32extern void imx35_init_early(void);
33extern void imx50_init_early(void);
34extern void imx51_init_early(void);
35extern void imx53_init_early(void);
36extern void mxc_init_irq(void __iomem *);
37extern void tzic_init_irq(void __iomem *);
38extern void mx1_init_irq(void);
39extern void mx21_init_irq(void);
40extern void mx25_init_irq(void);
41extern void mx27_init_irq(void);
42extern void mx31_init_irq(void);
43extern void mx35_init_irq(void);
44extern void mx50_init_irq(void);
45extern void mx51_init_irq(void);
46extern void mx53_init_irq(void);
47extern void imx1_soc_init(void);
48extern void imx21_soc_init(void);
49extern void imx25_soc_init(void);
50extern void imx27_soc_init(void);
51extern void imx31_soc_init(void);
52extern void imx35_soc_init(void);
53extern void imx50_soc_init(void);
54extern void imx51_soc_init(void);
55extern void imx51_init_late(void);
56extern void imx53_init_late(void);
57extern void epit_timer_init(void __iomem *base, int irq);
58extern void mxc_timer_init(void __iomem *, int);
59extern int mx1_clocks_init(unsigned long fref);
60extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
61extern int mx25_clocks_init(void);
62extern int mx27_clocks_init(unsigned long fref);
63extern int mx31_clocks_init(unsigned long fref);
64extern int mx35_clocks_init(void);
65extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
66 unsigned long ckih1, unsigned long ckih2);
67extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
68 unsigned long ckih1, unsigned long ckih2);
69extern int mx27_clocks_init_dt(void);
70extern int mx31_clocks_init_dt(void);
71extern int mx51_clocks_init_dt(void);
72extern int mx53_clocks_init_dt(void);
73extern int mx6q_clocks_init(void);
74extern struct platform_device *mxc_register_gpio(char *name, int id,
75 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
76extern void mxc_set_cpu_type(unsigned int type);
77extern void mxc_restart(char, const char *);
78extern void mxc_arch_reset_init(void __iomem *);
79extern int mx53_revision(void);
80extern int mx53_display_revision(void);
81extern void imx_set_aips(void __iomem *);
82
83enum mxc_cpu_pwr_mode {
84 WAIT_CLOCKED, /* wfi only */
85 WAIT_UNCLOCKED, /* WAIT */
86 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
87 STOP_POWER_ON, /* just STOP */
88 STOP_POWER_OFF, /* STOP + SRPG */
89};
90
91enum mx3_cpu_pwr_mode {
92 MX3_RUN,
93 MX3_WAIT,
94 MX3_DOZE,
95 MX3_SLEEP,
96};
97
98extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
99extern void imx_print_silicon_rev(const char *cpu, int srev);
100
101void avic_handle_irq(struct pt_regs *);
102void tzic_handle_irq(struct pt_regs *);
103
104#define imx1_handle_irq avic_handle_irq
105#define imx21_handle_irq avic_handle_irq
106#define imx25_handle_irq avic_handle_irq
107#define imx27_handle_irq avic_handle_irq
108#define imx31_handle_irq avic_handle_irq
109#define imx35_handle_irq avic_handle_irq
110#define imx50_handle_irq tzic_handle_irq
111#define imx51_handle_irq tzic_handle_irq
112#define imx53_handle_irq tzic_handle_irq
113#define imx6q_handle_irq gic_handle_irq
114
115extern void imx_enable_cpu(int cpu, bool enable);
116extern void imx_set_cpu_jump(int cpu, void *jump_addr);
117#ifdef CONFIG_DEBUG_LL
118extern void imx_lluart_map_io(void);
119#else
120static inline void imx_lluart_map_io(void) {}
121#endif
122extern void v7_cpu_resume(void);
123extern u32 *pl310_get_save_ptr(void);
124#ifdef CONFIG_SMP
125extern void v7_secondary_startup(void);
126extern void imx_scu_map_io(void);
127extern void imx_smp_prepare(void);
128#else
129static inline void imx_scu_map_io(void) {}
130static inline void imx_smp_prepare(void) {}
131#endif
132extern void imx_enable_cpu(int cpu, bool enable);
133extern void imx_set_cpu_jump(int cpu, void *jump_addr);
134extern void imx_src_init(void);
135extern void imx_src_prepare_restart(void);
136extern void imx_gpc_init(void);
137extern void imx_gpc_pre_suspend(void);
138extern void imx_gpc_post_resume(void);
139extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
140extern void imx6q_clock_map_io(void);
141
142extern void imx_cpu_die(unsigned int cpu);
143
144#ifdef CONFIG_PM
145extern void imx6q_pm_init(void);
146extern void imx51_pm_init(void);
147extern void imx53_pm_init(void);
148#else
149static inline void imx6q_pm_init(void) {}
150static inline void imx51_pm_init(void) {}
151static inline void imx53_pm_init(void) {}
152#endif
153
154#ifdef CONFIG_NEON
155extern int mx51_neon_fixup(void);
156#else
157static inline int mx51_neon_fixup(void) { return 0; }
158#endif
159
160extern struct smp_operations imx_smp_ops;
161
162#endif
diff --git a/arch/arm/mach-imx/include/mach/cpuidle.h b/arch/arm/mach-imx/include/mach/cpuidle.h
new file mode 100644
index 000000000000..bc932d1af372
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/cpuidle.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/cpuidle.h>
14
15#ifdef CONFIG_CPU_IDLE
16extern int imx_cpuidle_init(struct cpuidle_driver *drv);
17#else
18static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
19{
20 return -ENODEV;
21}
22#endif
diff --git a/arch/arm/mach-imx/include/mach/debug-macro.S b/arch/arm/mach-imx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..761e45f9456f
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/debug-macro.S
@@ -0,0 +1,51 @@
1/* arch/arm/mach-imx/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#include <mach/hardware.h>
14
15#ifdef CONFIG_DEBUG_IMX1_UART
16#define UART_PADDR MX1_UART1_BASE_ADDR
17#elif defined (CONFIG_DEBUG_IMX25_UART)
18#define UART_PADDR MX25_UART1_BASE_ADDR
19#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART)
20#define UART_PADDR MX2x_UART1_BASE_ADDR
21#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART)
22#define UART_PADDR MX3x_UART1_BASE_ADDR
23#elif defined (CONFIG_DEBUG_IMX51_UART)
24#define UART_PADDR MX51_UART1_BASE_ADDR
25#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
26#define UART_PADDR MX53_UART1_BASE_ADDR
27#elif defined (CONFIG_DEBUG_IMX6Q_UART2)
28#define UART_PADDR MX6Q_UART2_BASE_ADDR
29#elif defined (CONFIG_DEBUG_IMX6Q_UART4)
30#define UART_PADDR MX6Q_UART4_BASE_ADDR
31#endif
32
33#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
34
35 .macro addruart, rp, rv, tmp
36 ldr \rp, =UART_PADDR @ physical
37 ldr \rv, =UART_VADDR @ virtual
38 .endm
39
40 .macro senduart,rd,rx
41 str \rd, [\rx, #0x40] @ TXDATA
42 .endm
43
44 .macro waituart,rd,rx
45 .endm
46
47 .macro busyuart,rd,rx
481002: ldr \rd, [\rx, #0x98] @ SR2
49 tst \rd, #1 << 3 @ TXDC
50 beq 1002b @ wait until transmit done
51 .endm
diff --git a/arch/arm/mach-imx/include/mach/hardware.h b/arch/arm/mach-imx/include/mach/hardware.h
new file mode 100644
index 000000000000..ebf10654bb42
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/hardware.h
@@ -0,0 +1,134 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_HARDWARE_H__
21#define __ASM_ARCH_MXC_HARDWARE_H__
22
23#include <asm/sizes.h>
24
25#define addr_in_module(addr, mod) \
26 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
27
28#define IMX_IO_P2V_MODULE(addr, module) \
29 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
30 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
31
32/*
33 * This is rather complicated for humans and ugly to verify, but for a machine
34 * it's OK. Still more as it is usually only applied to constants. The upsides
35 * on using this approach are:
36 *
37 * - same mapping on all i.MX machines
38 * - works for assembler, too
39 * - no need to nurture #defines for virtual addresses
40 *
41 * The downside it, it's hard to verify (but I have a script for that).
42 *
43 * Obviously this needs to be injective for each SoC. In general it maps the
44 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
45 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
46 *
47 * It applies the following mappings for the different SoCs:
48 *
49 * mx1:
50 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
51 * mx21:
52 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
53 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
54 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
55 * mx25:
56 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
57 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
58 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
59 * mx27:
60 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
61 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
62 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
63 * mx31:
64 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
65 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
66 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
67 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
68 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
69 * mx35:
70 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
71 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
72 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
73 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
74 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
75 * mx50:
76 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
77 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
78 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
79 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
80 * mx51:
81 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
82 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
83 * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
84 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
85 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
86 * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000
87 * mx53:
88 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
89 * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000
90 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
91 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
92 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
93 * mx6q:
94 * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000
95 * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
96 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000
97 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
98 */
99#define IMX_IO_P2V(x) ( \
100 (((x) & 0x80000000) >> 7) | \
101 (0xf4000000 + \
102 (((x) & 0x50000000) >> 6) + \
103 (((x) & 0x0b000000) >> 4) + \
104 (((x) & 0x000fffff))))
105
106#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
107
108#include <mach/mxc.h>
109
110#include <mach/mx6q.h>
111#include <mach/mx50.h>
112#include <mach/mx51.h>
113#include <mach/mx53.h>
114#include <mach/mx3x.h>
115#include <mach/mx31.h>
116#include <mach/mx35.h>
117#include <mach/mx2x.h>
118#include <mach/mx21.h>
119#include <mach/mx27.h>
120#include <mach/mx1.h>
121#include <mach/mx25.h>
122
123#define imx_map_entry(soc, name, _type) { \
124 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
125 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
126 .length = soc ## _ ## name ## _SIZE, \
127 .type = _type, \
128}
129
130/* There's a off-by-one betweem the gpio bank number and the gpiochip */
131/* range e.g. GPIO_1_5 is gpio 5 under linux */
132#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
133
134#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/mach-imx/include/mach/iim.h b/arch/arm/mach-imx/include/mach/iim.h
new file mode 100644
index 000000000000..315bffadafda
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iim.h
@@ -0,0 +1,77 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_IIM_H__
21#define __ASM_ARCH_MXC_IIM_H__
22
23/* Register offsets */
24#define MXC_IIMSTAT 0x0000
25#define MXC_IIMSTATM 0x0004
26#define MXC_IIMERR 0x0008
27#define MXC_IIMEMASK 0x000C
28#define MXC_IIMFCTL 0x0010
29#define MXC_IIMUA 0x0014
30#define MXC_IIMLA 0x0018
31#define MXC_IIMSDAT 0x001C
32#define MXC_IIMPREV 0x0020
33#define MXC_IIMSREV 0x0024
34#define MXC_IIMPRG_P 0x0028
35#define MXC_IIMSCS0 0x002C
36#define MXC_IIMSCS1 0x0030
37#define MXC_IIMSCS2 0x0034
38#define MXC_IIMSCS3 0x0038
39#define MXC_IIMFBAC0 0x0800
40#define MXC_IIMJAC 0x0804
41#define MXC_IIMHWV1 0x0808
42#define MXC_IIMHWV2 0x080C
43#define MXC_IIMHAB0 0x0810
44#define MXC_IIMHAB1 0x0814
45/* Definitions for i.MX27 TO2 */
46#define MXC_IIMMAC 0x0814
47#define MXC_IIMPREV_FUSE 0x0818
48#define MXC_IIMSREV_FUSE 0x081C
49#define MXC_IIMSJC_CHALL_0 0x0820
50#define MXC_IIMSJC_CHALL_7 0x083C
51#define MXC_IIMFB0UC17 0x0840
52#define MXC_IIMFB0UC255 0x0BFC
53#define MXC_IIMFBAC1 0x0C00
54/* Definitions for i.MX27 TO2 */
55#define MXC_IIMSUID 0x0C04
56#define MXC_IIMKEY0 0x0C04
57#define MXC_IIMKEY20 0x0C54
58#define MXC_IIMSJC_RESP_0 0x0C58
59#define MXC_IIMSJC_RESP_7 0x0C74
60#define MXC_IIMFB1UC30 0x0C78
61#define MXC_IIMFB1UC255 0x0FFC
62
63/* Bit definitions */
64
65#define MXC_IIMHWV1_WLOCK (0x1 << 7)
66#define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6)
67#define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5)
68#define MXC_IIMHWV1_BOOT_INT (0x1 << 4)
69#define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3)
70#define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2)
71#define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1)
72
73#define MXC_IIMHWV2_WLOCK (0x1 << 7)
74#define MXC_IIMHWV2_BP_SDMA (0x1 << 6)
75#define MXC_IIMHWV2_SCM_DCM (0x1 << 5)
76
77#endif /* __ASM_ARCH_MXC_IIM_H__ */
diff --git a/arch/arm/mach-imx/include/mach/ipu.h b/arch/arm/mach-imx/include/mach/ipu.h
new file mode 100644
index 000000000000..539e559d18b2
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/ipu.h
@@ -0,0 +1,177 @@
1/*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _IPU_H_
13#define _IPU_H_
14
15#include <linux/types.h>
16#include <linux/dmaengine.h>
17
18/* IPU DMA Controller channel definitions. */
19enum ipu_channel {
20 IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
21 IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
22 IDMAC_ADC_0 = 1,
23 IDMAC_IC_2 = 2,
24 IDMAC_ADC_1 = 2,
25 IDMAC_IC_3 = 3,
26 IDMAC_IC_4 = 4,
27 IDMAC_IC_5 = 5,
28 IDMAC_IC_6 = 6,
29 IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
30 IDMAC_IC_8 = 8,
31 IDMAC_IC_9 = 9,
32 IDMAC_IC_10 = 10,
33 IDMAC_IC_11 = 11,
34 IDMAC_IC_12 = 12,
35 IDMAC_IC_13 = 13,
36 IDMAC_SDC_0 = 14, /* Background synchronous display data */
37 IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
38 IDMAC_SDC_2 = 16,
39 IDMAC_SDC_3 = 17,
40 IDMAC_ADC_2 = 18,
41 IDMAC_ADC_3 = 19,
42 IDMAC_ADC_4 = 20,
43 IDMAC_ADC_5 = 21,
44 IDMAC_ADC_6 = 22,
45 IDMAC_ADC_7 = 23,
46 IDMAC_PF_0 = 24,
47 IDMAC_PF_1 = 25,
48 IDMAC_PF_2 = 26,
49 IDMAC_PF_3 = 27,
50 IDMAC_PF_4 = 28,
51 IDMAC_PF_5 = 29,
52 IDMAC_PF_6 = 30,
53 IDMAC_PF_7 = 31,
54};
55
56/* Order significant! */
57enum ipu_channel_status {
58 IPU_CHANNEL_FREE,
59 IPU_CHANNEL_INITIALIZED,
60 IPU_CHANNEL_READY,
61 IPU_CHANNEL_ENABLED,
62};
63
64#define IPU_CHANNELS_NUM 32
65
66enum pixel_fmt {
67 /* 1 byte */
68 IPU_PIX_FMT_GENERIC,
69 IPU_PIX_FMT_RGB332,
70 IPU_PIX_FMT_YUV420P,
71 IPU_PIX_FMT_YUV422P,
72 IPU_PIX_FMT_YUV420P2,
73 IPU_PIX_FMT_YVU422P,
74 /* 2 bytes */
75 IPU_PIX_FMT_RGB565,
76 IPU_PIX_FMT_RGB666,
77 IPU_PIX_FMT_BGR666,
78 IPU_PIX_FMT_YUYV,
79 IPU_PIX_FMT_UYVY,
80 /* 3 bytes */
81 IPU_PIX_FMT_RGB24,
82 IPU_PIX_FMT_BGR24,
83 /* 4 bytes */
84 IPU_PIX_FMT_GENERIC_32,
85 IPU_PIX_FMT_RGB32,
86 IPU_PIX_FMT_BGR32,
87 IPU_PIX_FMT_ABGR32,
88 IPU_PIX_FMT_BGRA32,
89 IPU_PIX_FMT_RGBA32,
90};
91
92enum ipu_color_space {
93 IPU_COLORSPACE_RGB,
94 IPU_COLORSPACE_YCBCR,
95 IPU_COLORSPACE_YUV
96};
97
98/*
99 * Enumeration of IPU rotation modes
100 */
101enum ipu_rotate_mode {
102 /* Note the enum values correspond to BAM value */
103 IPU_ROTATE_NONE = 0,
104 IPU_ROTATE_VERT_FLIP = 1,
105 IPU_ROTATE_HORIZ_FLIP = 2,
106 IPU_ROTATE_180 = 3,
107 IPU_ROTATE_90_RIGHT = 4,
108 IPU_ROTATE_90_RIGHT_VFLIP = 5,
109 IPU_ROTATE_90_RIGHT_HFLIP = 6,
110 IPU_ROTATE_90_LEFT = 7,
111};
112
113/*
114 * Enumeration of DI ports for ADC.
115 */
116enum display_port {
117 DISP0,
118 DISP1,
119 DISP2,
120 DISP3
121};
122
123struct idmac_video_param {
124 unsigned short in_width;
125 unsigned short in_height;
126 uint32_t in_pixel_fmt;
127 unsigned short out_width;
128 unsigned short out_height;
129 uint32_t out_pixel_fmt;
130 unsigned short out_stride;
131 bool graphics_combine_en;
132 bool global_alpha_en;
133 bool key_color_en;
134 enum display_port disp;
135 unsigned short out_left;
136 unsigned short out_top;
137};
138
139/*
140 * Union of initialization parameters for a logical channel. So far only video
141 * parameters are used.
142 */
143union ipu_channel_param {
144 struct idmac_video_param video;
145};
146
147struct idmac_tx_desc {
148 struct dma_async_tx_descriptor txd;
149 struct scatterlist *sg; /* scatterlist for this */
150 unsigned int sg_len; /* tx-descriptor. */
151 struct list_head list;
152};
153
154struct idmac_channel {
155 struct dma_chan dma_chan;
156 dma_cookie_t completed; /* last completed cookie */
157 union ipu_channel_param params;
158 enum ipu_channel link; /* input channel, linked to the output */
159 enum ipu_channel_status status;
160 void *client; /* Only one client per channel */
161 unsigned int n_tx_desc;
162 struct idmac_tx_desc *desc; /* allocated tx-descriptors */
163 struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */
164 struct list_head free_list; /* free tx-descriptors */
165 struct list_head queue; /* queued tx-descriptors */
166 spinlock_t lock; /* protects sg[0,1], queue */
167 struct mutex chan_mutex; /* protects status, cookie, free_list */
168 bool sec_chan_en;
169 int active_buffer;
170 unsigned int eof_irq;
171 char eof_name[16]; /* EOF IRQ name for request_irq() */
172};
173
174#define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd)
175#define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan)
176
177#endif
diff --git a/arch/arm/mach-imx/include/mach/iram.h b/arch/arm/mach-imx/include/mach/iram.h
new file mode 100644
index 000000000000..022690c33702
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iram.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19#include <linux/errno.h>
20
21#ifdef CONFIG_IRAM_ALLOC
22
23int __init iram_init(unsigned long base, unsigned long size);
24void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
25void iram_free(unsigned long dma_addr, unsigned int size);
26
27#else
28
29static inline int __init iram_init(unsigned long base, unsigned long size)
30{
31 return -ENOMEM;
32}
33
34static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
35{
36 return NULL;
37}
38
39static inline void iram_free(unsigned long base, unsigned long size) {}
40
41#endif
diff --git a/arch/arm/mach-imx/include/mach/irqs.h b/arch/arm/mach-imx/include/mach/irqs.h
new file mode 100644
index 000000000000..d73f5e8ea9cb
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/irqs.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_IRQS_H__
12#define __ASM_ARCH_MXC_IRQS_H__
13
14extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
15
16/* all normal IRQs can be FIQs */
17#define FIQ_START 0
18/* switch between IRQ and FIQ */
19extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
20
21#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx1.h b/arch/arm/mach-imx/include/mach/mx1.h
new file mode 100644
index 000000000000..45bd31cc34d6
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx1.h
@@ -0,0 +1,172 @@
1/*
2 * Copyright (C) 1997,1998 Russell King
3 * Copyright (C) 1999 ARM Limited
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __MACH_MX1_H__
13#define __MACH_MX1_H__
14
15/*
16 * Memory map
17 */
18#define MX1_IO_BASE_ADDR 0x00200000
19#define MX1_IO_SIZE SZ_1M
20
21#define MX1_CS0_PHYS 0x10000000
22#define MX1_CS0_SIZE 0x02000000
23
24#define MX1_CS1_PHYS 0x12000000
25#define MX1_CS1_SIZE 0x01000000
26
27#define MX1_CS2_PHYS 0x13000000
28#define MX1_CS2_SIZE 0x01000000
29
30#define MX1_CS3_PHYS 0x14000000
31#define MX1_CS3_SIZE 0x01000000
32
33#define MX1_CS4_PHYS 0x15000000
34#define MX1_CS4_SIZE 0x01000000
35
36#define MX1_CS5_PHYS 0x16000000
37#define MX1_CS5_SIZE 0x01000000
38
39/*
40 * Register BASEs, based on OFFSETs
41 */
42#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
43#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
44#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
45#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
46#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
47#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
48#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
49#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
50#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
51#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
52#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
53#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
54#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
55#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
56#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
57#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
58#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
59#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
60#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
61#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
62#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
63#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
64#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
65#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
66#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
67#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
68#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
69#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
70#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
71#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
72#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
73#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
74#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
75
76/* macro to get at IO space when running virtually */
77#define MX1_IO_P2V(x) IMX_IO_P2V(x)
78#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
79
80/* fixed interrput numbers */
81#include <asm/irq.h>
82#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
83#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
84#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
85#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
86#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
87#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
88#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
89#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
90#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
91#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
92#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
93#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
94#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
95#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
96#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
97#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
98#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
99#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
100#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
101#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
102#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
103#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
104#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
105#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
106#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
107#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
108#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
109#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
110#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
111#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
112#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
113#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
114#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
115#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
116#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
117#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
118#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
119#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
120#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
121#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
122#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
123#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
124#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
125#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
126#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
127#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
128#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
129#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
130#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
131#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
132#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
133#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
134#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
135#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
136#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
137
138/* DMA */
139#define MX1_DMA_REQ_UART3_T 2
140#define MX1_DMA_REQ_UART3_R 3
141#define MX1_DMA_REQ_SSI2_T 4
142#define MX1_DMA_REQ_SSI2_R 5
143#define MX1_DMA_REQ_CSI_STAT 6
144#define MX1_DMA_REQ_CSI_R 7
145#define MX1_DMA_REQ_MSHC 8
146#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
147#define MX1_DMA_REQ_DSPA_DCT_DIN 10
148#define MX1_DMA_REQ_DSPA_MAC 11
149#define MX1_DMA_REQ_EXT 12
150#define MX1_DMA_REQ_SDHC 13
151#define MX1_DMA_REQ_SPI1_R 14
152#define MX1_DMA_REQ_SPI1_T 15
153#define MX1_DMA_REQ_SSI_T 16
154#define MX1_DMA_REQ_SSI_R 17
155#define MX1_DMA_REQ_ASP_DAC 18
156#define MX1_DMA_REQ_ASP_ADC 19
157#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
158#define MX1_DMA_REQ_SPI2_R 26
159#define MX1_DMA_REQ_SPI2_T 27
160#define MX1_DMA_REQ_UART2_T 28
161#define MX1_DMA_REQ_UART2_R 29
162#define MX1_DMA_REQ_UART1_T 30
163#define MX1_DMA_REQ_UART1_R 31
164
165/*
166 * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
167 * to not break drivers/usb/gadget/imx_udc. Should go
168 * away after this driver uses the new name.
169 */
170#define USBD_INT0 MX1_INT_USBD0
171
172#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx21.h b/arch/arm/mach-imx/include/mach/mx21.h
new file mode 100644
index 000000000000..468738aa997f
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx21.h
@@ -0,0 +1,189 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
5 *
6 * This contains i.MX21-specific hardware definitions. For those
7 * hardware pieces that are common between i.MX21 and i.MX27, have a
8 * look at mx2x.h.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#ifndef __MACH_MX21_H__
26#define __MACH_MX21_H__
27
28#define MX21_AIPI_BASE_ADDR 0x10000000
29#define MX21_AIPI_SIZE SZ_1M
30#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
31#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
32#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
33#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
34#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
35#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
36#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
37#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
38#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
39#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
40#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
41#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
42#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
43#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
44#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
45#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
46#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
47#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
48#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
49#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
50#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
51#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
52#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
53#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
54#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
55#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
56#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
57#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
58#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
59#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
60#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
61#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
62#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
63#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
64#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
65#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
66#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
67#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
68
69#define MX21_AVIC_BASE_ADDR 0x10040000
70
71#define MX21_SAHB1_BASE_ADDR 0x80000000
72#define MX21_SAHB1_SIZE SZ_1M
73#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
74
75/* Memory regions and CS */
76#define MX21_SDRAM_BASE_ADDR 0xc0000000
77#define MX21_CSD1_BASE_ADDR 0xc4000000
78
79#define MX21_CS0_BASE_ADDR 0xc8000000
80#define MX21_CS1_BASE_ADDR 0xcc000000
81#define MX21_CS2_BASE_ADDR 0xd0000000
82#define MX21_CS3_BASE_ADDR 0xd1000000
83#define MX21_CS4_BASE_ADDR 0xd2000000
84#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
85#define MX21_CS5_BASE_ADDR 0xdd000000
86
87/* NAND, SDRAM, WEIM etc controllers */
88#define MX21_X_MEMC_BASE_ADDR 0xdf000000
89#define MX21_X_MEMC_SIZE SZ_256K
90
91#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
92#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
93#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
94#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
95
96#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
97
98#define MX21_IO_P2V(x) IMX_IO_P2V(x)
99#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
100
101/* fixed interrupt numbers */
102#include <asm/irq.h>
103#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
104#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
105#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
106#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
107#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
108#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
109#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
110#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
111#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
112#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
113#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
114#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
115#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
116#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
117#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
118#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
119#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
120#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
121#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
122#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
123#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
124#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
125#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
126#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
127#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
128#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
129#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
130#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
131#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
132#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
133#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
134#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
135#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
136#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
137#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
138#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
139#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
140#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
141#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
142#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
143#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
144#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
145#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
146#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
147#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
148#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
149#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
150#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
151#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
152#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
153#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
154#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
155#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
156
157/* fixed DMA request numbers */
158#define MX21_DMA_REQ_CSPI3_RX 1
159#define MX21_DMA_REQ_CSPI3_TX 2
160#define MX21_DMA_REQ_EXT 3
161#define MX21_DMA_REQ_FIRI_RX 4
162#define MX21_DMA_REQ_SDHC2 6
163#define MX21_DMA_REQ_SDHC1 7
164#define MX21_DMA_REQ_SSI2_RX0 8
165#define MX21_DMA_REQ_SSI2_TX0 9
166#define MX21_DMA_REQ_SSI2_RX1 10
167#define MX21_DMA_REQ_SSI2_TX1 11
168#define MX21_DMA_REQ_SSI1_RX0 12
169#define MX21_DMA_REQ_SSI1_TX0 13
170#define MX21_DMA_REQ_SSI1_RX1 14
171#define MX21_DMA_REQ_SSI1_TX1 15
172#define MX21_DMA_REQ_CSPI2_RX 16
173#define MX21_DMA_REQ_CSPI2_TX 17
174#define MX21_DMA_REQ_CSPI1_RX 18
175#define MX21_DMA_REQ_CSPI1_TX 19
176#define MX21_DMA_REQ_UART4_RX 20
177#define MX21_DMA_REQ_UART4_TX 21
178#define MX21_DMA_REQ_UART3_RX 22
179#define MX21_DMA_REQ_UART3_TX 23
180#define MX21_DMA_REQ_UART2_RX 24
181#define MX21_DMA_REQ_UART2_TX 25
182#define MX21_DMA_REQ_UART1_RX 26
183#define MX21_DMA_REQ_UART1_TX 27
184#define MX21_DMA_REQ_BMI_TX 28
185#define MX21_DMA_REQ_BMI_RX 29
186#define MX21_DMA_REQ_CSI_STAT 30
187#define MX21_DMA_REQ_CSI_RX 31
188
189#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx25.h b/arch/arm/mach-imx/include/mach/mx25.h
new file mode 100644
index 000000000000..ec466400a200
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx25.h
@@ -0,0 +1,117 @@
1#ifndef __MACH_MX25_H__
2#define __MACH_MX25_H__
3
4#define MX25_AIPS1_BASE_ADDR 0x43f00000
5#define MX25_AIPS1_SIZE SZ_1M
6#define MX25_AIPS2_BASE_ADDR 0x53f00000
7#define MX25_AIPS2_SIZE SZ_1M
8#define MX25_AVIC_BASE_ADDR 0x68000000
9#define MX25_AVIC_SIZE SZ_1M
10
11#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
12#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
13#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
14#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
15#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
16#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
17#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
18
19#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
20#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
21#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
22#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
23#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
24#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
25#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
26#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
27#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
28#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
29#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
30
31#define MX25_UART1_BASE_ADDR 0x43f90000
32#define MX25_UART2_BASE_ADDR 0x43f94000
33#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
34#define MX25_UART3_BASE_ADDR 0x5000c000
35#define MX25_UART4_BASE_ADDR 0x50008000
36#define MX25_UART5_BASE_ADDR 0x5002c000
37
38#define MX25_CSPI3_BASE_ADDR 0x50004000
39#define MX25_CSPI2_BASE_ADDR 0x50010000
40#define MX25_FEC_BASE_ADDR 0x50038000
41#define MX25_SSI2_BASE_ADDR 0x50014000
42#define MX25_SSI1_BASE_ADDR 0x50034000
43#define MX25_NFC_BASE_ADDR 0xbb000000
44#define MX25_IIM_BASE_ADDR 0x53ff0000
45#define MX25_DRYICE_BASE_ADDR 0x53ffc000
46#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
47#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
48#define MX25_LCDC_BASE_ADDR 0x53fbc000
49#define MX25_KPP_BASE_ADDR 0x43fa8000
50#define MX25_SDMA_BASE_ADDR 0x53fd4000
51#define MX25_USB_BASE_ADDR 0x53ff4000
52#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
53/*
54 * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
55 * for the host controller. Early documentation drafts specified 0x400 and
56 * Freescale internal sources confirm only the latter value to work.
57 */
58#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
59#define MX25_CSI_BASE_ADDR 0x53ff8000
60
61#define MX25_IO_P2V(x) IMX_IO_P2V(x)
62#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
63
64/*
65 * Interrupt numbers
66 */
67#include <asm/irq.h>
68#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
69#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
70#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
71#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
72#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
73#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
74#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
75#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
76#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
77#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
78#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
79#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
80#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
81#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
82#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
83#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
84#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
85#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
86#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
87#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
88#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
89#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
90#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
91#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
92#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
93#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
94#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
95#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
96#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
97#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
98#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
99#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
100#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
101#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54)
102#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
103
104#define MX25_DMA_REQ_SSI2_RX1 22
105#define MX25_DMA_REQ_SSI2_TX1 23
106#define MX25_DMA_REQ_SSI2_RX0 24
107#define MX25_DMA_REQ_SSI2_TX0 25
108#define MX25_DMA_REQ_SSI1_RX1 26
109#define MX25_DMA_REQ_SSI1_TX1 27
110#define MX25_DMA_REQ_SSI1_RX0 28
111#define MX25_DMA_REQ_SSI1_TX0 29
112
113#ifndef __ASSEMBLY__
114extern int mx25_revision(void);
115#endif
116
117#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx27.h b/arch/arm/mach-imx/include/mach/mx27.h
new file mode 100644
index 000000000000..e074616d54ca
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx27.h
@@ -0,0 +1,238 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This contains i.MX27-specific hardware definitions. For those
6 * hardware pieces that are common between i.MX21 and i.MX27, have a
7 * look at mx2x.h.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24#ifndef __MACH_MX27_H__
25#define __MACH_MX27_H__
26
27#define MX27_AIPI_BASE_ADDR 0x10000000
28#define MX27_AIPI_SIZE SZ_1M
29#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
30#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
31#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
32#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
33#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
34#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
35#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
36#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
37#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
38#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
39#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
40#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
41#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
42#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
43#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
44#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
45#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
46#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
47#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
48#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
49#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
50#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
51#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
52#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
53#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
54#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
55#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
56#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
57#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
58#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
59#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
60#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
61#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
62#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
63#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
64#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
65#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
66#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
67#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
68#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
69#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
70#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
71#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
72#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
73#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
74#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
75#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
76#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
77#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
78#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
79#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
80#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
81#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
82#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
83#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
84#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
85#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
86
87#define MX27_AVIC_BASE_ADDR 0x10040000
88
89/* ROM patch */
90#define MX27_ROMP_BASE_ADDR 0x10041000
91
92#define MX27_SAHB1_BASE_ADDR 0x80000000
93#define MX27_SAHB1_SIZE SZ_1M
94#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
95#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
96
97/* Memory regions and CS */
98#define MX27_SDRAM_BASE_ADDR 0xa0000000
99#define MX27_CSD1_BASE_ADDR 0xb0000000
100
101#define MX27_CS0_BASE_ADDR 0xc0000000
102#define MX27_CS1_BASE_ADDR 0xc8000000
103#define MX27_CS2_BASE_ADDR 0xd0000000
104#define MX27_CS3_BASE_ADDR 0xd2000000
105#define MX27_CS4_BASE_ADDR 0xd4000000
106#define MX27_CS5_BASE_ADDR 0xd6000000
107
108/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
109#define MX27_X_MEMC_BASE_ADDR 0xd8000000
110#define MX27_X_MEMC_SIZE SZ_1M
111#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
112#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
113#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
114#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
115#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
116
117#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
118#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
119#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
120#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
121
122#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
123
124/* IRAM */
125#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
126
127#define MX27_IO_P2V(x) IMX_IO_P2V(x)
128#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
129
130/* fixed interrupt numbers */
131#include <asm/irq.h>
132#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
133#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
134#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
135#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
136#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
137#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
138#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
139#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
140#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
141#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
142#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
143#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
144#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
145#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
146#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
147#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
148#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
149#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
150#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
151#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
152#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
153#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
154#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
155#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
156#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
157#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
158#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
159#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
160#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
161#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
162#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
163#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
164#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
165#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
166#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
167#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
168#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
169#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
170#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
171#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
172#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
173#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
174#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
175#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
176#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
177#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
178#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
179#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
180#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
181#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
182#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
183#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
184#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
185#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
186#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
187#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
188#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
189#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
190#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
191#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
192#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
193#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
194#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
195
196/* fixed DMA request numbers */
197#define MX27_DMA_REQ_CSPI3_RX 1
198#define MX27_DMA_REQ_CSPI3_TX 2
199#define MX27_DMA_REQ_EXT 3
200#define MX27_DMA_REQ_MSHC 4
201#define MX27_DMA_REQ_SDHC2 6
202#define MX27_DMA_REQ_SDHC1 7
203#define MX27_DMA_REQ_SSI2_RX0 8
204#define MX27_DMA_REQ_SSI2_TX0 9
205#define MX27_DMA_REQ_SSI2_RX1 10
206#define MX27_DMA_REQ_SSI2_TX1 11
207#define MX27_DMA_REQ_SSI1_RX0 12
208#define MX27_DMA_REQ_SSI1_TX0 13
209#define MX27_DMA_REQ_SSI1_RX1 14
210#define MX27_DMA_REQ_SSI1_TX1 15
211#define MX27_DMA_REQ_CSPI2_RX 16
212#define MX27_DMA_REQ_CSPI2_TX 17
213#define MX27_DMA_REQ_CSPI1_RX 18
214#define MX27_DMA_REQ_CSPI1_TX 19
215#define MX27_DMA_REQ_UART4_RX 20
216#define MX27_DMA_REQ_UART4_TX 21
217#define MX27_DMA_REQ_UART3_RX 22
218#define MX27_DMA_REQ_UART3_TX 23
219#define MX27_DMA_REQ_UART2_RX 24
220#define MX27_DMA_REQ_UART2_TX 25
221#define MX27_DMA_REQ_UART1_RX 26
222#define MX27_DMA_REQ_UART1_TX 27
223#define MX27_DMA_REQ_ATA_TX 28
224#define MX27_DMA_REQ_ATA_RCV 29
225#define MX27_DMA_REQ_CSI_STAT 30
226#define MX27_DMA_REQ_CSI_RX 31
227#define MX27_DMA_REQ_UART5_TX 32
228#define MX27_DMA_REQ_UART5_RX 33
229#define MX27_DMA_REQ_UART6_TX 34
230#define MX27_DMA_REQ_UART6_RX 35
231#define MX27_DMA_REQ_SDHC3 36
232#define MX27_DMA_REQ_NFC 37
233
234#ifndef __ASSEMBLY__
235extern int mx27_revision(void);
236#endif
237
238#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx2x.h b/arch/arm/mach-imx/include/mach/mx2x.h
new file mode 100644
index 000000000000..11642f5b224c
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx2x.h
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This contains hardware definitions that are common between i.MX21 and
6 * i.MX27.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#ifndef __MACH_MX2x_H__
24#define __MACH_MX2x_H__
25
26/* The following addresses are common between i.MX21 and i.MX27 */
27
28/* Register offsets */
29#define MX2x_AIPI_BASE_ADDR 0x10000000
30#define MX2x_AIPI_SIZE SZ_1M
31#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
32#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
33#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
34#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
35#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
36#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
37#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
38#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
39#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
40#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
41#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
42#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
43#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
44#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
45#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
46#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
47#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
48#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
49#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
50#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
51#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
52#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
53#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
54#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
55#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
56#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
57#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
58#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
59#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
60#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
61#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
62#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
63
64#define MX2x_AVIC_BASE_ADDR 0x10040000
65
66#define MX2x_SAHB1_BASE_ADDR 0x80000000
67#define MX2x_SAHB1_SIZE SZ_1M
68#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
69
70/* fixed interrupt numbers */
71#include <asm/irq.h>
72#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
73#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
74#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
75#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
76#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
77#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
78#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
79#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
80#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
81#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
82#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
83#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
84#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
85#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
86#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
87#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
88#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
89#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
90#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
91#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
92#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
93#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
94#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
95#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
96#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
97#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
98#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
99#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
100#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
101#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
102#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
103#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
104#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
105#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
106#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
107#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
108#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
109#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
110#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
111#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
112#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
113#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
114#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
115
116/* fixed DMA request numbers */
117#define MX2x_DMA_REQ_CSPI3_RX 1
118#define MX2x_DMA_REQ_CSPI3_TX 2
119#define MX2x_DMA_REQ_EXT 3
120#define MX2x_DMA_REQ_SDHC2 6
121#define MX2x_DMA_REQ_SDHC1 7
122#define MX2x_DMA_REQ_SSI2_RX0 8
123#define MX2x_DMA_REQ_SSI2_TX0 9
124#define MX2x_DMA_REQ_SSI2_RX1 10
125#define MX2x_DMA_REQ_SSI2_TX1 11
126#define MX2x_DMA_REQ_SSI1_RX0 12
127#define MX2x_DMA_REQ_SSI1_TX0 13
128#define MX2x_DMA_REQ_SSI1_RX1 14
129#define MX2x_DMA_REQ_SSI1_TX1 15
130#define MX2x_DMA_REQ_CSPI2_RX 16
131#define MX2x_DMA_REQ_CSPI2_TX 17
132#define MX2x_DMA_REQ_CSPI1_RX 18
133#define MX2x_DMA_REQ_CSPI1_TX 19
134#define MX2x_DMA_REQ_UART4_RX 20
135#define MX2x_DMA_REQ_UART4_TX 21
136#define MX2x_DMA_REQ_UART3_RX 22
137#define MX2x_DMA_REQ_UART3_TX 23
138#define MX2x_DMA_REQ_UART2_RX 24
139#define MX2x_DMA_REQ_UART2_TX 25
140#define MX2x_DMA_REQ_UART1_RX 26
141#define MX2x_DMA_REQ_UART1_TX 27
142#define MX2x_DMA_REQ_CSI_STAT 30
143#define MX2x_DMA_REQ_CSI_RX 31
144
145#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx31.h b/arch/arm/mach-imx/include/mach/mx31.h
new file mode 100644
index 000000000000..ee9b1f9215df
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx31.h
@@ -0,0 +1,196 @@
1#ifndef __MACH_MX31_H__
2#define __MACH_MX31_H__
3
4/*
5 * IRAM
6 */
7#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
8#define MX31_IRAM_SIZE SZ_16K
9
10#define MX31_L2CC_BASE_ADDR 0x30000000
11#define MX31_L2CC_SIZE SZ_1M
12
13#define MX31_AIPS1_BASE_ADDR 0x43f00000
14#define MX31_AIPS1_SIZE SZ_1M
15#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
16#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
17#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
18#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
19#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
20#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
21#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
22#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
23#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
24#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
25#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
26#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
27#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
28#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
29#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
30#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
31#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
32#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
33#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
34#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
35#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
36#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
37#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
38#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
39#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
40
41#define MX31_SPBA0_BASE_ADDR 0x50000000
42#define MX31_SPBA0_SIZE SZ_1M
43#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
44#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
45#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
46#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
47#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
48#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
49#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
50#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
51#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
52#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
53
54#define MX31_AIPS2_BASE_ADDR 0x53f00000
55#define MX31_AIPS2_SIZE SZ_1M
56#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
57#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
58#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
59#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
60#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
61#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
62#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
63#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
64#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
65#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
66#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
67#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
68#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
69#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
70#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
71#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
72#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
73#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
74#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
75#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
76#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
77
78#define MX31_ROMP_BASE_ADDR 0x60000000
79#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
80#define MX31_ROMP_SIZE SZ_1M
81
82#define MX31_AVIC_BASE_ADDR 0x68000000
83#define MX31_AVIC_SIZE SZ_1M
84
85#define MX31_IPU_MEM_BASE_ADDR 0x70000000
86#define MX31_CSD0_BASE_ADDR 0x80000000
87#define MX31_CSD1_BASE_ADDR 0x90000000
88
89#define MX31_CS0_BASE_ADDR 0xa0000000
90#define MX31_CS1_BASE_ADDR 0xa8000000
91#define MX31_CS2_BASE_ADDR 0xb0000000
92#define MX31_CS3_BASE_ADDR 0xb2000000
93
94#define MX31_CS4_BASE_ADDR 0xb4000000
95#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
96#define MX31_CS4_SIZE SZ_32M
97
98#define MX31_CS5_BASE_ADDR 0xb6000000
99#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
100#define MX31_CS5_SIZE SZ_32M
101
102#define MX31_X_MEMC_BASE_ADDR 0xb8000000
103#define MX31_X_MEMC_SIZE SZ_64K
104#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
105#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
106#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
107#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
108#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
109#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
110
111#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
112#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
113#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
114#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
115
116#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
117
118#define MX31_IO_P2V(x) IMX_IO_P2V(x)
119#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
120
121/*
122 * Interrupt numbers
123 */
124#include <asm/irq.h>
125#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
126#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
127#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
128#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
129#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
130#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
131#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
132#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
133#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
134#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
135#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
136#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
137#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
138#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
139#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
140#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
141#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
142#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
143#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
144#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
145#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
146#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
147#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
148#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
149#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
150#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
151#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
152#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
153#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
154#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
155#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
156#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
157#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
158#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
159#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
160#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
161#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
162#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
163#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
164#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
165#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
166#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
167#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
168#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
169#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
170#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
171#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
172#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
173#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
174#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
175#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
176#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
177#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
178#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
179#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
180#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
181#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
182
183#define MX31_DMA_REQ_SDHC1 20
184#define MX31_DMA_REQ_SDHC2 21
185#define MX31_DMA_REQ_SSI2_RX1 22
186#define MX31_DMA_REQ_SSI2_TX1 23
187#define MX31_DMA_REQ_SSI2_RX0 24
188#define MX31_DMA_REQ_SSI2_TX0 25
189#define MX31_DMA_REQ_SSI1_RX1 26
190#define MX31_DMA_REQ_SSI1_TX1 27
191#define MX31_DMA_REQ_SSI1_RX0 28
192#define MX31_DMA_REQ_SSI1_TX0 29
193
194#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
195
196#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx35.h b/arch/arm/mach-imx/include/mach/mx35.h
new file mode 100644
index 000000000000..2af5d3a699c7
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx35.h
@@ -0,0 +1,190 @@
1#ifndef __MACH_MX35_H__
2#define __MACH_MX35_H__
3
4/*
5 * IRAM
6 */
7#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
8#define MX35_IRAM_SIZE SZ_128K
9
10#define MX35_L2CC_BASE_ADDR 0x30000000
11#define MX35_L2CC_SIZE SZ_1M
12
13#define MX35_AIPS1_BASE_ADDR 0x43f00000
14#define MX35_AIPS1_SIZE SZ_1M
15#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
16#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
17#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
21#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
25#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
26#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
27#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
28#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
29#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
30#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
31#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
32#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
33
34#define MX35_SPBA0_BASE_ADDR 0x50000000
35#define MX35_SPBA0_SIZE SZ_1M
36#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
37#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
38#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
39#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
40#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
41#define MX35_FEC_BASE_ADDR 0x50038000
42#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
43
44#define MX35_AIPS2_BASE_ADDR 0x53f00000
45#define MX35_AIPS2_SIZE SZ_1M
46#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
47#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
48#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
49#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
50#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
51#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
52#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
53#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
54#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
55#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
56#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
57#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
58#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
59#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
60#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
61#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
62#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
63#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
64#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
65#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
66#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
67#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
68#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
69#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
70/*
71 * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
72 * HS. When host support was implemented only a preliminary document was
73 * available, which told 0x400. This works fine.
74 */
75#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
76
77#define MX35_ROMP_BASE_ADDR 0x60000000
78#define MX35_ROMP_SIZE SZ_1M
79
80#define MX35_AVIC_BASE_ADDR 0x68000000
81#define MX35_AVIC_SIZE SZ_1M
82
83/*
84 * Memory regions and CS
85 */
86#define MX35_IPU_MEM_BASE_ADDR 0x70000000
87#define MX35_CSD0_BASE_ADDR 0x80000000
88#define MX35_CSD1_BASE_ADDR 0x90000000
89
90#define MX35_CS0_BASE_ADDR 0xa0000000
91#define MX35_CS1_BASE_ADDR 0xa8000000
92#define MX35_CS2_BASE_ADDR 0xb0000000
93#define MX35_CS3_BASE_ADDR 0xb2000000
94
95#define MX35_CS4_BASE_ADDR 0xb4000000
96#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
97#define MX35_CS4_SIZE SZ_32M
98
99#define MX35_CS5_BASE_ADDR 0xb6000000
100#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
101#define MX35_CS5_SIZE SZ_32M
102
103/*
104 * NAND, SDRAM, WEIM, M3IF, EMI controllers
105 */
106#define MX35_X_MEMC_BASE_ADDR 0xb8000000
107#define MX35_X_MEMC_SIZE SZ_64K
108#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
109#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
110#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
111#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
112#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
113
114#define MX35_NFC_BASE_ADDR 0xbb000000
115#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
116
117#define MX35_IO_P2V(x) IMX_IO_P2V(x)
118#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
119
120/*
121 * Interrupt numbers
122 */
123#include <asm/irq.h>
124#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
125#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
126#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
127#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
128#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
129#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
130#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
131#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
132#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
133#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
134#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
135#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
136#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
137#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
138#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
139#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
140#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
141#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
142#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
143#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
144#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
145#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
146#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
147#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
148#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
149#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
150#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
151#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
152#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
153#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
154#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
155#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
156#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
157#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
158#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
159#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
160#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
161#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
162#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
163#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
164#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
165#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
166#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
167#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
168#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
169#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
170#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
171#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
172#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
173#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
174#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
175#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
176#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
177#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
178
179#define MX35_DMA_REQ_SSI2_RX1 22
180#define MX35_DMA_REQ_SSI2_TX1 23
181#define MX35_DMA_REQ_SSI2_RX0 24
182#define MX35_DMA_REQ_SSI2_TX0 25
183#define MX35_DMA_REQ_SSI1_RX1 26
184#define MX35_DMA_REQ_SSI1_TX1 27
185#define MX35_DMA_REQ_SSI1_RX0 28
186#define MX35_DMA_REQ_SSI1_TX0 29
187
188#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
189
190#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx3x.h b/arch/arm/mach-imx/include/mach/mx3x.h
new file mode 100644
index 000000000000..96fb4fbc8ad7
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx3x.h
@@ -0,0 +1,195 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_MX3x_H__
12#define __MACH_MX3x_H__
13
14/*
15 * MX31 memory map:
16 *
17 * Virt Phys Size What
18 * ---------------------------------------------------------------------------
19 * FC000000 43F00000 1M AIPS 1
20 * FC100000 50000000 1M SPBA
21 * FC200000 53F00000 1M AIPS 2
22 * FC500000 60000000 128M ROMPATCH
23 * FC400000 68000000 128M AVIC
24 * 70000000 256M IPU (MAX M2)
25 * 80000000 256M CSD0 SDRAM/DDR
26 * 90000000 256M CSD1 SDRAM/DDR
27 * A0000000 128M CS0 Flash
28 * A8000000 128M CS1 Flash
29 * B0000000 32M CS2
30 * B2000000 32M CS3
31 * F4000000 B4000000 32M CS4
32 * B6000000 32M CS5
33 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
34 * C0000000 64M PCMCIA/CF
35 */
36
37/*
38 * L2CC
39 */
40#define MX3x_L2CC_BASE_ADDR 0x30000000
41#define MX3x_L2CC_SIZE SZ_1M
42
43/*
44 * AIPS 1
45 */
46#define MX3x_AIPS1_BASE_ADDR 0x43f00000
47#define MX3x_AIPS1_SIZE SZ_1M
48#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
49#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
50#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
51#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
52#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
53#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
54#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
55#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
56#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
57#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
58#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
59#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
60#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
61#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
62#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
63#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
64#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
65#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
66
67/*
68 * SPBA global module enabled #0
69 */
70#define MX3x_SPBA0_BASE_ADDR 0x50000000
71#define MX3x_SPBA0_SIZE SZ_1M
72#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
73#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
74#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
75#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
76#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
77#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
78
79/*
80 * AIPS 2
81 */
82#define MX3x_AIPS2_BASE_ADDR 0x53f00000
83#define MX3x_AIPS2_SIZE SZ_1M
84#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
85#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
86#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
87#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
88#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
89#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
90#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
91#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
92#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
93#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
94#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
95#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
96#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
97#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
98#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
99#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
100
101/*
102 * ROMP and AVIC
103 */
104#define MX3x_ROMP_BASE_ADDR 0x60000000
105#define MX3x_ROMP_SIZE SZ_1M
106
107#define MX3x_AVIC_BASE_ADDR 0x68000000
108#define MX3x_AVIC_SIZE SZ_1M
109
110/*
111 * Memory regions and CS
112 */
113#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
114#define MX3x_CSD0_BASE_ADDR 0x80000000
115#define MX3x_CSD1_BASE_ADDR 0x90000000
116
117#define MX3x_CS0_BASE_ADDR 0xa0000000
118#define MX3x_CS1_BASE_ADDR 0xa8000000
119#define MX3x_CS2_BASE_ADDR 0xb0000000
120#define MX3x_CS3_BASE_ADDR 0xb2000000
121
122#define MX3x_CS4_BASE_ADDR 0xb4000000
123#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000
124#define MX3x_CS4_SIZE SZ_32M
125
126#define MX3x_CS5_BASE_ADDR 0xb6000000
127#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000
128#define MX3x_CS5_SIZE SZ_32M
129
130/*
131 * NAND, SDRAM, WEIM, M3IF, EMI controllers
132 */
133#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
134#define MX3x_X_MEMC_SIZE SZ_64K
135#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
136#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
137#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
138#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
139#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
140
141#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
142
143/*
144 * Interrupt numbers
145 */
146#include <asm/irq.h>
147#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)
148#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)
149#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)
150#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)
151#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)
152#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)
153#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)
154#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)
155#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)
156#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)
157#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23)
158#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24)
159#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25)
160#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26)
161#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27)
162#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28)
163#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29)
164#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
165#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32)
166#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33)
167#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34)
168#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39)
169#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
170#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
171#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45)
172#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48)
173#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
174#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
175#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51)
176#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52)
177#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55)
178#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56)
179#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
180#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
181#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
182#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
183#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
184#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63)
185
186#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
187
188/* Mandatory defines used globally */
189
190#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
191extern int mx35_revision(void);
192extern int mx31_revision(void);
193#endif
194
195#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx50.h b/arch/arm/mach-imx/include/mach/mx50.h
new file mode 100644
index 000000000000..09ac19c1570c
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx50.h
@@ -0,0 +1,290 @@
1#ifndef __MACH_MX50_H__
2#define __MACH_MX50_H__
3
4/*
5 * IROM
6 */
7#define MX50_IROM_BASE_ADDR 0x0
8#define MX50_IROM_SIZE SZ_64K
9
10/* TZIC */
11#define MX50_TZIC_BASE_ADDR 0x0fffc000
12#define MX50_TZIC_SIZE SZ_16K
13
14/*
15 * IRAM
16 */
17#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
18#define MX50_IRAM_PARTITIONS 16
19#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
20
21/*
22 * Databahn
23 */
24#define MX50_DATABAHN_BASE_ADDR 0x14000000
25
26/*
27 * Graphics Memory of GPU
28 */
29#define MX50_GPU2D_BASE_ADDR 0x20000000
30
31#define MX50_DEBUG_BASE_ADDR 0x40000000
32#define MX50_DEBUG_SIZE SZ_1M
33#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
34#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
35#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
36#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
37#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
38#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
39#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
40#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
41
42#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
43#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
44#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
45#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
46#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
47#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
48#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
49#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
50#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
51#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
52#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
53#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
54#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
55#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
56
57/*
58 * SPBA global module enabled #0
59 */
60#define MX50_SPBA0_BASE_ADDR 0x50000000
61#define MX50_SPBA0_SIZE SZ_1M
62
63#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
64#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
65#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
66#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
67#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
68#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
69#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
70
71/*
72 * AIPS 1
73 */
74#define MX50_AIPS1_BASE_ADDR 0x53f00000
75#define MX50_AIPS1_SIZE SZ_1M
76
77#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
78#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
79#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
80#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
81#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
82#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
83#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
84#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
85#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
86#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
87#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
88#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
89#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
90#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
91#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
92#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
93#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
94#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
95#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
96#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
97#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
98#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
99
100#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
101#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
102
103/*
104 * AIPS 2
105 */
106#define MX50_AIPS2_BASE_ADDR 0x63f00000
107#define MX50_AIPS2_SIZE SZ_1M
108
109#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
110#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
111#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
112#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
113#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
114#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
115#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
116#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
117#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
118#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
119#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
120#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
121#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
122#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
123#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
124#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
125#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
126
127/*
128 * Memory regions and CS
129 */
130#define MX50_CSD0_BASE_ADDR 0x70000000
131#define MX50_CSD1_BASE_ADDR 0xb0000000
132#define MX50_CS0_BASE_ADDR 0xf0000000
133
134#define MX50_IO_P2V(x) IMX_IO_P2V(x)
135#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
136
137/*
138 * defines for SPBA modules
139 */
140#define MX50_SPBA_SDHC1 0x04
141#define MX50_SPBA_SDHC2 0x08
142#define MX50_SPBA_UART3 0x0c
143#define MX50_SPBA_CSPI1 0x10
144#define MX50_SPBA_SSI2 0x14
145#define MX50_SPBA_SDHC3 0x20
146#define MX50_SPBA_SDHC4 0x24
147#define MX50_SPBA_SPDIF 0x28
148#define MX50_SPBA_ATA 0x30
149#define MX50_SPBA_SLIM 0x34
150#define MX50_SPBA_HSI2C 0x38
151#define MX50_SPBA_CTRL 0x3c
152
153/*
154 * DMA request assignments
155 */
156#define MX50_DMA_REQ_GPC 1
157#define MX50_DMA_REQ_ATA_UART4_RX 2
158#define MX50_DMA_REQ_ATA_UART4_TX 3
159#define MX50_DMA_REQ_CSPI1_RX 6
160#define MX50_DMA_REQ_CSPI1_TX 7
161#define MX50_DMA_REQ_CSPI2_RX 8
162#define MX50_DMA_REQ_CSPI2_TX 9
163#define MX50_DMA_REQ_I2C3_SDHC3 10
164#define MX50_DMA_REQ_SDHC4 11
165#define MX50_DMA_REQ_UART2_FIRI_RX 12
166#define MX50_DMA_REQ_UART2_FIRI_TX 13
167#define MX50_DMA_REQ_EXT0 14
168#define MX50_DMA_REQ_EXT1 15
169#define MX50_DMA_REQ_UART5_RX 16
170#define MX50_DMA_REQ_UART5_TX 17
171#define MX50_DMA_REQ_UART1_RX 18
172#define MX50_DMA_REQ_UART1_TX 19
173#define MX50_DMA_REQ_I2C1_SDHC1 20
174#define MX50_DMA_REQ_I2C2_SDHC2 21
175#define MX50_DMA_REQ_SSI2_RX2 22
176#define MX50_DMA_REQ_SSI2_TX2 23
177#define MX50_DMA_REQ_SSI2_RX1 24
178#define MX50_DMA_REQ_SSI2_TX1 25
179#define MX50_DMA_REQ_SSI1_RX2 26
180#define MX50_DMA_REQ_SSI1_TX2 27
181#define MX50_DMA_REQ_SSI1_RX1 28
182#define MX50_DMA_REQ_SSI1_TX1 29
183#define MX50_DMA_REQ_CSPI_RX 38
184#define MX50_DMA_REQ_CSPI_TX 39
185#define MX50_DMA_REQ_UART3_RX 42
186#define MX50_DMA_REQ_UART3_TX 43
187
188/*
189 * Interrupt numbers
190 */
191#include <asm/irq.h>
192#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
193#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
194#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
195#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
196#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
197#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
198#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
199#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
200#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
201#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
202#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
203#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
204#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
205#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
206#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
207#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
208#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
209#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
210#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
211#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
212#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
213#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
214#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
215#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
216#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
217#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
218#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
219#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
220#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
221#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
222#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
223#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
224#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
225#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
226#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
227#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
228#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
229#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
230#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
231#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
232#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
233#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
234#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
235#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
236#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
237#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
238#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
239#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
240#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
241#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
242#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
243#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
244#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
245#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
246#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
247#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
248#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
249#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
250#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
251#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
252#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
253#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
254#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
255#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
256#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
257#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
258#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
259#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
260#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
261#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
262#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
263#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
264#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
265#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
266#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
267#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
268#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
269#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
270#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
271#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
272#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
273#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
274#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
275#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
276#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
277#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
278#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
279#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
280#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
281#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
282#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
283#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
284#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
285
286#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
287extern int mx50_revision(void);
288#endif
289
290#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx51.h b/arch/arm/mach-imx/include/mach/mx51.h
new file mode 100644
index 000000000000..af844f76261a
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx51.h
@@ -0,0 +1,346 @@
1#ifndef __MACH_MX51_H__
2#define __MACH_MX51_H__
3
4/*
5 * IROM
6 */
7#define MX51_IROM_BASE_ADDR 0x0
8#define MX51_IROM_SIZE SZ_64K
9
10/*
11 * IRAM
12 */
13#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
14#define MX51_IRAM_PARTITIONS 16
15#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
16
17#define MX51_GPU_BASE_ADDR 0x20000000
18#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
19#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
20
21/*
22 * SPBA global module enabled #0
23 */
24#define MX51_SPBA0_BASE_ADDR 0x70000000
25#define MX51_SPBA0_SIZE SZ_1M
26
27#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
28#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
29#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
30#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
31#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
32#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
33#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
34#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
35#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
36#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
37#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000)
38#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000)
39
40/*
41 * AIPS 1
42 */
43#define MX51_AIPS1_BASE_ADDR 0x73f00000
44#define MX51_AIPS1_SIZE SZ_1M
45
46#define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
47#define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000)
48#define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200)
49#define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400)
50#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
51#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
52#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
53#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
54#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
55#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
56#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
57#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
58#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
59#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000)
60#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000)
61#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000)
62#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000)
63#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000)
64#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000)
65#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000)
66#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000)
67#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000)
68#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000)
69
70/*
71 * AIPS 2
72 */
73#define MX51_AIPS2_BASE_ADDR 0x83f00000
74#define MX51_AIPS2_SIZE SZ_1M
75
76#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
77#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
78#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
79#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
80#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
81#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
82#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
83#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
84#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
85#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000)
86#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000)
87#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000)
88#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000)
89#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000)
90#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000)
91#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000)
92#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000)
93#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000)
94#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000)
95#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000)
96#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000)
97#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000)
98#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000)
99#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00)
100#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
101#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
102#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
103#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
104#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
105#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
106#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
107#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000)
108
109#define MX51_CSD0_BASE_ADDR 0x90000000
110#define MX51_CSD1_BASE_ADDR 0xa0000000
111#define MX51_CS0_BASE_ADDR 0xb0000000
112#define MX51_CS1_BASE_ADDR 0xb8000000
113#define MX51_CS2_BASE_ADDR 0xc0000000
114#define MX51_CS3_BASE_ADDR 0xc8000000
115#define MX51_CS4_BASE_ADDR 0xcc000000
116#define MX51_CS5_BASE_ADDR 0xce000000
117
118/*
119 * NFC
120 */
121#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */
122#define MX51_NFC_AXI_SIZE SZ_64K
123
124#define MX51_GPU2D_BASE_ADDR 0xd0000000
125#define MX51_TZIC_BASE_ADDR 0xe0000000
126#define MX51_TZIC_SIZE SZ_16K
127
128#define MX51_IO_P2V(x) IMX_IO_P2V(x)
129#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
130
131/*
132 * defines for SPBA modules
133 */
134#define MX51_SPBA_SDHC1 0x04
135#define MX51_SPBA_SDHC2 0x08
136#define MX51_SPBA_UART3 0x0c
137#define MX51_SPBA_CSPI1 0x10
138#define MX51_SPBA_SSI2 0x14
139#define MX51_SPBA_SDHC3 0x20
140#define MX51_SPBA_SDHC4 0x24
141#define MX51_SPBA_SPDIF 0x28
142#define MX51_SPBA_ATA 0x30
143#define MX51_SPBA_SLIM 0x34
144#define MX51_SPBA_HSI2C 0x38
145#define MX51_SPBA_CTRL 0x3c
146
147/*
148 * Defines for modules using static and dynamic DMA channels
149 */
150#define MX51_MXC_DMA_CHANNEL_IRAM 30
151#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
152#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
153#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
154#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
155#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
156#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
157#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
158#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
159#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
160#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
161#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
162#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
163#ifdef CONFIG_SDMA_IRAM
164#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
165#else /*CONFIG_SDMA_IRAM */
166#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
167#endif /*CONFIG_SDMA_IRAM */
168#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
169#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
170#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
171#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
172#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
173#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
174#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
175#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
176#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
177
178#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
179
180/*
181 * DMA request assignments
182 */
183#define MX51_DMA_REQ_VPU 0
184#define MX51_DMA_REQ_GPC 1
185#define MX51_DMA_REQ_ATA_RX 2
186#define MX51_DMA_REQ_ATA_TX 3
187#define MX51_DMA_REQ_ATA_TX_END 4
188#define MX51_DMA_REQ_SLIM_B 5
189#define MX51_DMA_REQ_CSPI1_RX 6
190#define MX51_DMA_REQ_CSPI1_TX 7
191#define MX51_DMA_REQ_CSPI2_RX 8
192#define MX51_DMA_REQ_CSPI2_TX 9
193#define MX51_DMA_REQ_HS_I2C_TX 10
194#define MX51_DMA_REQ_HS_I2C_RX 11
195#define MX51_DMA_REQ_FIRI_RX 12
196#define MX51_DMA_REQ_FIRI_TX 13
197#define MX51_DMA_REQ_EXTREQ1 14
198#define MX51_DMA_REQ_GPU 15
199#define MX51_DMA_REQ_UART2_RX 16
200#define MX51_DMA_REQ_UART2_TX 17
201#define MX51_DMA_REQ_UART1_RX 18
202#define MX51_DMA_REQ_UART1_TX 19
203#define MX51_DMA_REQ_SDHC1 20
204#define MX51_DMA_REQ_SDHC2 21
205#define MX51_DMA_REQ_SSI2_RX1 22
206#define MX51_DMA_REQ_SSI2_TX1 23
207#define MX51_DMA_REQ_SSI2_RX0 24
208#define MX51_DMA_REQ_SSI2_TX0 25
209#define MX51_DMA_REQ_SSI1_RX1 26
210#define MX51_DMA_REQ_SSI1_TX1 27
211#define MX51_DMA_REQ_SSI1_RX0 28
212#define MX51_DMA_REQ_SSI1_TX0 29
213#define MX51_DMA_REQ_EMI_RD 30
214#define MX51_DMA_REQ_CTI2_0 31
215#define MX51_DMA_REQ_EMI_WR 32
216#define MX51_DMA_REQ_CTI2_1 33
217#define MX51_DMA_REQ_EPIT2 34
218#define MX51_DMA_REQ_SSI3_RX1 35
219#define MX51_DMA_REQ_IPU 36
220#define MX51_DMA_REQ_SSI3_TX1 37
221#define MX51_DMA_REQ_CSPI_RX 38
222#define MX51_DMA_REQ_CSPI_TX 39
223#define MX51_DMA_REQ_SDHC3 40
224#define MX51_DMA_REQ_SDHC4 41
225#define MX51_DMA_REQ_SLIM_B_TX 42
226#define MX51_DMA_REQ_UART3_RX 43
227#define MX51_DMA_REQ_UART3_TX 44
228#define MX51_DMA_REQ_SPDIF 45
229#define MX51_DMA_REQ_SSI3_RX0 46
230#define MX51_DMA_REQ_SSI3_TX0 47
231
232/*
233 * Interrupt numbers
234 */
235#include <asm/irq.h>
236#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
237#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
238#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
239#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
240#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
241#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
242#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
243#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
244#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
245#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
246#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
247#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
248#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
249#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
250#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
251#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
252#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
253#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
254#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
255#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
256#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
257#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
258#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
259#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
260#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
261#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
262#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
263#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
264#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
265#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
266#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
267#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
268#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
269#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
270#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
271#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
272#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
273#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
274#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
275#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
276#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
277#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
278#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
279#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
280#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
281#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
282#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
283#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
284#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
285#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
286#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
287#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
288#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
289#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
290#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
291#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
292#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
293#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
294#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
295#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
296#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
297#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
298#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
299#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
300#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
301#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
302#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
303#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
304#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
305#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
306#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
307#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
308#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
309#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
310#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
311#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
312#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
313#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
314#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
315#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
316#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
317#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
318#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
319#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
320#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
321#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
322#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
323#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
324#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
325#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
326#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
327#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
328#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
329#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
330#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
331#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
332#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
333#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
334#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
335#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
336#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
337#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
338#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
339#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
340
341#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
342extern int mx51_revision(void);
343extern void mx51_display_revision(void);
344#endif
345
346#endif /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx53.h b/arch/arm/mach-imx/include/mach/mx53.h
new file mode 100644
index 000000000000..f829d1c22501
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx53.h
@@ -0,0 +1,342 @@
1#ifndef __MACH_MX53_H__
2#define __MACH_MX53_H__
3
4/*
5 * IROM
6 */
7#define MX53_IROM_BASE_ADDR 0x0
8#define MX53_IROM_SIZE SZ_64K
9
10/* TZIC */
11#define MX53_TZIC_BASE_ADDR 0x0FFFC000
12#define MX53_TZIC_SIZE SZ_16K
13
14/*
15 * AHCI SATA
16 */
17#define MX53_SATA_BASE_ADDR 0x10000000
18
19/*
20 * NFC
21 */
22#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */
23#define MX53_NFC_AXI_SIZE SZ_64K
24
25/*
26 * IRAM
27 */
28#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */
29#define MX53_IRAM_PARTITIONS 16
30#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */
31
32/*
33 * Graphics Memory of GPU
34 */
35#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
36#define MX53_GPU2D_BASE_ADDR 0x20000000
37#define MX53_GPU_BASE_ADDR 0x30000000
38#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
39
40#define MX53_DEBUG_BASE_ADDR 0x40000000
41#define MX53_DEBUG_SIZE SZ_1M
42#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000)
43#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000)
44#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000)
45#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000)
46#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000)
47#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000)
48#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000)
49#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000)
50
51/*
52 * SPBA global module enabled #0
53 */
54#define MX53_SPBA0_BASE_ADDR 0x50000000
55#define MX53_SPBA0_SIZE SZ_1M
56
57#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
58#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
59#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
60#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
61#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
62#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
63#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
64#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
65#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
66#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
67#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
68#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
69#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
70
71/*
72 * AIPS 1
73 */
74#define MX53_AIPS1_BASE_ADDR 0x53F00000
75#define MX53_AIPS1_SIZE SZ_1M
76
77#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
78#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
79#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
80#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
81#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
82#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
83#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
84#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
85#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
86#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
87#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
88#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
89#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
90#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
91#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
92#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
93#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
94#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
95#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
96#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
97#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
98#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
99#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
100#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
101#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
102#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
103
104/*
105 * AIPS 2
106 */
107#define MX53_AIPS2_BASE_ADDR 0x63F00000
108#define MX53_AIPS2_SIZE SZ_1M
109
110#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
111#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
112#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
113#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
114#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
115#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
116#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
117#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
118#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
119#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
120#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
121#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
122#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
123#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
124#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
125#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
126#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
127#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
128#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
129#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
130#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
131#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
132#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
133#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
134#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
135#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
136#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
137#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
138#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
139#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
140#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
141#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
142#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
143#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
144#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
145
146/*
147 * Memory regions and CS
148 */
149#define MX53_CSD0_BASE_ADDR 0x70000000
150#define MX53_CSD1_BASE_ADDR 0xB0000000
151#define MX53_CS0_BASE_ADDR 0xF0000000
152#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
153#define MX53_CS1_64MB_BASE_ADDR 0xF4000000
154#define MX53_CS2_64MB_BASE_ADDR 0xF4000000
155#define MX53_CS2_96MB_BASE_ADDR 0xF6000000
156#define MX53_CS3_BASE_ADDR 0xF6000000
157
158#define MX53_IO_P2V(x) IMX_IO_P2V(x)
159#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
160
161/*
162 * defines for SPBA modules
163 */
164#define MX53_SPBA_SDHC1 0x04
165#define MX53_SPBA_SDHC2 0x08
166#define MX53_SPBA_UART3 0x0C
167#define MX53_SPBA_CSPI1 0x10
168#define MX53_SPBA_SSI2 0x14
169#define MX53_SPBA_SDHC3 0x20
170#define MX53_SPBA_SDHC4 0x24
171#define MX53_SPBA_SPDIF 0x28
172#define MX53_SPBA_ATA 0x30
173#define MX53_SPBA_SLIM 0x34
174#define MX53_SPBA_HSI2C 0x38
175#define MX53_SPBA_CTRL 0x3C
176
177/*
178 * DMA request assignments
179 */
180#define MX53_DMA_REQ_SSI3_TX0 47
181#define MX53_DMA_REQ_SSI3_RX0 46
182#define MX53_DMA_REQ_SSI3_TX1 45
183#define MX53_DMA_REQ_SSI3_RX1 44
184#define MX53_DMA_REQ_UART3_TX 43
185#define MX53_DMA_REQ_UART3_RX 42
186#define MX53_DMA_REQ_ESAI_TX 41
187#define MX53_DMA_REQ_ESAI_RX 40
188#define MX53_DMA_REQ_CSPI_TX 39
189#define MX53_DMA_REQ_CSPI_RX 38
190#define MX53_DMA_REQ_ASRC_DMA6 37
191#define MX53_DMA_REQ_ASRC_DMA5 36
192#define MX53_DMA_REQ_ASRC_DMA4 35
193#define MX53_DMA_REQ_ASRC_DMA3 34
194#define MX53_DMA_REQ_ASRC_DMA2 33
195#define MX53_DMA_REQ_ASRC_DMA1 32
196#define MX53_DMA_REQ_EMI_WR 31
197#define MX53_DMA_REQ_EMI_RD 30
198#define MX53_DMA_REQ_SSI1_TX0 29
199#define MX53_DMA_REQ_SSI1_RX0 28
200#define MX53_DMA_REQ_SSI1_TX1 27
201#define MX53_DMA_REQ_SSI1_RX1 26
202#define MX53_DMA_REQ_SSI2_TX0 25
203#define MX53_DMA_REQ_SSI2_RX0 24
204#define MX53_DMA_REQ_SSI2_TX1 23
205#define MX53_DMA_REQ_SSI2_RX1 22
206#define MX53_DMA_REQ_I2C2_SDHC2 21
207#define MX53_DMA_REQ_I2C1_SDHC1 20
208#define MX53_DMA_REQ_UART1_TX 19
209#define MX53_DMA_REQ_UART1_RX 18
210#define MX53_DMA_REQ_UART5_TX 17
211#define MX53_DMA_REQ_UART5_RX 16
212#define MX53_DMA_REQ_SPDIF_TX 15
213#define MX53_DMA_REQ_SPDIF_RX 14
214#define MX53_DMA_REQ_UART2_FIRI_TX 13
215#define MX53_DMA_REQ_UART2_FIRI_RX 12
216#define MX53_DMA_REQ_SDHC4 11
217#define MX53_DMA_REQ_I2C3_SDHC3 10
218#define MX53_DMA_REQ_CSPI2_TX 9
219#define MX53_DMA_REQ_CSPI2_RX 8
220#define MX53_DMA_REQ_CSPI1_TX 7
221#define MX53_DMA_REQ_CSPI1_RX 6
222#define MX53_DMA_REQ_IPU 5
223#define MX53_DMA_REQ_ATA_TX_END 4
224#define MX53_DMA_REQ_ATA_UART4_TX 3
225#define MX53_DMA_REQ_ATA_UART4_RX 2
226#define MX53_DMA_REQ_GPC 1
227#define MX53_DMA_REQ_VPU 0
228
229/*
230 * Interrupt numbers
231 */
232#include <asm/irq.h>
233#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0)
234#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
235#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
236#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
237#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
238#define MX53_INT_DAP (NR_IRQS_LEGACY + 5)
239#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6)
240#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7)
241#define MX53_INT_NFC (NR_IRQS_LEGACY + 8)
242#define MX53_INT_VPU (NR_IRQS_LEGACY + 9)
243#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
244#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
245#define MX53_INT_GPU (NR_IRQS_LEGACY + 12)
246#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13)
247#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14)
248#define MX53_INT_EMI (NR_IRQS_LEGACY + 15)
249#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16)
250#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17)
251#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18)
252#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
253#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
254#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
255#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
256#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
257#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
258#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
259#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26)
260#define MX53_INT_CSU (NR_IRQS_LEGACY + 27)
261#define MX53_INT_SATA (NR_IRQS_LEGACY + 28)
262#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29)
263#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30)
264#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31)
265#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32)
266#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33)
267#define MX53_INT_RTC (NR_IRQS_LEGACY + 34)
268#define MX53_INT_PTP (NR_IRQS_LEGACY + 35)
269#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
270#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
271#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38)
272#define MX53_INT_GPT (NR_IRQS_LEGACY + 39)
273#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40)
274#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41)
275#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
276#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
277#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
278#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
279#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
280#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
281#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
282#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
283#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
284#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
285#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
286#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
287#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
288#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
289#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
290#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
291#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58)
292#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59)
293#define MX53_INT_KPP (NR_IRQS_LEGACY + 60)
294#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61)
295#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62)
296#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63)
297#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64)
298#define MX53_INT_MLB (NR_IRQS_LEGACY + 65)
299#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66)
300#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67)
301#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
302#define MX53_INT_IIM (NR_IRQS_LEGACY + 69)
303#define MX53_INT_ATA (NR_IRQS_LEGACY + 70)
304#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71)
305#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72)
306#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73)
307#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74)
308#define MX53_INT_SRC (NR_IRQS_LEGACY + 75)
309#define MX53_INT_NM (NR_IRQS_LEGACY + 76)
310#define MX53_INT_PMU (NR_IRQS_LEGACY + 77)
311#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
312#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
313#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
314#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81)
315#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82)
316#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83)
317#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
318#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
319#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86)
320#define MX53_INT_FEC (NR_IRQS_LEGACY + 87)
321#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88)
322#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
323#define MX53_INT_SJC (NR_IRQS_LEGACY + 90)
324#define MX53_INT_TVE (NR_IRQS_LEGACY + 92)
325#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93)
326#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94)
327#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
328#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96)
329#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
330#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
331#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99)
332#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
333#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
334#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
335#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
336#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
337#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
338#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
339#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107)
340#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108)
341
342#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx6q.h b/arch/arm/mach-imx/include/mach/mx6q.h
new file mode 100644
index 000000000000..f7e7dbac8f4b
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx6q.h
@@ -0,0 +1,35 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#ifndef __MACH_MX6Q_H__
14#define __MACH_MX6Q_H__
15
16#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
17#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
18
19/*
20 * The following are the blocks that need to be statically mapped.
21 * For other blocks, the base address really should be retrieved from
22 * device tree.
23 */
24#define MX6Q_SCU_BASE_ADDR 0x00a00000
25#define MX6Q_SCU_SIZE 0x1000
26#define MX6Q_CCM_BASE_ADDR 0x020c4000
27#define MX6Q_CCM_SIZE 0x4000
28#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
29#define MX6Q_ANATOP_SIZE 0x1000
30#define MX6Q_UART2_BASE_ADDR 0x021e8000
31#define MX6Q_UART2_SIZE 0x4000
32#define MX6Q_UART4_BASE_ADDR 0x021f0000
33#define MX6Q_UART4_SIZE 0x4000
34
35#endif /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mxc.h b/arch/arm/mach-imx/include/mach/mxc.h
new file mode 100644
index 000000000000..d78298366a91
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mxc.h
@@ -0,0 +1,179 @@
1/*
2 * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_H__
21#define __ASM_ARCH_MXC_H__
22
23#include <linux/types.h>
24
25#ifndef __ASM_ARCH_MXC_HARDWARE_H__
26#error "Do not include directly."
27#endif
28
29#define MXC_CPU_MX1 1
30#define MXC_CPU_MX21 21
31#define MXC_CPU_MX25 25
32#define MXC_CPU_MX27 27
33#define MXC_CPU_MX31 31
34#define MXC_CPU_MX35 35
35#define MXC_CPU_MX50 50
36#define MXC_CPU_MX51 51
37#define MXC_CPU_MX53 53
38
39#define IMX_CHIP_REVISION_1_0 0x10
40#define IMX_CHIP_REVISION_1_1 0x11
41#define IMX_CHIP_REVISION_1_2 0x12
42#define IMX_CHIP_REVISION_1_3 0x13
43#define IMX_CHIP_REVISION_2_0 0x20
44#define IMX_CHIP_REVISION_2_1 0x21
45#define IMX_CHIP_REVISION_2_2 0x22
46#define IMX_CHIP_REVISION_2_3 0x23
47#define IMX_CHIP_REVISION_3_0 0x30
48#define IMX_CHIP_REVISION_3_1 0x31
49#define IMX_CHIP_REVISION_3_2 0x32
50#define IMX_CHIP_REVISION_3_3 0x33
51#define IMX_CHIP_REVISION_UNKNOWN 0xff
52
53#ifndef __ASSEMBLY__
54extern unsigned int __mxc_cpu_type;
55#endif
56
57#ifdef CONFIG_SOC_IMX1
58# ifdef mxc_cpu_type
59# undef mxc_cpu_type
60# define mxc_cpu_type __mxc_cpu_type
61# else
62# define mxc_cpu_type MXC_CPU_MX1
63# endif
64# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
65#else
66# define cpu_is_mx1() (0)
67#endif
68
69#ifdef CONFIG_SOC_IMX21
70# ifdef mxc_cpu_type
71# undef mxc_cpu_type
72# define mxc_cpu_type __mxc_cpu_type
73# else
74# define mxc_cpu_type MXC_CPU_MX21
75# endif
76# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
77#else
78# define cpu_is_mx21() (0)
79#endif
80
81#ifdef CONFIG_SOC_IMX25
82# ifdef mxc_cpu_type
83# undef mxc_cpu_type
84# define mxc_cpu_type __mxc_cpu_type
85# else
86# define mxc_cpu_type MXC_CPU_MX25
87# endif
88# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
89#else
90# define cpu_is_mx25() (0)
91#endif
92
93#ifdef CONFIG_SOC_IMX27
94# ifdef mxc_cpu_type
95# undef mxc_cpu_type
96# define mxc_cpu_type __mxc_cpu_type
97# else
98# define mxc_cpu_type MXC_CPU_MX27
99# endif
100# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
101#else
102# define cpu_is_mx27() (0)
103#endif
104
105#ifdef CONFIG_SOC_IMX31
106# ifdef mxc_cpu_type
107# undef mxc_cpu_type
108# define mxc_cpu_type __mxc_cpu_type
109# else
110# define mxc_cpu_type MXC_CPU_MX31
111# endif
112# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
113#else
114# define cpu_is_mx31() (0)
115#endif
116
117#ifdef CONFIG_SOC_IMX35
118# ifdef mxc_cpu_type
119# undef mxc_cpu_type
120# define mxc_cpu_type __mxc_cpu_type
121# else
122# define mxc_cpu_type MXC_CPU_MX35
123# endif
124# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
125#else
126# define cpu_is_mx35() (0)
127#endif
128
129#ifdef CONFIG_SOC_IMX50
130# ifdef mxc_cpu_type
131# undef mxc_cpu_type
132# define mxc_cpu_type __mxc_cpu_type
133# else
134# define mxc_cpu_type MXC_CPU_MX50
135# endif
136# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
137#else
138# define cpu_is_mx50() (0)
139#endif
140
141#ifdef CONFIG_SOC_IMX51
142# ifdef mxc_cpu_type
143# undef mxc_cpu_type
144# define mxc_cpu_type __mxc_cpu_type
145# else
146# define mxc_cpu_type MXC_CPU_MX51
147# endif
148# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
149#else
150# define cpu_is_mx51() (0)
151#endif
152
153#ifdef CONFIG_SOC_IMX53
154# ifdef mxc_cpu_type
155# undef mxc_cpu_type
156# define mxc_cpu_type __mxc_cpu_type
157# else
158# define mxc_cpu_type MXC_CPU_MX53
159# endif
160# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
161#else
162# define cpu_is_mx53() (0)
163#endif
164
165#ifndef __ASSEMBLY__
166
167struct cpu_op {
168 u32 cpu_rate;
169};
170
171int tzic_enable_wake(void);
172
173extern struct cpu_op *(*get_cpu_op)(int *op);
174#endif
175
176#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
177#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
178
179#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/mach-imx/include/mach/timex.h b/arch/arm/mach-imx/include/mach/timex.h
new file mode 100644
index 000000000000..10343d1f87e1
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/timex.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ASM_ARCH_MXC_TIMEX_H__
17#define __ASM_ARCH_MXC_TIMEX_H__
18
19/* Bogus value */
20#define CLOCK_TICK_RATE 12345678
21
22#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/mach-imx/include/mach/ulpi.h b/arch/arm/mach-imx/include/mach/ulpi.h
new file mode 100644
index 000000000000..42bdaca6d7d9
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/ulpi.h
@@ -0,0 +1,16 @@
1#ifndef __MACH_ULPI_H
2#define __MACH_ULPI_H
3
4#ifdef CONFIG_USB_ULPI
5struct usb_phy *imx_otg_ulpi_create(unsigned int flags);
6#else
7static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
8{
9 return NULL;
10}
11#endif
12
13extern struct usb_phy_io_ops mxc_ulpi_access_ops;
14
15#endif /* __MACH_ULPI_H */
16
diff --git a/arch/arm/mach-imx/include/mach/uncompress.h b/arch/arm/mach-imx/include/mach/uncompress.h
new file mode 100644
index 000000000000..477971b00930
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/uncompress.h
@@ -0,0 +1,132 @@
1/*
2 * arch/arm/plat-mxc/include/mach/uncompress.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) Shane Nay (shane@minirl.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
18#define __ASM_ARCH_MXC_UNCOMPRESS_H__
19
20#define __MXC_BOOT_UNCOMPRESS
21
22#include <asm/mach-types.h>
23
24unsigned long uart_base;
25
26#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
27
28#define USR2 0x98
29#define USR2_TXFE (1<<14)
30#define TXR 0x40
31#define UCR1 0x80
32#define UCR1_UARTEN 1
33
34/*
35 * The following code assumes the serial port has already been
36 * initialized by the bootloader. We search for the first enabled
37 * port in the most probable order. If you didn't setup a port in
38 * your bootloader then nothing will appear (which might be desired).
39 *
40 * This does not append a newline
41 */
42
43static void putc(int ch)
44{
45 if (!uart_base)
46 return;
47 if (!(UART(UCR1) & UCR1_UARTEN))
48 return;
49
50 while (!(UART(USR2) & USR2_TXFE))
51 barrier();
52
53 UART(TXR) = ch;
54}
55
56static inline void flush(void)
57{
58}
59
60#define MX1_UART1_BASE_ADDR 0x00206000
61#define MX25_UART1_BASE_ADDR 0x43f90000
62#define MX2X_UART1_BASE_ADDR 0x1000a000
63#define MX3X_UART1_BASE_ADDR 0x43F90000
64#define MX3X_UART2_BASE_ADDR 0x43F94000
65#define MX3X_UART5_BASE_ADDR 0x43FB4000
66#define MX51_UART1_BASE_ADDR 0x73fbc000
67#define MX50_UART1_BASE_ADDR 0x53fbc000
68#define MX53_UART1_BASE_ADDR 0x53fbc000
69
70static __inline__ void __arch_decomp_setup(unsigned long arch_id)
71{
72 switch (arch_id) {
73 case MACH_TYPE_MX1ADS:
74 case MACH_TYPE_SCB9328:
75 uart_base = MX1_UART1_BASE_ADDR;
76 break;
77 case MACH_TYPE_MX25_3DS:
78 uart_base = MX25_UART1_BASE_ADDR;
79 break;
80 case MACH_TYPE_IMX27LITE:
81 case MACH_TYPE_MX27_3DS:
82 case MACH_TYPE_MX27ADS:
83 case MACH_TYPE_PCM038:
84 case MACH_TYPE_MX21ADS:
85 case MACH_TYPE_PCA100:
86 case MACH_TYPE_MXT_TD60:
87 case MACH_TYPE_IMX27IPCAM:
88 uart_base = MX2X_UART1_BASE_ADDR;
89 break;
90 case MACH_TYPE_MX31LITE:
91 case MACH_TYPE_ARMADILLO5X0:
92 case MACH_TYPE_MX31MOBOARD:
93 case MACH_TYPE_QONG:
94 case MACH_TYPE_MX31_3DS:
95 case MACH_TYPE_PCM037:
96 case MACH_TYPE_MX31ADS:
97 case MACH_TYPE_MX35_3DS:
98 case MACH_TYPE_PCM043:
99 case MACH_TYPE_LILLY1131:
100 case MACH_TYPE_VPR200:
101 case MACH_TYPE_EUKREA_CPUIMX35SD:
102 uart_base = MX3X_UART1_BASE_ADDR;
103 break;
104 case MACH_TYPE_MAGX_ZN5:
105 uart_base = MX3X_UART2_BASE_ADDR;
106 break;
107 case MACH_TYPE_BUG:
108 uart_base = MX3X_UART5_BASE_ADDR;
109 break;
110 case MACH_TYPE_MX51_BABBAGE:
111 case MACH_TYPE_EUKREA_CPUIMX51SD:
112 case MACH_TYPE_MX51_3DS:
113 uart_base = MX51_UART1_BASE_ADDR;
114 break;
115 case MACH_TYPE_MX50_RDP:
116 uart_base = MX50_UART1_BASE_ADDR;
117 break;
118 case MACH_TYPE_MX53_EVK:
119 case MACH_TYPE_MX53_LOCO:
120 case MACH_TYPE_MX53_SMD:
121 case MACH_TYPE_MX53_ARD:
122 uart_base = MX53_UART1_BASE_ADDR;
123 break;
124 default:
125 break;
126 }
127}
128
129#define arch_decomp_setup() __arch_decomp_setup(arch_id)
130#define arch_decomp_wdog()
131
132#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/arch/arm/mach-imx/iram_alloc.c b/arch/arm/mach-imx/iram_alloc.c
new file mode 100644
index 000000000000..074c3869626a
--- /dev/null
+++ b/arch/arm/mach-imx/iram_alloc.c
@@ -0,0 +1,73 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/spinlock.h>
24#include <linux/genalloc.h>
25#include <mach/iram.h>
26
27static unsigned long iram_phys_base;
28static void __iomem *iram_virt_base;
29static struct gen_pool *iram_pool;
30
31static inline void __iomem *iram_phys_to_virt(unsigned long p)
32{
33 return iram_virt_base + (p - iram_phys_base);
34}
35
36void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
37{
38 if (!iram_pool)
39 return NULL;
40
41 *dma_addr = gen_pool_alloc(iram_pool, size);
42 pr_debug("iram alloc - %dB@0x%lX\n", size, *dma_addr);
43 if (!*dma_addr)
44 return NULL;
45 return iram_phys_to_virt(*dma_addr);
46}
47EXPORT_SYMBOL(iram_alloc);
48
49void iram_free(unsigned long addr, unsigned int size)
50{
51 if (!iram_pool)
52 return;
53
54 gen_pool_free(iram_pool, addr, size);
55}
56EXPORT_SYMBOL(iram_free);
57
58int __init iram_init(unsigned long base, unsigned long size)
59{
60 iram_phys_base = base;
61
62 iram_pool = gen_pool_create(PAGE_SHIFT, -1);
63 if (!iram_pool)
64 return -ENOMEM;
65
66 gen_pool_add(iram_pool, base, size, -1);
67 iram_virt_base = ioremap(iram_phys_base, size);
68 if (!iram_virt_base)
69 return -EIO;
70
71 pr_debug("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base);
72 return 0;
73}
diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
new file mode 100644
index 000000000000..b6e11458e5ae
--- /dev/null
+++ b/arch/arm/mach-imx/irq-common.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) BitBox Ltd 2010
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/module.h>
20#include <linux/irq.h>
21
22#include "irq-common.h"
23
24int imx_irq_set_priority(unsigned char irq, unsigned char prio)
25{
26 struct irq_chip_generic *gc;
27 struct mxc_extra_irq *exirq;
28 int ret;
29
30 ret = -ENOSYS;
31
32 gc = irq_get_chip_data(irq);
33 if (gc && gc->private) {
34 exirq = gc->private;
35 if (exirq->set_priority)
36 ret = exirq->set_priority(irq, prio);
37 }
38
39 return ret;
40}
41EXPORT_SYMBOL(imx_irq_set_priority);
42
43int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
44{
45 struct irq_chip_generic *gc;
46 struct mxc_extra_irq *exirq;
47 int ret;
48
49 ret = -ENOSYS;
50
51 gc = irq_get_chip_data(irq);
52 if (gc && gc->private) {
53 exirq = gc->private;
54 if (exirq->set_irq_fiq)
55 ret = exirq->set_irq_fiq(irq, type);
56 }
57
58 return ret;
59}
60EXPORT_SYMBOL(mxc_set_irq_fiq);
diff --git a/arch/arm/mach-imx/irq-common.h b/arch/arm/mach-imx/irq-common.h
new file mode 100644
index 000000000000..6ccb3a14c693
--- /dev/null
+++ b/arch/arm/mach-imx/irq-common.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) BitBox Ltd 2010
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __PLAT_MXC_IRQ_COMMON_H__
20#define __PLAT_MXC_IRQ_COMMON_H__
21
22struct mxc_extra_irq
23{
24 int (*set_priority)(unsigned char irq, unsigned char prio);
25 int (*set_irq_fiq)(unsigned int irq, unsigned int type);
26};
27
28#endif
diff --git a/arch/arm/mach-imx/ssi-fiq-ksym.c b/arch/arm/mach-imx/ssi-fiq-ksym.c
new file mode 100644
index 000000000000..792090f9a032
--- /dev/null
+++ b/arch/arm/mach-imx/ssi-fiq-ksym.c
@@ -0,0 +1,20 @@
1/*
2 * Exported ksyms for the SSI FIQ handler
3 *
4 * Copyright (C) 2009, Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12
13#include <linux/platform_data/asoc-imx-ssi.h>
14
15EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer);
16EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer);
17EXPORT_SYMBOL(imx_ssi_fiq_start);
18EXPORT_SYMBOL(imx_ssi_fiq_end);
19EXPORT_SYMBOL(imx_ssi_fiq_base);
20
diff --git a/arch/arm/mach-imx/ssi-fiq.S b/arch/arm/mach-imx/ssi-fiq.S
new file mode 100644
index 000000000000..a8b93c5f29b5
--- /dev/null
+++ b/arch/arm/mach-imx/ssi-fiq.S
@@ -0,0 +1,147 @@
1/*
2 * Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/linkage.h>
10#include <asm/assembler.h>
11
12/*
13 * r8 = bit 0-15: tx offset, bit 16-31: tx buffer size
14 * r9 = bit 0-15: rx offset, bit 16-31: rx buffer size
15 */
16
17#define SSI_STX0 0x00
18#define SSI_SRX0 0x08
19#define SSI_SISR 0x14
20#define SSI_SIER 0x18
21#define SSI_SACNT 0x38
22
23#define SSI_SACNT_AC97EN (1 << 0)
24
25#define SSI_SIER_TFE0_EN (1 << 0)
26#define SSI_SISR_TFE0 (1 << 0)
27#define SSI_SISR_RFF0 (1 << 2)
28#define SSI_SIER_RFF0_EN (1 << 2)
29
30 .text
31 .global imx_ssi_fiq_start
32 .global imx_ssi_fiq_end
33 .global imx_ssi_fiq_base
34 .global imx_ssi_fiq_rx_buffer
35 .global imx_ssi_fiq_tx_buffer
36
37/*
38 * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol
39 * using ENDPROC(). imx_ssi_fiq_start and imx_ssi_fiq_end are used to
40 * mark the function body so that it can be copied to the FIQ vector in
41 * the vectors page. imx_ssi_fiq_start should only be called as the result
42 * of an FIQ: calling it directly will not work.
43 */
44imx_ssi_fiq_start:
45 ldr r12, .L_imx_ssi_fiq_base
46
47 /* TX */
48 ldr r13, .L_imx_ssi_fiq_tx_buffer
49
50 /* shall we send? */
51 ldr r11, [r12, #SSI_SIER]
52 tst r11, #SSI_SIER_TFE0_EN
53 beq 1f
54
55 /* TX FIFO empty? */
56 ldr r11, [r12, #SSI_SISR]
57 tst r11, #SSI_SISR_TFE0
58 beq 1f
59
60 mov r10, #0x10000
61 sub r10, #1
62 and r10, r10, r8 /* r10: current buffer offset */
63
64 add r13, r13, r10
65
66 ldrh r11, [r13]
67 strh r11, [r12, #SSI_STX0]
68
69 ldrh r11, [r13, #2]
70 strh r11, [r12, #SSI_STX0]
71
72 ldrh r11, [r13, #4]
73 strh r11, [r12, #SSI_STX0]
74
75 ldrh r11, [r13, #6]
76 strh r11, [r12, #SSI_STX0]
77
78 add r10, #8
79 lsr r11, r8, #16 /* r11: buffer size */
80 cmp r10, r11
81 lslgt r8, r11, #16
82 addle r8, #8
831:
84 /* RX */
85
86 /* shall we receive? */
87 ldr r11, [r12, #SSI_SIER]
88 tst r11, #SSI_SIER_RFF0_EN
89 beq 1f
90
91 /* RX FIFO full? */
92 ldr r11, [r12, #SSI_SISR]
93 tst r11, #SSI_SISR_RFF0
94 beq 1f
95
96 ldr r13, .L_imx_ssi_fiq_rx_buffer
97
98 mov r10, #0x10000
99 sub r10, #1
100 and r10, r10, r9 /* r10: current buffer offset */
101
102 add r13, r13, r10
103
104 ldr r11, [r12, #SSI_SACNT]
105 tst r11, #SSI_SACNT_AC97EN
106
107 ldr r11, [r12, #SSI_SRX0]
108 strh r11, [r13]
109
110 ldr r11, [r12, #SSI_SRX0]
111 strh r11, [r13, #2]
112
113 /* dummy read to skip slot 12 */
114 ldrne r11, [r12, #SSI_SRX0]
115
116 ldr r11, [r12, #SSI_SRX0]
117 strh r11, [r13, #4]
118
119 ldr r11, [r12, #SSI_SRX0]
120 strh r11, [r13, #6]
121
122 /* dummy read to skip slot 12 */
123 ldrne r11, [r12, #SSI_SRX0]
124
125 add r10, #8
126 lsr r11, r9, #16 /* r11: buffer size */
127 cmp r10, r11
128 lslgt r9, r11, #16
129 addle r9, #8
130
1311:
132 @ return from FIQ
133 subs pc, lr, #4
134
135 .align
136.L_imx_ssi_fiq_base:
137imx_ssi_fiq_base:
138 .word 0x0
139.L_imx_ssi_fiq_rx_buffer:
140imx_ssi_fiq_rx_buffer:
141 .word 0x0
142.L_imx_ssi_fiq_tx_buffer:
143imx_ssi_fiq_tx_buffer:
144 .word 0x0
145.L_imx_ssi_fiq_end:
146imx_ssi_fiq_end:
147
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
new file mode 100644
index 000000000000..3da78cfc5a94
--- /dev/null
+++ b/arch/arm/mach-imx/system.c
@@ -0,0 +1,69 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
6 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/err.h>
23#include <linux/delay.h>
24
25#include <mach/hardware.h>
26#include <mach/common.h>
27#include <asm/system_misc.h>
28#include <asm/proc-fns.h>
29#include <asm/mach-types.h>
30
31static void __iomem *wdog_base;
32
33/*
34 * Reset the system. It is called by machine_restart().
35 */
36void mxc_restart(char mode, const char *cmd)
37{
38 unsigned int wcr_enable;
39
40 if (cpu_is_mx1()) {
41 wcr_enable = (1 << 0);
42 } else {
43 struct clk *clk;
44
45 clk = clk_get_sys("imx2-wdt.0", NULL);
46 if (!IS_ERR(clk))
47 clk_prepare_enable(clk);
48 wcr_enable = (1 << 2);
49 }
50
51 /* Assert SRS signal */
52 __raw_writew(wcr_enable, wdog_base);
53
54 /* wait for reset to assert... */
55 mdelay(500);
56
57 printk(KERN_ERR "Watchdog reset failed to assert reset\n");
58
59 /* delay to allow the serial port to show the message */
60 mdelay(50);
61
62 /* we'll take a jump through zero as a poor second */
63 soft_restart(0);
64}
65
66void mxc_arch_reset_init(void __iomem *base)
67{
68 wdog_base = base;
69}
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
new file mode 100644
index 000000000000..a17abcf98325
--- /dev/null
+++ b/arch/arm/mach-imx/time.c
@@ -0,0 +1,325 @@
1/*
2 * linux/arch/arm/plat-mxc/time.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/clockchips.h>
27#include <linux/clk.h>
28#include <linux/err.h>
29
30#include <mach/hardware.h>
31#include <asm/sched_clock.h>
32#include <asm/mach/time.h>
33#include <mach/common.h>
34
35/*
36 * There are 2 versions of the timer hardware on Freescale MXC hardware.
37 * Version 1: MX1/MXL, MX21, MX27.
38 * Version 2: MX25, MX31, MX35, MX37, MX51
39 */
40
41/* defines common for all i.MX */
42#define MXC_TCTL 0x00
43#define MXC_TCTL_TEN (1 << 0) /* Enable module */
44#define MXC_TPRER 0x04
45
46/* MX1, MX21, MX27 */
47#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
48#define MX1_2_TCTL_IRQEN (1 << 4)
49#define MX1_2_TCTL_FRR (1 << 8)
50#define MX1_2_TCMP 0x08
51#define MX1_2_TCN 0x10
52#define MX1_2_TSTAT 0x14
53
54/* MX21, MX27 */
55#define MX2_TSTAT_CAPT (1 << 1)
56#define MX2_TSTAT_COMP (1 << 0)
57
58/* MX31, MX35, MX25, MX5 */
59#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
60#define V2_TCTL_CLK_IPG (1 << 6)
61#define V2_TCTL_CLK_PER (2 << 6)
62#define V2_TCTL_FRR (1 << 9)
63#define V2_IR 0x0c
64#define V2_TSTAT 0x08
65#define V2_TSTAT_OF1 (1 << 0)
66#define V2_TCN 0x24
67#define V2_TCMP 0x10
68
69#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
70#define timer_is_v2() (!timer_is_v1())
71
72static struct clock_event_device clockevent_mxc;
73static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
74
75static void __iomem *timer_base;
76
77static inline void gpt_irq_disable(void)
78{
79 unsigned int tmp;
80
81 if (timer_is_v2())
82 __raw_writel(0, timer_base + V2_IR);
83 else {
84 tmp = __raw_readl(timer_base + MXC_TCTL);
85 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
86 }
87}
88
89static inline void gpt_irq_enable(void)
90{
91 if (timer_is_v2())
92 __raw_writel(1<<0, timer_base + V2_IR);
93 else {
94 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
95 timer_base + MXC_TCTL);
96 }
97}
98
99static void gpt_irq_acknowledge(void)
100{
101 if (timer_is_v1()) {
102 if (cpu_is_mx1())
103 __raw_writel(0, timer_base + MX1_2_TSTAT);
104 else
105 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
106 timer_base + MX1_2_TSTAT);
107 } else if (timer_is_v2())
108 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
109}
110
111static void __iomem *sched_clock_reg;
112
113static u32 notrace mxc_read_sched_clock(void)
114{
115 return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
116}
117
118static int __init mxc_clocksource_init(struct clk *timer_clk)
119{
120 unsigned int c = clk_get_rate(timer_clk);
121 void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
122
123 sched_clock_reg = reg;
124
125 setup_sched_clock(mxc_read_sched_clock, 32, c);
126 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
127 clocksource_mmio_readl_up);
128}
129
130/* clock event */
131
132static int mx1_2_set_next_event(unsigned long evt,
133 struct clock_event_device *unused)
134{
135 unsigned long tcmp;
136
137 tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
138
139 __raw_writel(tcmp, timer_base + MX1_2_TCMP);
140
141 return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
142 -ETIME : 0;
143}
144
145static int v2_set_next_event(unsigned long evt,
146 struct clock_event_device *unused)
147{
148 unsigned long tcmp;
149
150 tcmp = __raw_readl(timer_base + V2_TCN) + evt;
151
152 __raw_writel(tcmp, timer_base + V2_TCMP);
153
154 return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
155 -ETIME : 0;
156}
157
158#ifdef DEBUG
159static const char *clock_event_mode_label[] = {
160 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
161 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
162 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
163 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
164 [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
165};
166#endif /* DEBUG */
167
168static void mxc_set_mode(enum clock_event_mode mode,
169 struct clock_event_device *evt)
170{
171 unsigned long flags;
172
173 /*
174 * The timer interrupt generation is disabled at least
175 * for enough time to call mxc_set_next_event()
176 */
177 local_irq_save(flags);
178
179 /* Disable interrupt in GPT module */
180 gpt_irq_disable();
181
182 if (mode != clockevent_mode) {
183 /* Set event time into far-far future */
184 if (timer_is_v2())
185 __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
186 timer_base + V2_TCMP);
187 else
188 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
189 timer_base + MX1_2_TCMP);
190
191 /* Clear pending interrupt */
192 gpt_irq_acknowledge();
193 }
194
195#ifdef DEBUG
196 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
197 clock_event_mode_label[clockevent_mode],
198 clock_event_mode_label[mode]);
199#endif /* DEBUG */
200
201 /* Remember timer mode */
202 clockevent_mode = mode;
203 local_irq_restore(flags);
204
205 switch (mode) {
206 case CLOCK_EVT_MODE_PERIODIC:
207 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
208 "supported for i.MX\n");
209 break;
210 case CLOCK_EVT_MODE_ONESHOT:
211 /*
212 * Do not put overhead of interrupt enable/disable into
213 * mxc_set_next_event(), the core has about 4 minutes
214 * to call mxc_set_next_event() or shutdown clock after
215 * mode switching
216 */
217 local_irq_save(flags);
218 gpt_irq_enable();
219 local_irq_restore(flags);
220 break;
221 case CLOCK_EVT_MODE_SHUTDOWN:
222 case CLOCK_EVT_MODE_UNUSED:
223 case CLOCK_EVT_MODE_RESUME:
224 /* Left event sources disabled, no more interrupts appear */
225 break;
226 }
227}
228
229/*
230 * IRQ handler for the timer
231 */
232static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
233{
234 struct clock_event_device *evt = &clockevent_mxc;
235 uint32_t tstat;
236
237 if (timer_is_v2())
238 tstat = __raw_readl(timer_base + V2_TSTAT);
239 else
240 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
241
242 gpt_irq_acknowledge();
243
244 evt->event_handler(evt);
245
246 return IRQ_HANDLED;
247}
248
249static struct irqaction mxc_timer_irq = {
250 .name = "i.MX Timer Tick",
251 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
252 .handler = mxc_timer_interrupt,
253};
254
255static struct clock_event_device clockevent_mxc = {
256 .name = "mxc_timer1",
257 .features = CLOCK_EVT_FEAT_ONESHOT,
258 .shift = 32,
259 .set_mode = mxc_set_mode,
260 .set_next_event = mx1_2_set_next_event,
261 .rating = 200,
262};
263
264static int __init mxc_clockevent_init(struct clk *timer_clk)
265{
266 unsigned int c = clk_get_rate(timer_clk);
267
268 if (timer_is_v2())
269 clockevent_mxc.set_next_event = v2_set_next_event;
270
271 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
272 clockevent_mxc.shift);
273 clockevent_mxc.max_delta_ns =
274 clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
275 clockevent_mxc.min_delta_ns =
276 clockevent_delta2ns(0xff, &clockevent_mxc);
277
278 clockevent_mxc.cpumask = cpumask_of(0);
279
280 clockevents_register_device(&clockevent_mxc);
281
282 return 0;
283}
284
285void __init mxc_timer_init(void __iomem *base, int irq)
286{
287 uint32_t tctl_val;
288 struct clk *timer_clk;
289 struct clk *timer_ipg_clk;
290
291 timer_clk = clk_get_sys("imx-gpt.0", "per");
292 if (IS_ERR(timer_clk)) {
293 pr_err("i.MX timer: unable to get clk\n");
294 return;
295 }
296
297 timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
298 if (!IS_ERR(timer_ipg_clk))
299 clk_prepare_enable(timer_ipg_clk);
300
301 clk_prepare_enable(timer_clk);
302
303 timer_base = base;
304
305 /*
306 * Initialise to a known state (all timers off, and timing reset)
307 */
308
309 __raw_writel(0, timer_base + MXC_TCTL);
310 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
311
312 if (timer_is_v2())
313 tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
314 else
315 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
316
317 __raw_writel(tctl_val, timer_base + MXC_TCTL);
318
319 /* init and register the timer to the framework */
320 mxc_clocksource_init(timer_clk);
321 mxc_clockevent_init(timer_clk);
322
323 /* Make irqs happen */
324 setup_irq(irq, &mxc_timer_irq);
325}
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
new file mode 100644
index 000000000000..3ed1adbc09f8
--- /dev/null
+++ b/arch/arm/mach-imx/tzic.c
@@ -0,0 +1,224 @@
1/*
2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/io.h>
18#include <linux/irqdomain.h>
19#include <linux/of.h>
20
21#include <asm/mach/irq.h>
22#include <asm/exception.h>
23
24#include <mach/hardware.h>
25#include <mach/common.h>
26#include <mach/irqs.h>
27
28#include "irq-common.h"
29
30/*
31 *****************************************
32 * TZIC Registers *
33 *****************************************
34 */
35
36#define TZIC_INTCNTL 0x0000 /* Control register */
37#define TZIC_INTTYPE 0x0004 /* Controller Type register */
38#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
39#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
40#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
41#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
42#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
43#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
44#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
45#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
46#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
47#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
48#define TZIC_PND0 0x0D00 /* Pending Register 0 */
49#define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */
50#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
51#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
52#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
53
54void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
55static struct irq_domain *domain;
56
57#define TZIC_NUM_IRQS 128
58
59#ifdef CONFIG_FIQ
60static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
61{
62 unsigned int index, mask, value;
63
64 index = irq >> 5;
65 if (unlikely(index >= 4))
66 return -EINVAL;
67 mask = 1U << (irq & 0x1F);
68
69 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
70 if (type)
71 value &= ~mask;
72 __raw_writel(value, tzic_base + TZIC_INTSEC0(index));
73
74 return 0;
75}
76#else
77#define tzic_set_irq_fiq NULL
78#endif
79
80#ifdef CONFIG_PM
81static void tzic_irq_suspend(struct irq_data *d)
82{
83 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
84 int idx = d->hwirq >> 5;
85
86 __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
87}
88
89static void tzic_irq_resume(struct irq_data *d)
90{
91 int idx = d->hwirq >> 5;
92
93 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
94 tzic_base + TZIC_WAKEUP0(idx));
95}
96
97#else
98#define tzic_irq_suspend NULL
99#define tzic_irq_resume NULL
100#endif
101
102static struct mxc_extra_irq tzic_extra_irq = {
103#ifdef CONFIG_FIQ
104 .set_irq_fiq = tzic_set_irq_fiq,
105#endif
106};
107
108static __init void tzic_init_gc(int idx, unsigned int irq_start)
109{
110 struct irq_chip_generic *gc;
111 struct irq_chip_type *ct;
112
113 gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
114 handle_level_irq);
115 gc->private = &tzic_extra_irq;
116 gc->wake_enabled = IRQ_MSK(32);
117
118 ct = gc->chip_types;
119 ct->chip.irq_mask = irq_gc_mask_disable_reg;
120 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
121 ct->chip.irq_set_wake = irq_gc_set_wake;
122 ct->chip.irq_suspend = tzic_irq_suspend;
123 ct->chip.irq_resume = tzic_irq_resume;
124 ct->regs.disable = TZIC_ENCLEAR0(idx);
125 ct->regs.enable = TZIC_ENSET0(idx);
126
127 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
128}
129
130asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
131{
132 u32 stat;
133 int i, irqofs, handled;
134
135 do {
136 handled = 0;
137
138 for (i = 0; i < 4; i++) {
139 stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
140 __raw_readl(tzic_base + TZIC_INTSEC0(i));
141
142 while (stat) {
143 handled = 1;
144 irqofs = fls(stat) - 1;
145 handle_IRQ(irq_find_mapping(domain,
146 irqofs + i * 32), regs);
147 stat &= ~(1 << irqofs);
148 }
149 }
150 } while (handled);
151}
152
153/*
154 * This function initializes the TZIC hardware and disables all the
155 * interrupts. It registers the interrupt enable and disable functions
156 * to the kernel for each interrupt source.
157 */
158void __init tzic_init_irq(void __iomem *irqbase)
159{
160 struct device_node *np;
161 int irq_base;
162 int i;
163
164 tzic_base = irqbase;
165 /* put the TZIC into the reset value with
166 * all interrupts disabled
167 */
168 i = __raw_readl(tzic_base + TZIC_INTCNTL);
169
170 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
171 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
172 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
173
174 for (i = 0; i < 4; i++)
175 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
176
177 /* disable all interrupts */
178 for (i = 0; i < 4; i++)
179 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
180
181 /* all IRQ no FIQ Warning :: No selection */
182
183 irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
184 WARN_ON(irq_base < 0);
185
186 np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
187 domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
188 &irq_domain_simple_ops, NULL);
189 WARN_ON(!domain);
190
191 for (i = 0; i < 4; i++, irq_base += 32)
192 tzic_init_gc(i, irq_base);
193
194#ifdef CONFIG_FIQ
195 /* Initialize FIQ */
196 init_FIQ(FIQ_START);
197#endif
198
199 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
200}
201
202/**
203 * tzic_enable_wake() - enable wakeup interrupt
204 *
205 * @return 0 if successful; non-zero otherwise
206 *
207 * This function provides an interrupt synchronization point that is required
208 * by tzic enabled platforms before entering imx specific low power modes (ie,
209 * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
210 */
211int tzic_enable_wake(void)
212{
213 unsigned int i;
214
215 __raw_writel(1, tzic_base + TZIC_DSMINT);
216 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
217 return -EAGAIN;
218
219 for (i = 0; i < 4; i++)
220 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
221 tzic_base + TZIC_WAKEUP0(i));
222
223 return 0;
224}
diff --git a/arch/arm/mach-imx/ulpi.c b/arch/arm/mach-imx/ulpi.c
new file mode 100644
index 000000000000..d2963427184f
--- /dev/null
+++ b/arch/arm/mach-imx/ulpi.c
@@ -0,0 +1,118 @@
1/*
2 * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright 2009 Daniel Mack <daniel@caiaq.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/delay.h>
24#include <linux/usb/otg.h>
25#include <linux/usb/ulpi.h>
26
27#include <mach/ulpi.h>
28
29/* ULPIVIEW register bits */
30#define ULPIVW_WU (1 << 31) /* Wakeup */
31#define ULPIVW_RUN (1 << 30) /* read/write run */
32#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */
33#define ULPIVW_SS (1 << 27) /* SyncState */
34#define ULPIVW_PORT_MASK 0x07 /* Port field */
35#define ULPIVW_PORT_SHIFT 24
36#define ULPIVW_ADDR_MASK 0xff /* data address field */
37#define ULPIVW_ADDR_SHIFT 16
38#define ULPIVW_RDATA_MASK 0xff /* read data field */
39#define ULPIVW_RDATA_SHIFT 8
40#define ULPIVW_WDATA_MASK 0xff /* write data field */
41#define ULPIVW_WDATA_SHIFT 0
42
43static int ulpi_poll(void __iomem *view, u32 bit)
44{
45 int timeout = 10000;
46
47 while (timeout--) {
48 u32 data = __raw_readl(view);
49
50 if (!(data & bit))
51 return 0;
52
53 cpu_relax();
54 };
55
56 printk(KERN_WARNING "timeout polling for ULPI device\n");
57
58 return -ETIMEDOUT;
59}
60
61static int ulpi_read(struct usb_phy *otg, u32 reg)
62{
63 int ret;
64 void __iomem *view = otg->io_priv;
65
66 /* make sure interface is running */
67 if (!(__raw_readl(view) & ULPIVW_SS)) {
68 __raw_writel(ULPIVW_WU, view);
69
70 /* wait for wakeup */
71 ret = ulpi_poll(view, ULPIVW_WU);
72 if (ret)
73 return ret;
74 }
75
76 /* read the register */
77 __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
78
79 /* wait for completion */
80 ret = ulpi_poll(view, ULPIVW_RUN);
81 if (ret)
82 return ret;
83
84 return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
85}
86
87static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
88{
89 int ret;
90 void __iomem *view = otg->io_priv;
91
92 /* make sure the interface is running */
93 if (!(__raw_readl(view) & ULPIVW_SS)) {
94 __raw_writel(ULPIVW_WU, view);
95 /* wait for wakeup */
96 ret = ulpi_poll(view, ULPIVW_WU);
97 if (ret)
98 return ret;
99 }
100
101 __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
102 (reg << ULPIVW_ADDR_SHIFT) |
103 ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
104
105 /* wait for completion */
106 return ulpi_poll(view, ULPIVW_RUN);
107}
108
109struct usb_phy_io_ops mxc_ulpi_access_ops = {
110 .read = ulpi_read,
111 .write = ulpi_write,
112};
113EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
114
115struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
116{
117 return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
118}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 09:44:16 -0500