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-rw-r--r--arch/arm/mach-imx/Kconfig38
-rw-r--r--arch/arm/mach-imx/Makefile3
-rw-r--r--arch/arm/mach-imx/Makefile.boot4
-rw-r--r--arch/arm/mach-imx/clk-imx25.c3
-rw-r--r--arch/arm/mach-imx/clk-imx27.c9
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c2
-rw-r--r--arch/arm/mach-imx/common.h12
-rw-r--r--arch/arm/mach-imx/cpu-imx5.c39
-rw-r--r--arch/arm/mach-imx/devices-imx50.h33
-rw-r--r--arch/arm/mach-imx/devices/Kconfig2
-rw-r--r--arch/arm/mach-imx/devices/platform-fec.c6
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-i2c.c10
-rw-r--r--arch/arm/mach-imx/devices/platform-imx-uart.c12
-rw-r--r--arch/arm/mach-imx/epit.c15
-rw-r--r--arch/arm/mach-imx/gpc.c2
-rw-r--r--arch/arm/mach-imx/hardware.h6
-rw-r--r--arch/arm/mach-imx/imx25-dt.c11
-rw-r--r--arch/arm/mach-imx/imx27-dt.c16
-rw-r--r--arch/arm/mach-imx/imx31-dt.c16
-rw-r--r--arch/arm/mach-imx/imx51-dt.c16
-rw-r--r--arch/arm/mach-imx/iomux-mx50.h977
-rw-r--r--arch/arm/mach-imx/lluart.c47
-rw-r--r--arch/arm/mach-imx/mach-apf9328.c6
-rw-r--r--arch/arm/mach-imx/mach-armadillo5x0.c6
-rw-r--r--arch/arm/mach-imx/mach-bug.c6
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c6
-rw-r--r--arch/arm/mach-imx/mach-cpuimx35.c6
-rw-r--r--arch/arm/mach-imx/mach-cpuimx51sd.c6
-rw-r--r--arch/arm/mach-imx/mach-eukrea_cpuimx25.c6
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c6
-rw-r--r--arch/arm/mach-imx/mach-imx27ipcam.c6
-rw-r--r--arch/arm/mach-imx/mach-imx27lite.c6
-rw-r--r--arch/arm/mach-imx/mach-imx53.c16
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c20
-rw-r--r--arch/arm/mach-imx/mach-kzm_arm11_01.c6
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c8
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c6
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c6
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c6
-rw-r--r--arch/arm/mach-imx/mach-mx27ads.c6
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c6
-rw-r--r--arch/arm/mach-imx/mach-mx31ads.c6
-rw-r--r--arch/arm/mach-imx/mach-mx31lilly.c6
-rw-r--r--arch/arm/mach-imx/mach-mx31lite.c6
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c6
-rw-r--r--arch/arm/mach-imx/mach-mx35_3ds.c6
-rw-r--r--arch/arm/mach-imx/mach-mx50_rdp.c225
-rw-r--r--arch/arm/mach-imx/mach-mx51_3ds.c178
-rw-r--r--arch/arm/mach-imx/mach-mx51_babbage.c6
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c6
-rw-r--r--arch/arm/mach-imx/mach-pca100.c6
-rw-r--r--arch/arm/mach-imx/mach-pcm037.c6
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c6
-rw-r--r--arch/arm/mach-imx/mach-pcm043.c6
-rw-r--r--arch/arm/mach-imx/mach-qong.c6
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c6
-rw-r--r--arch/arm/mach-imx/mach-vpr200.c6
-rw-r--r--arch/arm/mach-imx/mm-imx5.c48
-rw-r--r--arch/arm/mach-imx/mx50.h290
-rw-r--r--arch/arm/mach-imx/mxc.h13
-rw-r--r--arch/arm/mach-imx/platsmp.c4
-rw-r--r--arch/arm/mach-imx/pm-imx5.c7
-rw-r--r--arch/arm/mach-imx/time.c15
63 files changed, 83 insertions, 2200 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0a2349dc7018..4c9c6f9d2c55 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -95,9 +95,6 @@ config MACH_MX27
95config ARCH_MX5 95config ARCH_MX5
96 bool 96 bool
97 97
98config ARCH_MX50
99 bool
100
101config ARCH_MX51 98config ARCH_MX51
102 bool 99 bool
103 100
@@ -164,11 +161,6 @@ config SOC_IMX5
164 select CPU_V7 161 select CPU_V7
165 select MXC_TZIC 162 select MXC_TZIC
166 163
167config SOC_IMX50
168 bool
169 select ARCH_MX50
170 select SOC_IMX5
171
172config SOC_IMX51 164config SOC_IMX51
173 bool 165 bool
174 select ARCH_MX5 166 select ARCH_MX5
@@ -488,7 +480,7 @@ config MACH_MX31ADS_WM1133_EV1
488 bool "Support Wolfson Microelectronics 1133-EV1 module" 480 bool "Support Wolfson Microelectronics 1133-EV1 module"
489 depends on MACH_MX31ADS 481 depends on MACH_MX31ADS
490 depends on MFD_WM8350_I2C 482 depends on MFD_WM8350_I2C
491 depends on REGULATOR_WM8350 483 depends on REGULATOR_WM8350 = y
492 select MFD_WM8350_CONFIG_MODE_0 484 select MFD_WM8350_CONFIG_MODE_0
493 select MFD_WM8352_CONFIG_MODE_0 485 select MFD_WM8352_CONFIG_MODE_0
494 help 486 help
@@ -738,25 +730,10 @@ endif
738 730
739if ARCH_MULTI_V7 731if ARCH_MULTI_V7
740 732
741comment "i.MX5 platforms:"
742
743config MACH_MX50_RDP
744 bool "Support MX50 reference design platform"
745 depends on BROKEN
746 select IMX_HAVE_PLATFORM_IMX_I2C
747 select IMX_HAVE_PLATFORM_IMX_UART
748 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
749 select IMX_HAVE_PLATFORM_SPI_IMX
750 select SOC_IMX50
751 help
752 Include support for MX50 reference design platform (RDP) board. This
753 includes specific configurations for the board and its peripherals.
754
755comment "i.MX51 machines:" 733comment "i.MX51 machines:"
756 734
757config MACH_IMX51_DT 735config MACH_IMX51_DT
758 bool "Support i.MX51 platforms from device tree" 736 bool "Support i.MX51 platforms from device tree"
759 select MACH_MX51_BABBAGE
760 select SOC_IMX51 737 select SOC_IMX51
761 help 738 help
762 Include support for Freescale i.MX51 based platforms 739 Include support for Freescale i.MX51 based platforms
@@ -777,19 +754,6 @@ config MACH_MX51_BABBAGE
777 u-boot. This includes specific configurations for the board and its 754 u-boot. This includes specific configurations for the board and its
778 peripherals. 755 peripherals.
779 756
780config MACH_MX51_3DS
781 bool "Support MX51PDK (3DS)"
782 select IMX_HAVE_PLATFORM_IMX2_WDT
783 select IMX_HAVE_PLATFORM_IMX_KEYPAD
784 select IMX_HAVE_PLATFORM_IMX_UART
785 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
786 select IMX_HAVE_PLATFORM_SPI_IMX
787 select MXC_DEBUG_BOARD
788 select SOC_IMX51
789 help
790 Include support for MX51PDK (3DS) platform. This includes specific
791 configurations for the board and its peripherals.
792
793config MACH_EUKREA_CPUIMX51SD 757config MACH_EUKREA_CPUIMX51SD
794 bool "Support Eukrea CPUIMX51SD module" 758 bool "Support Eukrea CPUIMX51SD module"
795 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 759 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0634b3152c24..240e0294c372 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -88,7 +88,6 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
88obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o 88obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
89obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o 89obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
90 90
91obj-$(CONFIG_DEBUG_LL) += lluart.o
92obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o 91obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
93obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o 92obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
94obj-$(CONFIG_HAVE_IMX_SRC) += src.o 93obj-$(CONFIG_HAVE_IMX_SRC) += src.o
@@ -103,10 +102,8 @@ endif
103 102
104# i.MX5 based machines 103# i.MX5 based machines
105obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o 104obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
106obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
107obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o 105obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
108obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o 106obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
109obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
110 107
111obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o 108obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
112obj-$(CONFIG_SOC_IMX53) += mach-imx53.o 109obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index b27815de8473..41ba1bb0437b 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -22,10 +22,6 @@ zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000
22params_phys-$(CONFIG_SOC_IMX35) := 0x80000100 22params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
23initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000 23initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
24 24
25zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000
26params_phys-$(CONFIG_SOC_IMX50) := 0x70000100
27initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000
28
29zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000 25zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000
30params_phys-$(CONFIG_SOC_IMX51) := 0x90000100 26params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
31initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000 27initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 2c570cdaae7b..69858c78f40d 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -224,6 +224,9 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
224 224
225 clk_prepare_enable(clk[emi_ahb]); 225 clk_prepare_enable(clk[emi_ahb]);
226 226
227 /* Clock source for gpt must be derived from AHB */
228 clk_set_parent(clk[per5_sel], clk[ahb]);
229
227 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); 230 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
228 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 231 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
229 232
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 1ffe3b534e51..e30369a58e4e 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -228,9 +228,12 @@ int __init mx27_clocks_init(unsigned long fref)
228 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1"); 228 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
229 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2"); 229 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
230 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2"); 230 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
231 clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0"); 231 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
232 clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1"); 232 clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
233 clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2"); 233 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
234 clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
235 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
236 clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
234 clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0"); 237 clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
235 clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0"); 238 clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
236 clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0"); 239 clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index c0c4e723b7f5..19644f6524dc 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -56,8 +56,6 @@
56 56
57static void __iomem *ccm_base; 57static void __iomem *ccm_base;
58 58
59void __init imx6q_clock_map_io(void) { }
60
61int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) 59int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
62{ 60{
63 u32 val = readl_relaxed(ccm_base + CLPCR); 61 u32 val = readl_relaxed(ccm_base + CLPCR);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index fa36fb84ab19..76c420043289 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -21,7 +21,6 @@ extern void mx25_map_io(void);
21extern void mx27_map_io(void); 21extern void mx27_map_io(void);
22extern void mx31_map_io(void); 22extern void mx31_map_io(void);
23extern void mx35_map_io(void); 23extern void mx35_map_io(void);
24extern void mx50_map_io(void);
25extern void mx51_map_io(void); 24extern void mx51_map_io(void);
26extern void mx53_map_io(void); 25extern void mx53_map_io(void);
27extern void imx1_init_early(void); 26extern void imx1_init_early(void);
@@ -30,7 +29,6 @@ extern void imx25_init_early(void);
30extern void imx27_init_early(void); 29extern void imx27_init_early(void);
31extern void imx31_init_early(void); 30extern void imx31_init_early(void);
32extern void imx35_init_early(void); 31extern void imx35_init_early(void);
33extern void imx50_init_early(void);
34extern void imx51_init_early(void); 32extern void imx51_init_early(void);
35extern void imx53_init_early(void); 33extern void imx53_init_early(void);
36extern void mxc_init_irq(void __iomem *); 34extern void mxc_init_irq(void __iomem *);
@@ -41,7 +39,6 @@ extern void mx25_init_irq(void);
41extern void mx27_init_irq(void); 39extern void mx27_init_irq(void);
42extern void mx31_init_irq(void); 40extern void mx31_init_irq(void);
43extern void mx35_init_irq(void); 41extern void mx35_init_irq(void);
44extern void mx50_init_irq(void);
45extern void mx51_init_irq(void); 42extern void mx51_init_irq(void);
46extern void mx53_init_irq(void); 43extern void mx53_init_irq(void);
47extern void imx1_soc_init(void); 44extern void imx1_soc_init(void);
@@ -50,7 +47,6 @@ extern void imx25_soc_init(void);
50extern void imx27_soc_init(void); 47extern void imx27_soc_init(void);
51extern void imx31_soc_init(void); 48extern void imx31_soc_init(void);
52extern void imx35_soc_init(void); 49extern void imx35_soc_init(void);
53extern void imx50_soc_init(void);
54extern void imx51_soc_init(void); 50extern void imx51_soc_init(void);
55extern void imx51_init_late(void); 51extern void imx51_init_late(void);
56extern void imx53_init_late(void); 52extern void imx53_init_late(void);
@@ -109,18 +105,11 @@ void tzic_handle_irq(struct pt_regs *);
109#define imx27_handle_irq avic_handle_irq 105#define imx27_handle_irq avic_handle_irq
110#define imx31_handle_irq avic_handle_irq 106#define imx31_handle_irq avic_handle_irq
111#define imx35_handle_irq avic_handle_irq 107#define imx35_handle_irq avic_handle_irq
112#define imx50_handle_irq tzic_handle_irq
113#define imx51_handle_irq tzic_handle_irq 108#define imx51_handle_irq tzic_handle_irq
114#define imx53_handle_irq tzic_handle_irq 109#define imx53_handle_irq tzic_handle_irq
115#define imx6q_handle_irq gic_handle_irq
116 110
117extern void imx_enable_cpu(int cpu, bool enable); 111extern void imx_enable_cpu(int cpu, bool enable);
118extern void imx_set_cpu_jump(int cpu, void *jump_addr); 112extern void imx_set_cpu_jump(int cpu, void *jump_addr);
119#ifdef CONFIG_DEBUG_LL
120extern void imx_lluart_map_io(void);
121#else
122static inline void imx_lluart_map_io(void) {}
123#endif
124extern void v7_cpu_resume(void); 113extern void v7_cpu_resume(void);
125extern u32 *pl310_get_save_ptr(void); 114extern u32 *pl310_get_save_ptr(void);
126#ifdef CONFIG_SMP 115#ifdef CONFIG_SMP
@@ -139,7 +128,6 @@ extern void imx_gpc_init(void);
139extern void imx_gpc_pre_suspend(void); 128extern void imx_gpc_pre_suspend(void);
140extern void imx_gpc_post_resume(void); 129extern void imx_gpc_post_resume(void);
141extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); 130extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
142extern void imx6q_clock_map_io(void);
143 131
144extern void imx_cpu_die(unsigned int cpu); 132extern void imx_cpu_die(unsigned int cpu);
145extern int imx_cpu_kill(unsigned int cpu); 133extern int imx_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index d88760014ff9..d7ce72252a4e 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -22,7 +22,6 @@
22static int mx5_cpu_rev = -1; 22static int mx5_cpu_rev = -1;
23 23
24#define IIM_SREV 0x24 24#define IIM_SREV 0x24
25#define MX50_HW_ADADIG_DIGPROG 0xB0
26 25
27static int get_mx51_srev(void) 26static int get_mx51_srev(void)
28{ 27{
@@ -108,41 +107,3 @@ int mx53_revision(void)
108 return mx5_cpu_rev; 107 return mx5_cpu_rev;
109} 108}
110EXPORT_SYMBOL(mx53_revision); 109EXPORT_SYMBOL(mx53_revision);
111
112static int get_mx50_srev(void)
113{
114 void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
115 u32 rev;
116
117 if (!anatop) {
118 mx5_cpu_rev = -EINVAL;
119 return 0;
120 }
121
122 rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
123 rev &= 0xff;
124
125 iounmap(anatop);
126 if (rev == 0x0)
127 return IMX_CHIP_REVISION_1_0;
128 else if (rev == 0x1)
129 return IMX_CHIP_REVISION_1_1;
130 return 0;
131}
132
133/*
134 * Returns:
135 * the silicon revision of the cpu
136 * -EINVAL - not a mx50
137 */
138int mx50_revision(void)
139{
140 if (!cpu_is_mx50())
141 return -EINVAL;
142
143 if (mx5_cpu_rev == -1)
144 mx5_cpu_rev = get_mx50_srev();
145
146 return mx5_cpu_rev;
147}
148EXPORT_SYMBOL(mx50_revision);
diff --git a/arch/arm/mach-imx/devices-imx50.h b/arch/arm/mach-imx/devices-imx50.h
deleted file mode 100644
index 2c290391f298..000000000000
--- a/arch/arm/mach-imx/devices-imx50.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include "devices/devices-common.h"
22
23extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
24#define imx50_add_imx_uart(id, pdata) \
25 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
26
27extern const struct imx_fec_data imx50_fec_data;
28#define imx50_add_fec(pdata) \
29 imx_add_fec(&imx50_fec_data, pdata)
30
31extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
32#define imx50_add_imx_i2c(id, pdata) \
33 imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 9a8f1ca7bcb1..9b9ba1f4ffe1 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -1,6 +1,6 @@
1config IMX_HAVE_PLATFORM_FEC 1config IMX_HAVE_PLATFORM_FEC
2 bool 2 bool
3 default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53 3 default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
4 4
5config IMX_HAVE_PLATFORM_FLEXCAN 5config IMX_HAVE_PLATFORM_FLEXCAN
6 bool 6 bool
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
index 2cb188ad9a0a..63eba08f87b1 100644
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ b/arch/arm/mach-imx/devices/platform-fec.c
@@ -35,12 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst =
35 imx_fec_data_entry_single(MX35, "imx27-fec"); 35 imx_fec_data_entry_single(MX35, "imx27-fec");
36#endif 36#endif
37 37
38#ifdef CONFIG_SOC_IMX50
39/* i.mx50 has the i.mx25 type fec */
40const struct imx_fec_data imx50_fec_data __initconst =
41 imx_fec_data_entry_single(MX50, "imx25-fec");
42#endif
43
44#ifdef CONFIG_SOC_IMX51 38#ifdef CONFIG_SOC_IMX51
45/* i.mx51 has the i.mx27 type fec */ 39/* i.mx51 has the i.mx27 type fec */
46const struct imx_fec_data imx51_fec_data __initconst = 40const struct imx_fec_data imx51_fec_data __initconst =
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 8e30e5703cd2..57d342e85c2f 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -70,16 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
70}; 70};
71#endif /* ifdef CONFIG_SOC_IMX35 */ 71#endif /* ifdef CONFIG_SOC_IMX35 */
72 72
73#ifdef CONFIG_SOC_IMX50
74const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
75#define imx50_imx_i2c_data_entry(_id, _hwid) \
76 imx_imx_i2c_data_entry(MX50, "imx21-i2c", _id, _hwid, SZ_4K)
77 imx50_imx_i2c_data_entry(0, 1),
78 imx50_imx_i2c_data_entry(1, 2),
79 imx50_imx_i2c_data_entry(2, 3),
80};
81#endif /* ifdef CONFIG_SOC_IMX51 */
82
83#ifdef CONFIG_SOC_IMX51 73#ifdef CONFIG_SOC_IMX51
84const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { 74const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
85#define imx51_imx_i2c_data_entry(_id, _hwid) \ 75#define imx51_imx_i2c_data_entry(_id, _hwid) \
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index 67bf866a2cb6..faac4aa6ca6d 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -94,18 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
94}; 94};
95#endif /* ifdef CONFIG_SOC_IMX35 */ 95#endif /* ifdef CONFIG_SOC_IMX35 */
96 96
97#ifdef CONFIG_SOC_IMX50
98const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = {
99#define imx50_imx_uart_data_entry(_id, _hwid) \
100 imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K)
101 imx50_imx_uart_data_entry(0, 1),
102 imx50_imx_uart_data_entry(1, 2),
103 imx50_imx_uart_data_entry(2, 3),
104 imx50_imx_uart_data_entry(3, 4),
105 imx50_imx_uart_data_entry(4, 5),
106};
107#endif /* ifdef CONFIG_SOC_IMX50 */
108
109#ifdef CONFIG_SOC_IMX51 97#ifdef CONFIG_SOC_IMX51
110const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { 98const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
111#define imx51_imx_uart_data_entry(_id, _hwid) \ 99#define imx51_imx_uart_data_entry(_id, _hwid) \
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c
index 04a5961beeac..e02de188ae83 100644
--- a/arch/arm/mach-imx/epit.c
+++ b/arch/arm/mach-imx/epit.c
@@ -178,7 +178,6 @@ static struct irqaction epit_timer_irq = {
178static struct clock_event_device clockevent_epit = { 178static struct clock_event_device clockevent_epit = {
179 .name = "epit", 179 .name = "epit",
180 .features = CLOCK_EVT_FEAT_ONESHOT, 180 .features = CLOCK_EVT_FEAT_ONESHOT,
181 .shift = 32,
182 .set_mode = epit_set_mode, 181 .set_mode = epit_set_mode,
183 .set_next_event = epit_set_next_event, 182 .set_next_event = epit_set_next_event,
184 .rating = 200, 183 .rating = 200,
@@ -186,18 +185,10 @@ static struct clock_event_device clockevent_epit = {
186 185
187static int __init epit_clockevent_init(struct clk *timer_clk) 186static int __init epit_clockevent_init(struct clk *timer_clk)
188{ 187{
189 unsigned int c = clk_get_rate(timer_clk);
190
191 clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
192 clockevent_epit.shift);
193 clockevent_epit.max_delta_ns =
194 clockevent_delta2ns(0xfffffffe, &clockevent_epit);
195 clockevent_epit.min_delta_ns =
196 clockevent_delta2ns(0x800, &clockevent_epit);
197
198 clockevent_epit.cpumask = cpumask_of(0); 188 clockevent_epit.cpumask = cpumask_of(0);
199 189 clockevents_config_and_register(&clockevent_epit,
200 clockevents_register_device(&clockevent_epit); 190 clk_get_rate(timer_clk),
191 0x800, 0xfffffffe);
201 192
202 return 0; 193 return 0;
203} 194}
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index e1537f9e45b8..ff24920699e4 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -15,7 +15,7 @@
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/of_irq.h> 17#include <linux/of_irq.h>
18#include <asm/hardware/gic.h> 18#include <linux/irqchip/arm-gic.h>
19 19
20#define GPC_IMR1 0x008 20#define GPC_IMR1 0x008
21#define GPC_PGC_CPU_PDN 0x2a0 21#define GPC_PGC_CPU_PDN 0x2a0
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 3ce7fa3bd43f..911e9b31b03f 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -72,11 +72,6 @@
72 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 72 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
73 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000 73 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
74 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 74 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
75 * mx50:
76 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
77 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
78 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
79 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
80 * mx51: 75 * mx51:
81 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 76 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
82 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 77 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
@@ -108,7 +103,6 @@
108#include "mxc.h" 103#include "mxc.h"
109 104
110#include "mx6q.h" 105#include "mx6q.h"
111#include "mx50.h"
112#include "mx51.h" 106#include "mx51.h"
113#include "mx53.h" 107#include "mx53.h"
114#include "mx3x.h" 108#include "mx3x.h"
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index e17dfbc42192..03b65e5ea541 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -22,15 +22,6 @@ static void __init imx25_dt_init(void)
22 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 22 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
23} 23}
24 24
25static void __init imx25_timer_init(void)
26{
27 mx25_clocks_init_dt();
28}
29
30static struct sys_timer imx25_timer = {
31 .init = imx25_timer_init,
32};
33
34static const char * const imx25_dt_board_compat[] __initconst = { 25static const char * const imx25_dt_board_compat[] __initconst = {
35 "fsl,imx25", 26 "fsl,imx25",
36 NULL 27 NULL
@@ -41,7 +32,7 @@ DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
41 .init_early = imx25_init_early, 32 .init_early = imx25_init_early,
42 .init_irq = mx25_init_irq, 33 .init_irq = mx25_init_irq,
43 .handle_irq = imx25_handle_irq, 34 .handle_irq = imx25_handle_irq,
44 .timer = &imx25_timer, 35 .init_time = imx25_timer_init,
45 .init_machine = imx25_dt_init, 36 .init_machine = imx25_dt_init,
46 .dt_compat = imx25_dt_board_compat, 37 .dt_compat = imx25_dt_board_compat,
47 .restart = mxc_restart, 38 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index ebfae96543c4..c915a490a11c 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -39,26 +39,22 @@ static void __init imx27_dt_init(void)
39 imx27_auxdata_lookup, NULL); 39 imx27_auxdata_lookup, NULL);
40} 40}
41 41
42static void __init imx27_timer_init(void)
43{
44 mx27_clocks_init_dt();
45}
46
47static struct sys_timer imx27_timer = {
48 .init = imx27_timer_init,
49};
50
51static const char * const imx27_dt_board_compat[] __initconst = { 42static const char * const imx27_dt_board_compat[] __initconst = {
52 "fsl,imx27", 43 "fsl,imx27",
53 NULL 44 NULL
54}; 45};
55 46
47static void __init imx27_timer_init(void)
48{
49 mx27_clocks_init_dt();
50}
51
56DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") 52DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
57 .map_io = mx27_map_io, 53 .map_io = mx27_map_io,
58 .init_early = imx27_init_early, 54 .init_early = imx27_init_early,
59 .init_irq = mx27_init_irq, 55 .init_irq = mx27_init_irq,
60 .handle_irq = imx27_handle_irq, 56 .handle_irq = imx27_handle_irq,
61 .timer = &imx27_timer, 57 .init_time = imx27_timer_init,
62 .init_machine = imx27_dt_init, 58 .init_machine = imx27_dt_init,
63 .dt_compat = imx27_dt_board_compat, 59 .dt_compat = imx27_dt_board_compat,
64 .restart = mxc_restart, 60 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index af476de2570e..b5c04eece780 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -38,26 +38,22 @@ static void __init imx31_dt_init(void)
38 imx31_auxdata_lookup, NULL); 38 imx31_auxdata_lookup, NULL);
39} 39}
40 40
41static void __init imx31_timer_init(void)
42{
43 mx31_clocks_init_dt();
44}
45
46static struct sys_timer imx31_timer = {
47 .init = imx31_timer_init,
48};
49
50static const char *imx31_dt_board_compat[] __initdata = { 41static const char *imx31_dt_board_compat[] __initdata = {
51 "fsl,imx31", 42 "fsl,imx31",
52 NULL 43 NULL
53}; 44};
54 45
46static void __init imx31_dt_timer_init(void)
47{
48 mx31_clocks_init_dt();
49}
50
55DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") 51DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
56 .map_io = mx31_map_io, 52 .map_io = mx31_map_io,
57 .init_early = imx31_init_early, 53 .init_early = imx31_init_early,
58 .init_irq = mx31_init_irq, 54 .init_irq = mx31_init_irq,
59 .handle_irq = imx31_handle_irq, 55 .handle_irq = imx31_handle_irq,
60 .timer = &imx31_timer, 56 .init_time = imx31_dt_timer_init,
61 .init_machine = imx31_dt_init, 57 .init_machine = imx31_dt_init,
62 .dt_compat = imx31_dt_board_compat, 58 .dt_compat = imx31_dt_board_compat,
63 .restart = mxc_restart, 59 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 5ffa40c673f8..e2926a8863f8 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -24,26 +24,22 @@ static void __init imx51_dt_init(void)
24 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 24 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
25} 25}
26 26
27static void __init imx51_timer_init(void)
28{
29 mx51_clocks_init_dt();
30}
31
32static struct sys_timer imx51_timer = {
33 .init = imx51_timer_init,
34};
35
36static const char *imx51_dt_board_compat[] __initdata = { 27static const char *imx51_dt_board_compat[] __initdata = {
37 "fsl,imx51", 28 "fsl,imx51",
38 NULL 29 NULL
39}; 30};
40 31
32static void __init imx51_timer_init(void)
33{
34 mx51_clocks_init_dt();
35}
36
41DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") 37DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
42 .map_io = mx51_map_io, 38 .map_io = mx51_map_io,
43 .init_early = imx51_init_early, 39 .init_early = imx51_init_early,
44 .init_irq = mx51_init_irq, 40 .init_irq = mx51_init_irq,
45 .handle_irq = imx51_handle_irq, 41 .handle_irq = imx51_handle_irq,
46 .timer = &imx51_timer, 42 .init_time = imx51_timer_init,
47 .init_machine = imx51_dt_init, 43 .init_machine = imx51_dt_init,
48 .init_late = imx51_init_late, 44 .init_late = imx51_init_late,
49 .dt_compat = imx51_dt_board_compat, 45 .dt_compat = imx51_dt_board_compat,
diff --git a/arch/arm/mach-imx/iomux-mx50.h b/arch/arm/mach-imx/iomux-mx50.h
deleted file mode 100644
index 00f56e0e8009..000000000000
--- a/arch/arm/mach-imx/iomux-mx50.h
+++ /dev/null
@@ -1,977 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_IOMUX_MX50_H__
20#define __MACH_IOMUX_MX50_H__
21
22#include "iomux-v3.h"
23
24#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
25
26#define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
27 PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
28
29#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE)
30
31#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \
32 PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
33
34#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
36
37#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
38 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \
39 PAD_CTL_DSE_HIGH)
40
41#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
42 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \
43 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
44
45#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
46 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)
47
48#define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \
49 PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH)
50
51#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
52#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL)
53#define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
54
55#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL)
56#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL)
57#define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
58
59#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
60#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL)
61#define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
62
63#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
64#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL)
65#define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
66
67#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL)
68#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL)
69#define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
70
71#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL)
72#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL)
73#define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
74
75#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
76#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL)
77#define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \
78 PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
79#define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL)
80
81#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
82#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL)
83#define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH)
84#define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL)
85
86#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
87 MX50_I2C_PAD_CTRL)
88#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
89#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL)
90
91#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
92 MX50_I2C_PAD_CTRL)
93#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL)
94#define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL)
95
96#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
97 MX50_I2C_PAD_CTRL)
98#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL)
100#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
101
102#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
103 MX50_I2C_PAD_CTRL)
104#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL)
105#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL)
106#define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL)
107
108#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \
109 MX50_I2C_PAD_CTRL)
110#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL)
111#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
112#define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL)
113#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL)
114#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL)
115
116#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \
117 MX50_I2C_PAD_CTRL)
118#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL)
119#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL)
120#define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL)
121#define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL)
122#define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL)
123#define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \
124 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
125
126#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
127#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL)
128#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL)
129#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL)
130
131#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
132#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL)
133#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \
134 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
135#define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL)
136#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL)
137#define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL)
138
139#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL)
140#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL)
141#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL)
142#define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL)
144#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL)
145
146#define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
147#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL)
148#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \
149 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
150#define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL)
151#define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL)
152#define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL)
153
154#define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
155#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL)
156#define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL)
157#define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL)
158
159#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
160#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL)
161
162#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
163#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL)
164
165#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
166#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL)
167#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL)
168
169#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
170#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL)
171#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD)
172
173#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
174#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
175#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
176#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
177#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
178#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
179#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH)
180
181#define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
182#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL)
183#define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL)
184#define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL)
185#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD)
186#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
187#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
188
189#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL)
190#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
191
192#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
193#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
194
195#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
196#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
197#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
198#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
199#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
200
201#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
202#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
203#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
204#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL)
205#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL)
206
207#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL)
208#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
209#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
210#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
211
212#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL)
213#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL)
214#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
215#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
216
217#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
218#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
219#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
220#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
221
222#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL)
223#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL)
224#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
225#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
226
227#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL)
228#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
229#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
230#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
231#define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL)
232#define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL)
233
234#define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL)
235#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL)
236#define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
237#define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL)
238#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
239#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
240
241#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL)
242#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
243#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL)
244#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
245#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
246#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
247#define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL)
248
249#define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL)
250#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL)
251#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL)
252#define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
253#define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL)
254#define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL)
255#define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL)
256
257#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
258#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL)
259
260#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
261#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL)
262
263#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
264#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL)
265
266#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
267#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL)
268
269#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
270#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL)
271#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL)
272#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL)
273#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL)
274#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL)
275#define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL)
276
277#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
278#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
279#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
280#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
281#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
282#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
283#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
284
285#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
286#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL)
287#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD)
288#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
289#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL)
290#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL)
291#define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL)
292
293#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
294#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
295#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
296#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
297#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL)
298#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
299#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
300
301#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL)
303#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL)
304#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL)
305#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL)
306#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL)
307#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL)
308#define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL)
309
310#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
311#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
312#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
313#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
314#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
315#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
316#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
317#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
318
319#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
320#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
321#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
322#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
323#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL)
324#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL)
325#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
326#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
327
328#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
329#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL)
330#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL)
331#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
332#define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL)
333#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL)
334#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL)
335#define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL)
336
337#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
338#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL)
339#define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL)
340
341#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
342#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL)
343#define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL)
344
345#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL)
346#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL)
347#define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL)
348
349#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL)
350#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL)
351#define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL)
352
353#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL)
354#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL)
355#define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL)
356
357#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL)
358#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL)
359
360#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
361#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
362#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL)
363
364#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
365#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
366#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL)
367
368#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL)
369#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL)
370#define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL)
371#define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL)
372
373#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL)
374#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL)
375#define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL)
376#define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL)
377
378#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
379#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL)
380#define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL)
381#define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL)
382
383#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL)
384#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL)
385#define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL)
386#define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL)
387
388#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL)
389#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL)
390#define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL)
391#define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL)
392#define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL)
393#define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL)
394
395#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL)
396#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
397#define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL)
398#define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL)
399#define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL)
400#define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL)
401
402#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
403#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL)
404#define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL)
405#define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL)
406#define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL)
407#define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL)
408
409#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL)
410#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL)
411#define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL)
412#define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL)
413#define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL)
414#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL)
415
416#define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL)
417#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL)
418#define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL)
419#define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL)
420#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL)
421
422#define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL)
423#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL)
424#define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL)
425#define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL)
426#define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL)
427
428#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL)
429
430#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL)
431
432#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL)
433
434#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL)
435
436#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL)
437
438#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL)
439
440#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL)
441
442#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL)
443
444#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL)
445
446#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL)
447
448#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL)
449
450#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL)
451
452#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL)
453
454#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL)
455#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL)
456#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE)
457
458#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL)
459#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL)
460#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE)
461#define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
462
463#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL)
464#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL)
465#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE)
466#define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
467
468#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL)
469#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL)
470#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE)
471#define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
472#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL)
473
474#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL)
475#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL)
476#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE)
477#define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
478
479#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL)
480#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL)
481#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
482#define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
483
484#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL)
485#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL)
486#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
487#define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
488#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL)
489
490#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL)
491#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
492#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
493#define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
494
495
496#define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
497#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL)
498#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
499#define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
500
501#define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
502#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL)
503#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
504#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
505
506#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
507#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
508#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
509#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
510
511#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
512#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
513#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL)
514#define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
515#define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL)
516
517#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL)
518#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL)
519#define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
520
521#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
522#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL)
523#define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL)
524
525#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL)
526#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL)
527#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
528#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
529
530#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL)
531#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL)
532#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
533#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
534
535#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
536#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL)
537#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
538#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
539#define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL)
540
541#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL)
542#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL)
543#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
544#define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL)
545
546#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL)
547#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL)
548#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
549#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
550#define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL)
551
552#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL)
553#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL)
554#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
555#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
556
557#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
558#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
559#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
560#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
561
562#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL)
563#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL)
564#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
565#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
566
567#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL)
568#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL)
569#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
570#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
571
572#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL)
573#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL)
574#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
575#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
576
577#define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
578#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL)
579#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
580#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
581#define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL)
582#define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL)
583
584#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL)
585#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL)
586#define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL)
587#define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL)
588#define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL)
589#define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL)
590#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL)
591
592#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL)
593#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL)
594#define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL)
595#define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL)
596#define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL)
597#define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL)
598#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL)
599
600#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL)
601#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL)
602#define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL)
603#define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL)
604#define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL)
605#define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL)
606#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL)
607
608#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL)
609#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL)
610#define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL)
611#define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL)
612#define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL)
613#define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL)
614
615#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL)
616#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL)
617#define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL)
618#define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
619#define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL)
620#define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL)
621#define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL)
622
623#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL)
624#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL)
625#define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL)
626#define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
627#define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL)
628#define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL)
629#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL)
630
631#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL)
632#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL)
633#define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL)
634#define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
635#define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL)
636#define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL)
637#define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL)
638
639#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL)
640#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL)
641#define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL)
642#define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
643#define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL)
644#define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL)
645#define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL)
646
647#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
648#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL)
649#define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL)
650#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
651#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
652
653#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
654#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL)
655#define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL)
656#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
657#define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
658
659#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
660#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL)
661#define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL)
662#define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
663#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL)
664
665#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
666#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL)
667#define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL)
668#define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
669#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL)
670
671#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
672#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL)
673#define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL)
674
675#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
676#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL)
677#define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL)
678
679#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
680#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL)
681#define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL)
682
683#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
684#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL)
685#define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL)
686
687#define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
688#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL)
689#define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL)
690#define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
691
692#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
693#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
694#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL)
695#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
696
697#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
698#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
699#define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL)
700#define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
701
702#define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
703#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL)
704#define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL)
705#define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
706
707#define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
708#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL)
709#define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL)
710#define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
711
712#define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
713#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL)
714#define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL)
715#define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
716
717#define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
718#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL)
719#define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL)
720#define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
721#define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL)
722
723#define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
724#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL)
725#define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL)
726#define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
727#define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL)
728
729#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
730#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL)
731#define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL)
732#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
733#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL)
734
735#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
736#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL)
737#define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL)
738#define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
739#define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL)
740
741#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
742#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL)
743#define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL)
744#define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
745#define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL)
746
747#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
748#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL)
749#define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL)
750#define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
751#define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL)
752
753#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
754#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
755#define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL)
756#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
757#define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL)
758
759#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
760#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
761#define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL)
762#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
763#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL)
764
765#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
766#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
767#define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL)
768#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
769#define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL)
770
771#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
772#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL)
773#define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL)
774#define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
775#define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL)
776
777#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
778#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL)
779#define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL)
780#define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL)
781#define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL)
782
783#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
784#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL)
785#define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL)
786#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL)
787#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL)
788
789#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
790#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL)
791#define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL)
792#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL)
793#define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL)
794
795#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
796#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL)
797#define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL)
798#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL)
799#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL)
800
801#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
802#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL)
803#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL)
804#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL)
805#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL)
806
807#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
808#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL)
809#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL)
810#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL)
811#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL)
812
813#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
814#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL)
815#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL)
816#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL)
817#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL)
818
819#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
820#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL)
821#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL)
822#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL)
823#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL)
824#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL)
825
826#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
827#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
828#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL)
829#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL)
830
831#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
832#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
833#define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL)
834
835#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
836#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
837#define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL)
838
839#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
840#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL)
841#define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL)
842
843#define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
844#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
845#define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL)
846
847#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
848#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
849#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL)
850
851#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
852#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL)
853#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL)
854
855#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
856#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL)
857#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL)
858
859#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
860#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL)
861#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL)
862
863#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
864#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
865#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL)
866
867#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
868#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL)
869#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL)
870
871#define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
872#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL)
873#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL)
874
875#define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
876#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL)
877#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL)
878
879#define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
880#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL)
881#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL)
882
883#define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
884#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL)
885#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL)
886
887#define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
888#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL)
889#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL)
890
891#define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
892#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL)
893#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL)
894
895#define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL)
896#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL)
897#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL)
898
899#define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
900#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
901#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL)
902
903#define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
904#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL)
905#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
906
907#define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
908#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
909#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
910
911#define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
912#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
913#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
914
915#define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
916#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL)
917#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
918
919#define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
920#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL)
921#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
922#define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL)
923
924#define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
925#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL)
926#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
927#define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL)
928
929#define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
930#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
931#define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \
932 PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
933#define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL)
934
935#define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
936#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL)
937#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH)
938#define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL)
939
940#define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
941#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL)
942#define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
943
944#define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
945#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL)
946
947#define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
948#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL)
949
950#define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
951#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL)
952
953#define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
954#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL)
955
956#define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
957#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL)
958
959#define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
960#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL)
961
962#define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
963#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL)
964
965#define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
966#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL)
967
968#define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
969#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL)
970
971#define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
972#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL)
973
974#define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
975#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL)
976
977#endif /* __MACH_IOMUX_MX50_H__ */
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
deleted file mode 100644
index 2fdc9bf2fb5e..000000000000
--- a/arch/arm/mach-imx/lluart.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <asm/page.h>
15#include <asm/sizes.h>
16#include <asm/mach/map.h>
17
18#include "hardware.h"
19
20#define IMX6Q_UART1_BASE_ADDR 0x02020000
21#define IMX6Q_UART2_BASE_ADDR 0x021e8000
22#define IMX6Q_UART3_BASE_ADDR 0x021ec000
23#define IMX6Q_UART4_BASE_ADDR 0x021f0000
24#define IMX6Q_UART5_BASE_ADDR 0x021f4000
25
26/*
27 * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
28 * of IMX6Q_UART##n##_BASE_ADDR.
29 */
30#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
31#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
32#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
33
34static struct map_desc imx_lluart_desc = {
35#ifdef CONFIG_DEBUG_IMX6Q_UART
36 .virtual = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE),
37 .pfn = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE),
38 .length = 0x4000,
39 .type = MT_DEVICE,
40#endif
41};
42
43void __init imx_lluart_map_io(void)
44{
45 if (imx_lluart_desc.virtual)
46 iotable_init(&imx_lluart_desc, 1);
47}
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 5c9bd2c66e6d..067580b2969b 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -137,17 +137,13 @@ static void __init apf9328_timer_init(void)
137 mx1_clocks_init(32768); 137 mx1_clocks_init(32768);
138} 138}
139 139
140static struct sys_timer apf9328_timer = {
141 .init = apf9328_timer_init,
142};
143
144MACHINE_START(APF9328, "Armadeus APF9328") 140MACHINE_START(APF9328, "Armadeus APF9328")
145 /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */ 141 /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */
146 .map_io = mx1_map_io, 142 .map_io = mx1_map_io,
147 .init_early = imx1_init_early, 143 .init_early = imx1_init_early,
148 .init_irq = mx1_init_irq, 144 .init_irq = mx1_init_irq,
149 .handle_irq = imx1_handle_irq, 145 .handle_irq = imx1_handle_irq,
150 .timer = &apf9328_timer, 146 .init_time = apf9328_timer_init,
151 .init_machine = apf9328_init, 147 .init_machine = apf9328_init,
152 .restart = mxc_restart, 148 .restart = mxc_restart,
153MACHINE_END 149MACHINE_END
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 59bd6b06a6b5..368a6e3f5926 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -557,10 +557,6 @@ static void __init armadillo5x0_timer_init(void)
557 mx31_clocks_init(26000000); 557 mx31_clocks_init(26000000);
558} 558}
559 559
560static struct sys_timer armadillo5x0_timer = {
561 .init = armadillo5x0_timer_init,
562};
563
564MACHINE_START(ARMADILLO5X0, "Armadillo-500") 560MACHINE_START(ARMADILLO5X0, "Armadillo-500")
565 /* Maintainer: Alberto Panizzo */ 561 /* Maintainer: Alberto Panizzo */
566 .atag_offset = 0x100, 562 .atag_offset = 0x100,
@@ -568,7 +564,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
568 .init_early = imx31_init_early, 564 .init_early = imx31_init_early,
569 .init_irq = mx31_init_irq, 565 .init_irq = mx31_init_irq,
570 .handle_irq = imx31_handle_irq, 566 .handle_irq = imx31_handle_irq,
571 .timer = &armadillo5x0_timer, 567 .init_time = armadillo5x0_timer_init,
572 .init_machine = armadillo5x0_init, 568 .init_machine = armadillo5x0_init,
573 .restart = mxc_restart, 569 .restart = mxc_restart,
574MACHINE_END 570MACHINE_END
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index 3a39d5aec07a..2d00476f7d2c 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -53,16 +53,12 @@ static void __init bug_timer_init(void)
53 mx31_clocks_init(26000000); 53 mx31_clocks_init(26000000);
54} 54}
55 55
56static struct sys_timer bug_timer = {
57 .init = bug_timer_init,
58};
59
60MACHINE_START(BUG, "BugLabs BUGBase") 56MACHINE_START(BUG, "BugLabs BUGBase")
61 .map_io = mx31_map_io, 57 .map_io = mx31_map_io,
62 .init_early = imx31_init_early, 58 .init_early = imx31_init_early,
63 .init_irq = mx31_init_irq, 59 .init_irq = mx31_init_irq,
64 .handle_irq = imx31_handle_irq, 60 .handle_irq = imx31_handle_irq,
65 .timer = &bug_timer, 61 .init_time = bug_timer_init,
66 .init_machine = bug_board_init, 62 .init_machine = bug_board_init,
67 .restart = mxc_restart, 63 .restart = mxc_restart,
68MACHINE_END 64MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 12a370646b45..146559311bd2 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -309,17 +309,13 @@ static void __init eukrea_cpuimx27_timer_init(void)
309 mx27_clocks_init(26000000); 309 mx27_clocks_init(26000000);
310} 310}
311 311
312static struct sys_timer eukrea_cpuimx27_timer = {
313 .init = eukrea_cpuimx27_timer_init,
314};
315
316MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27") 312MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
317 .atag_offset = 0x100, 313 .atag_offset = 0x100,
318 .map_io = mx27_map_io, 314 .map_io = mx27_map_io,
319 .init_early = imx27_init_early, 315 .init_early = imx27_init_early,
320 .init_irq = mx27_init_irq, 316 .init_irq = mx27_init_irq,
321 .handle_irq = imx27_handle_irq, 317 .handle_irq = imx27_handle_irq,
322 .timer = &eukrea_cpuimx27_timer, 318 .init_time = eukrea_cpuimx27_timer_init,
323 .init_machine = eukrea_cpuimx27_init, 319 .init_machine = eukrea_cpuimx27_init,
324 .restart = mxc_restart, 320 .restart = mxc_restart,
325MACHINE_END 321MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 5a31bf8c8f4c..771362d1fbee 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -193,10 +193,6 @@ static void __init eukrea_cpuimx35_timer_init(void)
193 mx35_clocks_init(); 193 mx35_clocks_init();
194} 194}
195 195
196static struct sys_timer eukrea_cpuimx35_timer = {
197 .init = eukrea_cpuimx35_timer_init,
198};
199
200MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35") 196MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
201 /* Maintainer: Eukrea Electromatique */ 197 /* Maintainer: Eukrea Electromatique */
202 .atag_offset = 0x100, 198 .atag_offset = 0x100,
@@ -204,7 +200,7 @@ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
204 .init_early = imx35_init_early, 200 .init_early = imx35_init_early,
205 .init_irq = mx35_init_irq, 201 .init_irq = mx35_init_irq,
206 .handle_irq = imx35_handle_irq, 202 .handle_irq = imx35_handle_irq,
207 .timer = &eukrea_cpuimx35_timer, 203 .init_time = eukrea_cpuimx35_timer_init,
208 .init_machine = eukrea_cpuimx35_init, 204 .init_machine = eukrea_cpuimx35_init,
209 .restart = mxc_restart, 205 .restart = mxc_restart,
210MACHINE_END 206MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index b727de029c8f..9b7393234f6f 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -355,10 +355,6 @@ static void __init eukrea_cpuimx51sd_timer_init(void)
355 mx51_clocks_init(32768, 24000000, 22579200, 0); 355 mx51_clocks_init(32768, 24000000, 22579200, 0);
356} 356}
357 357
358static struct sys_timer mxc_timer = {
359 .init = eukrea_cpuimx51sd_timer_init,
360};
361
362MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") 358MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
363 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 359 /* Maintainer: Eric Bénard <eric@eukrea.com> */
364 .atag_offset = 0x100, 360 .atag_offset = 0x100,
@@ -366,7 +362,7 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
366 .init_early = imx51_init_early, 362 .init_early = imx51_init_early,
367 .init_irq = mx51_init_irq, 363 .init_irq = mx51_init_irq,
368 .handle_irq = imx51_handle_irq, 364 .handle_irq = imx51_handle_irq,
369 .timer = &mxc_timer, 365 .init_time = eukrea_cpuimx51sd_timer_init,
370 .init_machine = eukrea_cpuimx51sd_init, 366 .init_machine = eukrea_cpuimx51sd_init,
371 .init_late = imx51_init_late, 367 .init_late = imx51_init_late,
372 .restart = mxc_restart, 368 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 75027a5ad8b7..4bf454424249 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -159,10 +159,6 @@ static void __init eukrea_cpuimx25_timer_init(void)
159 mx25_clocks_init(); 159 mx25_clocks_init();
160} 160}
161 161
162static struct sys_timer eukrea_cpuimx25_timer = {
163 .init = eukrea_cpuimx25_timer_init,
164};
165
166MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25") 162MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
167 /* Maintainer: Eukrea Electromatique */ 163 /* Maintainer: Eukrea Electromatique */
168 .atag_offset = 0x100, 164 .atag_offset = 0x100,
@@ -170,7 +166,7 @@ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
170 .init_early = imx25_init_early, 166 .init_early = imx25_init_early,
171 .init_irq = mx25_init_irq, 167 .init_irq = mx25_init_irq,
172 .handle_irq = imx25_handle_irq, 168 .handle_irq = imx25_handle_irq,
173 .timer = &eukrea_cpuimx25_timer, 169 .init_time = eukrea_cpuimx25_timer_init,
174 .init_machine = eukrea_cpuimx25_init, 170 .init_machine = eukrea_cpuimx25_init,
175 .restart = mxc_restart, 171 .restart = mxc_restart,
176MACHINE_END 172MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 318bd8df7fcc..29ac8ee651d2 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -598,10 +598,6 @@ static void __init visstrim_m10_timer_init(void)
598 mx27_clocks_init((unsigned long)25000000); 598 mx27_clocks_init((unsigned long)25000000);
599} 599}
600 600
601static struct sys_timer visstrim_m10_timer = {
602 .init = visstrim_m10_timer_init,
603};
604
605MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") 601MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
606 .atag_offset = 0x100, 602 .atag_offset = 0x100,
607 .reserve = visstrim_reserve, 603 .reserve = visstrim_reserve,
@@ -609,7 +605,7 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
609 .init_early = imx27_init_early, 605 .init_early = imx27_init_early,
610 .init_irq = mx27_init_irq, 606 .init_irq = mx27_init_irq,
611 .handle_irq = imx27_handle_irq, 607 .handle_irq = imx27_handle_irq,
612 .timer = &visstrim_m10_timer, 608 .init_time = visstrim_m10_timer_init,
613 .init_machine = visstrim_m10_board_init, 609 .init_machine = visstrim_m10_board_init,
614 .restart = mxc_restart, 610 .restart = mxc_restart,
615MACHINE_END 611MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 53a860112938..1a851aea6832 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -65,10 +65,6 @@ static void __init mx27ipcam_timer_init(void)
65 mx27_clocks_init(25000000); 65 mx27_clocks_init(25000000);
66} 66}
67 67
68static struct sys_timer mx27ipcam_timer = {
69 .init = mx27ipcam_timer_init,
70};
71
72MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") 68MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
73 /* maintainer: Freescale Semiconductor, Inc. */ 69 /* maintainer: Freescale Semiconductor, Inc. */
74 .atag_offset = 0x100, 70 .atag_offset = 0x100,
@@ -76,7 +72,7 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
76 .init_early = imx27_init_early, 72 .init_early = imx27_init_early,
77 .init_irq = mx27_init_irq, 73 .init_irq = mx27_init_irq,
78 .handle_irq = imx27_handle_irq, 74 .handle_irq = imx27_handle_irq,
79 .timer = &mx27ipcam_timer, 75 .init_time = mx27ipcam_timer_init,
80 .init_machine = mx27ipcam_init, 76 .init_machine = mx27ipcam_init,
81 .restart = mxc_restart, 77 .restart = mxc_restart,
82MACHINE_END 78MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index fc8dce931378..3da2e3e44ce9 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -72,17 +72,13 @@ static void __init mx27lite_timer_init(void)
72 mx27_clocks_init(26000000); 72 mx27_clocks_init(26000000);
73} 73}
74 74
75static struct sys_timer mx27lite_timer = {
76 .init = mx27lite_timer_init,
77};
78
79MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") 75MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
80 .atag_offset = 0x100, 76 .atag_offset = 0x100,
81 .map_io = mx27_map_io, 77 .map_io = mx27_map_io,
82 .init_early = imx27_init_early, 78 .init_early = imx27_init_early,
83 .init_irq = mx27_init_irq, 79 .init_irq = mx27_init_irq,
84 .handle_irq = imx27_handle_irq, 80 .handle_irq = imx27_handle_irq,
85 .timer = &mx27lite_timer, 81 .init_time = mx27lite_timer_init,
86 .init_machine = mx27lite_init, 82 .init_machine = mx27lite_init,
87 .restart = mxc_restart, 83 .restart = mxc_restart,
88MACHINE_END 84MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 860284dea0e7..f579c616feed 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -44,26 +44,22 @@ static void __init imx53_dt_init(void)
44 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 44 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
45} 45}
46 46
47static void __init imx53_timer_init(void)
48{
49 mx53_clocks_init_dt();
50}
51
52static struct sys_timer imx53_timer = {
53 .init = imx53_timer_init,
54};
55
56static const char *imx53_dt_board_compat[] __initdata = { 47static const char *imx53_dt_board_compat[] __initdata = {
57 "fsl,imx53", 48 "fsl,imx53",
58 NULL 49 NULL
59}; 50};
60 51
52static void __init imx53_timer_init(void)
53{
54 mx53_clocks_init_dt();
55}
56
61DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") 57DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
62 .map_io = mx53_map_io, 58 .map_io = mx53_map_io,
63 .init_early = imx53_init_early, 59 .init_early = imx53_init_early,
64 .init_irq = mx53_init_irq, 60 .init_irq = mx53_init_irq,
65 .handle_irq = imx53_handle_irq, 61 .handle_irq = imx53_handle_irq,
66 .timer = &imx53_timer, 62 .init_time = imx53_timer_init,
67 .init_machine = imx53_dt_init, 63 .init_machine = imx53_dt_init,
68 .init_late = imx53_init_late, 64 .init_late = imx53_init_late,
69 .dt_compat = imx53_dt_board_compat, 65 .dt_compat = imx53_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 4eb1b3ac794c..5a18e7e5c564 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -18,6 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/irqchip.h>
21#include <linux/of.h> 22#include <linux/of.h>
22#include <linux/of_address.h> 23#include <linux/of_address.h>
23#include <linux/of_irq.h> 24#include <linux/of_irq.h>
@@ -29,8 +30,8 @@
29#include <asm/cpuidle.h> 30#include <asm/cpuidle.h>
30#include <asm/smp_twd.h> 31#include <asm/smp_twd.h>
31#include <asm/hardware/cache-l2x0.h> 32#include <asm/hardware/cache-l2x0.h>
32#include <asm/hardware/gic.h>
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
34#include <asm/mach/time.h> 35#include <asm/mach/time.h>
35#include <asm/system_misc.h> 36#include <asm/system_misc.h>
36 37
@@ -216,22 +217,16 @@ static void __init imx6q_init_late(void)
216 217
217static void __init imx6q_map_io(void) 218static void __init imx6q_map_io(void)
218{ 219{
219 imx_lluart_map_io(); 220 debug_ll_io_init();
220 imx_scu_map_io(); 221 imx_scu_map_io();
221 imx6q_clock_map_io();
222} 222}
223 223
224static const struct of_device_id imx6q_irq_match[] __initconst = {
225 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
226 { /* sentinel */ }
227};
228
229static void __init imx6q_init_irq(void) 224static void __init imx6q_init_irq(void)
230{ 225{
231 l2x0_of_init(0, ~0UL); 226 l2x0_of_init(0, ~0UL);
232 imx_src_init(); 227 imx_src_init();
233 imx_gpc_init(); 228 imx_gpc_init();
234 of_irq_init(imx6q_irq_match); 229 irqchip_init();
235} 230}
236 231
237static void __init imx6q_timer_init(void) 232static void __init imx6q_timer_init(void)
@@ -241,10 +236,6 @@ static void __init imx6q_timer_init(void)
241 imx_print_silicon_rev("i.MX6Q", imx6q_revision()); 236 imx_print_silicon_rev("i.MX6Q", imx6q_revision());
242} 237}
243 238
244static struct sys_timer imx6q_timer = {
245 .init = imx6q_timer_init,
246};
247
248static const char *imx6q_dt_compat[] __initdata = { 239static const char *imx6q_dt_compat[] __initdata = {
249 "fsl,imx6q", 240 "fsl,imx6q",
250 NULL, 241 NULL,
@@ -254,8 +245,7 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
254 .smp = smp_ops(imx_smp_ops), 245 .smp = smp_ops(imx_smp_ops),
255 .map_io = imx6q_map_io, 246 .map_io = imx6q_map_io,
256 .init_irq = imx6q_init_irq, 247 .init_irq = imx6q_init_irq,
257 .handle_irq = imx6q_handle_irq, 248 .init_time = imx6q_timer_init,
258 .timer = &imx6q_timer,
259 .init_machine = imx6q_init_machine, 249 .init_machine = imx6q_init_machine,
260 .init_late = imx6q_init_late, 250 .init_late = imx6q_init_late,
261 .dt_compat = imx6q_dt_compat, 251 .dt_compat = imx6q_dt_compat,
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 2e536ea53444..c7bc41d6b468 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -284,17 +284,13 @@ static void __init kzm_timer_init(void)
284 mx31_clocks_init(26000000); 284 mx31_clocks_init(26000000);
285} 285}
286 286
287static struct sys_timer kzm_timer = {
288 .init = kzm_timer_init,
289};
290
291MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") 287MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
292 .atag_offset = 0x100, 288 .atag_offset = 0x100,
293 .map_io = kzm_map_io, 289 .map_io = kzm_map_io,
294 .init_early = imx31_init_early, 290 .init_early = imx31_init_early,
295 .init_irq = mx31_init_irq, 291 .init_irq = mx31_init_irq,
296 .handle_irq = imx31_handle_irq, 292 .handle_irq = imx31_handle_irq,
297 .timer = &kzm_timer, 293 .init_time = kzm_timer_init,
298 .init_machine = kzm_board_init, 294 .init_machine = kzm_board_init,
299 .restart = mxc_restart, 295 .restart = mxc_restart,
300MACHINE_END 296MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 06b483783e68..9f883e4d6fc9 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -132,10 +132,6 @@ static void __init mx1ads_timer_init(void)
132 mx1_clocks_init(32000); 132 mx1_clocks_init(32000);
133} 133}
134 134
135static struct sys_timer mx1ads_timer = {
136 .init = mx1ads_timer_init,
137};
138
139MACHINE_START(MX1ADS, "Freescale MX1ADS") 135MACHINE_START(MX1ADS, "Freescale MX1ADS")
140 /* Maintainer: Sascha Hauer, Pengutronix */ 136 /* Maintainer: Sascha Hauer, Pengutronix */
141 .atag_offset = 0x100, 137 .atag_offset = 0x100,
@@ -143,7 +139,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
143 .init_early = imx1_init_early, 139 .init_early = imx1_init_early,
144 .init_irq = mx1_init_irq, 140 .init_irq = mx1_init_irq,
145 .handle_irq = imx1_handle_irq, 141 .handle_irq = imx1_handle_irq,
146 .timer = &mx1ads_timer, 142 .init_time = mx1ads_timer_init,
147 .init_machine = mx1ads_init, 143 .init_machine = mx1ads_init,
148 .restart = mxc_restart, 144 .restart = mxc_restart,
149MACHINE_END 145MACHINE_END
@@ -154,7 +150,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
154 .init_early = imx1_init_early, 150 .init_early = imx1_init_early,
155 .init_irq = mx1_init_irq, 151 .init_irq = mx1_init_irq,
156 .handle_irq = imx1_handle_irq, 152 .handle_irq = imx1_handle_irq,
157 .timer = &mx1ads_timer, 153 .init_time = mx1ads_timer_init,
158 .init_machine = mx1ads_init, 154 .init_machine = mx1ads_init,
159 .restart = mxc_restart, 155 .restart = mxc_restart,
160MACHINE_END 156MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 6adb3136bb08..a06aa4dc37fc 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -318,10 +318,6 @@ static void __init mx21ads_timer_init(void)
318 mx21_clocks_init(32768, 26000000); 318 mx21_clocks_init(32768, 26000000);
319} 319}
320 320
321static struct sys_timer mx21ads_timer = {
322 .init = mx21ads_timer_init,
323};
324
325MACHINE_START(MX21ADS, "Freescale i.MX21ADS") 321MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
326 /* maintainer: Freescale Semiconductor, Inc. */ 322 /* maintainer: Freescale Semiconductor, Inc. */
327 .atag_offset = 0x100, 323 .atag_offset = 0x100,
@@ -329,7 +325,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
329 .init_early = imx21_init_early, 325 .init_early = imx21_init_early,
330 .init_irq = mx21_init_irq, 326 .init_irq = mx21_init_irq,
331 .handle_irq = imx21_handle_irq, 327 .handle_irq = imx21_handle_irq,
332 .timer = &mx21ads_timer, 328 .init_time = mx21ads_timer_init,
333 .init_machine = mx21ads_board_init, 329 .init_machine = mx21ads_board_init,
334 .restart = mxc_restart, 330 .restart = mxc_restart,
335MACHINE_END 331MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index b1b03aa55bb8..8bcda688a006 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -257,10 +257,6 @@ static void __init mx25pdk_timer_init(void)
257 mx25_clocks_init(); 257 mx25_clocks_init();
258} 258}
259 259
260static struct sys_timer mx25pdk_timer = {
261 .init = mx25pdk_timer_init,
262};
263
264MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") 260MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
265 /* Maintainer: Freescale Semiconductor, Inc. */ 261 /* Maintainer: Freescale Semiconductor, Inc. */
266 .atag_offset = 0x100, 262 .atag_offset = 0x100,
@@ -268,7 +264,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
268 .init_early = imx25_init_early, 264 .init_early = imx25_init_early,
269 .init_irq = mx25_init_irq, 265 .init_irq = mx25_init_irq,
270 .handle_irq = imx25_handle_irq, 266 .handle_irq = imx25_handle_irq,
271 .timer = &mx25pdk_timer, 267 .init_time = mx25pdk_timer_init,
272 .init_machine = mx25pdk_init, 268 .init_machine = mx25pdk_init,
273 .restart = mxc_restart, 269 .restart = mxc_restart,
274MACHINE_END 270MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index d0e547fa925f..25b3e4c9bc0a 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -538,10 +538,6 @@ static void __init mx27pdk_timer_init(void)
538 mx27_clocks_init(26000000); 538 mx27_clocks_init(26000000);
539} 539}
540 540
541static struct sys_timer mx27pdk_timer = {
542 .init = mx27pdk_timer_init,
543};
544
545MACHINE_START(MX27_3DS, "Freescale MX27PDK") 541MACHINE_START(MX27_3DS, "Freescale MX27PDK")
546 /* maintainer: Freescale Semiconductor, Inc. */ 542 /* maintainer: Freescale Semiconductor, Inc. */
547 .atag_offset = 0x100, 543 .atag_offset = 0x100,
@@ -549,7 +545,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
549 .init_early = imx27_init_early, 545 .init_early = imx27_init_early,
550 .init_irq = mx27_init_irq, 546 .init_irq = mx27_init_irq,
551 .handle_irq = imx27_handle_irq, 547 .handle_irq = imx27_handle_irq,
552 .timer = &mx27pdk_timer, 548 .init_time = mx27pdk_timer_init,
553 .init_machine = mx27pdk_init, 549 .init_machine = mx27pdk_init,
554 .restart = mxc_restart, 550 .restart = mxc_restart,
555MACHINE_END 551MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 3d036f57f0e6..9821b824dcaf 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -323,10 +323,6 @@ static void __init mx27ads_timer_init(void)
323 mx27_clocks_init(fref); 323 mx27_clocks_init(fref);
324} 324}
325 325
326static struct sys_timer mx27ads_timer = {
327 .init = mx27ads_timer_init,
328};
329
330static struct map_desc mx27ads_io_desc[] __initdata = { 326static struct map_desc mx27ads_io_desc[] __initdata = {
331 { 327 {
332 .virtual = PBC_BASE_ADDRESS, 328 .virtual = PBC_BASE_ADDRESS,
@@ -349,7 +345,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
349 .init_early = imx27_init_early, 345 .init_early = imx27_init_early,
350 .init_irq = mx27_init_irq, 346 .init_irq = mx27_init_irq,
351 .handle_irq = imx27_handle_irq, 347 .handle_irq = imx27_handle_irq,
352 .timer = &mx27ads_timer, 348 .init_time = mx27ads_timer_init,
353 .init_machine = mx27ads_board_init, 349 .init_machine = mx27ads_board_init,
354 .restart = mxc_restart, 350 .restart = mxc_restart,
355MACHINE_END 351MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index bc301befdd06..1ed916175d41 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -762,10 +762,6 @@ static void __init mx31_3ds_timer_init(void)
762 mx31_clocks_init(26000000); 762 mx31_clocks_init(26000000);
763} 763}
764 764
765static struct sys_timer mx31_3ds_timer = {
766 .init = mx31_3ds_timer_init,
767};
768
769static void __init mx31_3ds_reserve(void) 765static void __init mx31_3ds_reserve(void)
770{ 766{
771 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ 767 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
@@ -780,7 +776,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
780 .init_early = imx31_init_early, 776 .init_early = imx31_init_early,
781 .init_irq = mx31_init_irq, 777 .init_irq = mx31_init_irq,
782 .handle_irq = imx31_handle_irq, 778 .handle_irq = imx31_handle_irq,
783 .timer = &mx31_3ds_timer, 779 .init_time = mx31_3ds_timer_init,
784 .init_machine = mx31_3ds_init, 780 .init_machine = mx31_3ds_init,
785 .reserve = mx31_3ds_reserve, 781 .reserve = mx31_3ds_reserve,
786 .restart = mxc_restart, 782 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 8b56f8883f32..daf8889125cc 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -576,10 +576,6 @@ static void __init mx31ads_timer_init(void)
576 mx31_clocks_init(26000000); 576 mx31_clocks_init(26000000);
577} 577}
578 578
579static struct sys_timer mx31ads_timer = {
580 .init = mx31ads_timer_init,
581};
582
583MACHINE_START(MX31ADS, "Freescale MX31ADS") 579MACHINE_START(MX31ADS, "Freescale MX31ADS")
584 /* Maintainer: Freescale Semiconductor, Inc. */ 580 /* Maintainer: Freescale Semiconductor, Inc. */
585 .atag_offset = 0x100, 581 .atag_offset = 0x100,
@@ -587,7 +583,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
587 .init_early = imx31_init_early, 583 .init_early = imx31_init_early,
588 .init_irq = mx31ads_init_irq, 584 .init_irq = mx31ads_init_irq,
589 .handle_irq = imx31_handle_irq, 585 .handle_irq = imx31_handle_irq,
590 .timer = &mx31ads_timer, 586 .init_time = mx31ads_timer_init,
591 .init_machine = mx31ads_init, 587 .init_machine = mx31ads_init,
592 .restart = mxc_restart, 588 .restart = mxc_restart,
593MACHINE_END 589MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 08b9965c8b36..832b1e2f964e 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -303,17 +303,13 @@ static void __init mx31lilly_timer_init(void)
303 mx31_clocks_init(26000000); 303 mx31_clocks_init(26000000);
304} 304}
305 305
306static struct sys_timer mx31lilly_timer = {
307 .init = mx31lilly_timer_init,
308};
309
310MACHINE_START(LILLY1131, "INCO startec LILLY-1131") 306MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
311 .atag_offset = 0x100, 307 .atag_offset = 0x100,
312 .map_io = mx31_map_io, 308 .map_io = mx31_map_io,
313 .init_early = imx31_init_early, 309 .init_early = imx31_init_early,
314 .init_irq = mx31_init_irq, 310 .init_irq = mx31_init_irq,
315 .handle_irq = imx31_handle_irq, 311 .handle_irq = imx31_handle_irq,
316 .timer = &mx31lilly_timer, 312 .init_time = mx31lilly_timer_init,
317 .init_machine = mx31lilly_board_init, 313 .init_machine = mx31lilly_board_init,
318 .restart = mxc_restart, 314 .restart = mxc_restart,
319MACHINE_END 315MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index bdcd92e59518..bea07299b61a 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -285,10 +285,6 @@ static void __init mx31lite_timer_init(void)
285 mx31_clocks_init(26000000); 285 mx31_clocks_init(26000000);
286} 286}
287 287
288static struct sys_timer mx31lite_timer = {
289 .init = mx31lite_timer_init,
290};
291
292MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") 288MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
293 /* Maintainer: Freescale Semiconductor, Inc. */ 289 /* Maintainer: Freescale Semiconductor, Inc. */
294 .atag_offset = 0x100, 290 .atag_offset = 0x100,
@@ -296,7 +292,7 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
296 .init_early = imx31_init_early, 292 .init_early = imx31_init_early,
297 .init_irq = mx31_init_irq, 293 .init_irq = mx31_init_irq,
298 .handle_irq = imx31_handle_irq, 294 .handle_irq = imx31_handle_irq,
299 .timer = &mx31lite_timer, 295 .init_time = mx31lite_timer_init,
300 .init_machine = mx31lite_init, 296 .init_machine = mx31lite_init,
301 .restart = mxc_restart, 297 .restart = mxc_restart,
302MACHINE_END 298MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 2517cfa9f26b..dae4cd7be040 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -596,10 +596,6 @@ static void __init mx31moboard_timer_init(void)
596 mx31_clocks_init(26000000); 596 mx31_clocks_init(26000000);
597} 597}
598 598
599static struct sys_timer mx31moboard_timer = {
600 .init = mx31moboard_timer_init,
601};
602
603static void __init mx31moboard_reserve(void) 599static void __init mx31moboard_reserve(void)
604{ 600{
605 /* reserve 4 MiB for mx3-camera */ 601 /* reserve 4 MiB for mx3-camera */
@@ -615,7 +611,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
615 .init_early = imx31_init_early, 611 .init_early = imx31_init_early,
616 .init_irq = mx31_init_irq, 612 .init_irq = mx31_init_irq,
617 .handle_irq = imx31_handle_irq, 613 .handle_irq = imx31_handle_irq,
618 .timer = &mx31moboard_timer, 614 .init_time = mx31moboard_timer_init,
619 .init_machine = mx31moboard_init, 615 .init_machine = mx31moboard_init,
620 .restart = mxc_restart, 616 .restart = mxc_restart,
621MACHINE_END 617MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 5277da45d60c..a42f4f07051f 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -602,10 +602,6 @@ static void __init mx35pdk_timer_init(void)
602 mx35_clocks_init(); 602 mx35_clocks_init();
603} 603}
604 604
605static struct sys_timer mx35pdk_timer = {
606 .init = mx35pdk_timer_init,
607};
608
609static void __init mx35_3ds_reserve(void) 605static void __init mx35_3ds_reserve(void)
610{ 606{
611 /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ 607 /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
@@ -620,7 +616,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
620 .init_early = imx35_init_early, 616 .init_early = imx35_init_early,
621 .init_irq = mx35_init_irq, 617 .init_irq = mx35_init_irq,
622 .handle_irq = imx35_handle_irq, 618 .handle_irq = imx35_handle_irq,
623 .timer = &mx35pdk_timer, 619 .init_time = mx35pdk_timer_init,
624 .init_machine = mx35_3ds_init, 620 .init_machine = mx35_3ds_init,
625 .reserve = mx35_3ds_reserve, 621 .reserve = mx35_3ds_reserve,
626 .restart = mxc_restart, 622 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c
deleted file mode 100644
index 0c1f88a80bdc..000000000000
--- a/arch/arm/mach-imx/mach-mx50_rdp.c
+++ /dev/null
@@ -1,225 +0,0 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25#include <linux/io.h>
26
27#include <asm/irq.h>
28#include <asm/setup.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/time.h>
32
33#include "common.h"
34#include "devices-imx50.h"
35#include "hardware.h"
36#include "iomux-mx50.h"
37
38#define FEC_EN IMX_GPIO_NR(6, 23)
39#define FEC_RESET_B IMX_GPIO_NR(4, 12)
40
41static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
42 /* SD1 */
43 MX50_PAD_ECSPI2_SS0__GPIO_4_19,
44 MX50_PAD_EIM_CRE__GPIO_1_27,
45 MX50_PAD_SD1_CMD__SD1_CMD,
46
47 MX50_PAD_SD1_CLK__SD1_CLK,
48 MX50_PAD_SD1_D0__SD1_D0,
49 MX50_PAD_SD1_D1__SD1_D1,
50 MX50_PAD_SD1_D2__SD1_D2,
51 MX50_PAD_SD1_D3__SD1_D3,
52
53 /* SD2 */
54 MX50_PAD_SD2_CD__GPIO_5_17,
55 MX50_PAD_SD2_WP__GPIO_5_16,
56 MX50_PAD_SD2_CMD__SD2_CMD,
57 MX50_PAD_SD2_CLK__SD2_CLK,
58 MX50_PAD_SD2_D0__SD2_D0,
59 MX50_PAD_SD2_D1__SD2_D1,
60 MX50_PAD_SD2_D2__SD2_D2,
61 MX50_PAD_SD2_D3__SD2_D3,
62 MX50_PAD_SD2_D4__SD2_D4,
63 MX50_PAD_SD2_D5__SD2_D5,
64 MX50_PAD_SD2_D6__SD2_D6,
65 MX50_PAD_SD2_D7__SD2_D7,
66
67 /* SD3 */
68 MX50_PAD_SD3_CMD__SD3_CMD,
69 MX50_PAD_SD3_CLK__SD3_CLK,
70 MX50_PAD_SD3_D0__SD3_D0,
71 MX50_PAD_SD3_D1__SD3_D1,
72 MX50_PAD_SD3_D2__SD3_D2,
73 MX50_PAD_SD3_D3__SD3_D3,
74 MX50_PAD_SD3_D4__SD3_D4,
75 MX50_PAD_SD3_D5__SD3_D5,
76 MX50_PAD_SD3_D6__SD3_D6,
77 MX50_PAD_SD3_D7__SD3_D7,
78
79 /* PWR_INT */
80 MX50_PAD_ECSPI2_MISO__GPIO_4_18,
81
82 /* UART pad setting */
83 MX50_PAD_UART1_TXD__UART1_TXD,
84 MX50_PAD_UART1_RXD__UART1_RXD,
85 MX50_PAD_UART1_RTS__UART1_RTS,
86 MX50_PAD_UART2_TXD__UART2_TXD,
87 MX50_PAD_UART2_RXD__UART2_RXD,
88 MX50_PAD_UART2_CTS__UART2_CTS,
89 MX50_PAD_UART2_RTS__UART2_RTS,
90
91 MX50_PAD_I2C1_SCL__I2C1_SCL,
92 MX50_PAD_I2C1_SDA__I2C1_SDA,
93 MX50_PAD_I2C2_SCL__I2C2_SCL,
94 MX50_PAD_I2C2_SDA__I2C2_SDA,
95
96 MX50_PAD_EPITO__USBH1_PWR,
97 /* Need to comment below line if
98 * one needs to debug owire.
99 */
100 MX50_PAD_OWIRE__USBH1_OC,
101 /* using gpio to control otg pwr */
102 MX50_PAD_PWM2__GPIO_6_25,
103 MX50_PAD_I2C3_SCL__USBOTG_OC,
104
105 MX50_PAD_SSI_RXC__FEC_MDIO,
106 MX50_PAD_SSI_RXFS__FEC_MDC,
107 MX50_PAD_DISP_D0__FEC_TXCLK,
108 MX50_PAD_DISP_D1__FEC_RX_ER,
109 MX50_PAD_DISP_D2__FEC_RX_DV,
110 MX50_PAD_DISP_D3__FEC_RXD1,
111 MX50_PAD_DISP_D4__FEC_RXD0,
112 MX50_PAD_DISP_D5__FEC_TX_EN,
113 MX50_PAD_DISP_D6__FEC_TXD1,
114 MX50_PAD_DISP_D7__FEC_TXD0,
115 MX50_PAD_I2C3_SDA__GPIO_6_23,
116 MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
117
118 MX50_PAD_CSPI_SS0__CSPI_SS0,
119 MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
120 MX50_PAD_CSPI_MOSI__CSPI_MOSI,
121 MX50_PAD_CSPI_MISO__CSPI_MISO,
122
123 /* SGTL500_OSC_EN */
124 MX50_PAD_UART1_CTS__GPIO_6_8,
125
126 /* SGTL_AMP_SHDN */
127 MX50_PAD_UART3_RXD__GPIO_6_15,
128
129 /* Keypad */
130 MX50_PAD_KEY_COL0__KEY_COL0,
131 MX50_PAD_KEY_ROW0__KEY_ROW0,
132 MX50_PAD_KEY_COL1__KEY_COL1,
133 MX50_PAD_KEY_ROW1__KEY_ROW1,
134 MX50_PAD_KEY_COL2__KEY_COL2,
135 MX50_PAD_KEY_ROW2__KEY_ROW2,
136 MX50_PAD_KEY_COL3__KEY_COL3,
137 MX50_PAD_KEY_ROW3__KEY_ROW3,
138 MX50_PAD_EIM_DA0__KEY_COL4,
139 MX50_PAD_EIM_DA1__KEY_ROW4,
140 MX50_PAD_EIM_DA2__KEY_COL5,
141 MX50_PAD_EIM_DA3__KEY_ROW5,
142 MX50_PAD_EIM_DA4__KEY_COL6,
143 MX50_PAD_EIM_DA5__KEY_ROW6,
144 MX50_PAD_EIM_DA6__KEY_COL7,
145 MX50_PAD_EIM_DA7__KEY_ROW7,
146 /*EIM pads */
147 MX50_PAD_EIM_DA8__GPIO_1_8,
148 MX50_PAD_EIM_DA9__GPIO_1_9,
149 MX50_PAD_EIM_DA10__GPIO_1_10,
150 MX50_PAD_EIM_DA11__GPIO_1_11,
151 MX50_PAD_EIM_DA12__GPIO_1_12,
152 MX50_PAD_EIM_DA13__GPIO_1_13,
153 MX50_PAD_EIM_DA14__GPIO_1_14,
154 MX50_PAD_EIM_DA15__GPIO_1_15,
155 MX50_PAD_EIM_CS2__GPIO_1_16,
156 MX50_PAD_EIM_CS1__GPIO_1_17,
157 MX50_PAD_EIM_CS0__GPIO_1_18,
158 MX50_PAD_EIM_EB0__GPIO_1_19,
159 MX50_PAD_EIM_EB1__GPIO_1_20,
160 MX50_PAD_EIM_WAIT__GPIO_1_21,
161 MX50_PAD_EIM_BCLK__GPIO_1_22,
162 MX50_PAD_EIM_RDY__GPIO_1_23,
163 MX50_PAD_EIM_OE__GPIO_1_24,
164};
165
166/* Serial ports */
167static const struct imxuart_platform_data uart_pdata __initconst = {
168 .flags = IMXUART_HAVE_RTSCTS,
169};
170
171static const struct fec_platform_data fec_data __initconst = {
172 .phy = PHY_INTERFACE_MODE_RMII,
173};
174
175static inline void mx50_rdp_fec_reset(void)
176{
177 gpio_request(FEC_EN, "fec-en");
178 gpio_direction_output(FEC_EN, 0);
179 gpio_request(FEC_RESET_B, "fec-reset_b");
180 gpio_direction_output(FEC_RESET_B, 0);
181 msleep(1);
182 gpio_set_value(FEC_RESET_B, 1);
183}
184
185static const struct imxi2c_platform_data i2c_data __initconst = {
186 .bitrate = 100000,
187};
188
189/*
190 * Board specific initialization.
191 */
192static void __init mx50_rdp_board_init(void)
193{
194 imx50_soc_init();
195
196 mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
197 ARRAY_SIZE(mx50_rdp_pads));
198
199 imx50_add_imx_uart(0, &uart_pdata);
200 imx50_add_imx_uart(1, &uart_pdata);
201 mx50_rdp_fec_reset();
202 imx50_add_fec(&fec_data);
203 imx50_add_imx_i2c(0, &i2c_data);
204 imx50_add_imx_i2c(1, &i2c_data);
205 imx50_add_imx_i2c(2, &i2c_data);
206}
207
208static void __init mx50_rdp_timer_init(void)
209{
210 mx50_clocks_init(32768, 24000000, 22579200);
211}
212
213static struct sys_timer mx50_rdp_timer = {
214 .init = mx50_rdp_timer_init,
215};
216
217MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
218 .map_io = mx50_map_io,
219 .init_early = imx50_init_early,
220 .init_irq = mx50_init_irq,
221 .handle_irq = imx50_handle_irq,
222 .timer = &mx50_rdp_timer,
223 .init_machine = mx50_rdp_board_init,
224 .restart = mxc_restart,
225MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
deleted file mode 100644
index abc25bd1107b..000000000000
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ /dev/null
@@ -1,178 +0,0 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/irq.h>
14#include <linux/platform_device.h>
15#include <linux/spi/spi.h>
16#include <linux/gpio.h>
17
18#include <asm/mach-types.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/time.h>
21
22#include "3ds_debugboard.h"
23#include "common.h"
24#include "devices-imx51.h"
25#include "hardware.h"
26#include "iomux-mx51.h"
27
28#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
29
30static iomux_v3_cfg_t mx51_3ds_pads[] = {
31 /* UART1 */
32 MX51_PAD_UART1_RXD__UART1_RXD,
33 MX51_PAD_UART1_TXD__UART1_TXD,
34 MX51_PAD_UART1_RTS__UART1_RTS,
35 MX51_PAD_UART1_CTS__UART1_CTS,
36
37 /* UART2 */
38 MX51_PAD_UART2_RXD__UART2_RXD,
39 MX51_PAD_UART2_TXD__UART2_TXD,
40 MX51_PAD_EIM_D25__UART2_CTS,
41 MX51_PAD_EIM_D26__UART2_RTS,
42
43 /* UART3 */
44 MX51_PAD_UART3_RXD__UART3_RXD,
45 MX51_PAD_UART3_TXD__UART3_TXD,
46 MX51_PAD_EIM_D24__UART3_CTS,
47 MX51_PAD_EIM_D27__UART3_RTS,
48
49 /* CPLD PARENT IRQ PIN */
50 MX51_PAD_GPIO1_6__GPIO1_6,
51
52 /* KPP */
53 MX51_PAD_KEY_ROW0__KEY_ROW0,
54 MX51_PAD_KEY_ROW1__KEY_ROW1,
55 MX51_PAD_KEY_ROW2__KEY_ROW2,
56 MX51_PAD_KEY_ROW3__KEY_ROW3,
57 MX51_PAD_KEY_COL0__KEY_COL0,
58 MX51_PAD_KEY_COL1__KEY_COL1,
59 MX51_PAD_KEY_COL2__KEY_COL2,
60 MX51_PAD_KEY_COL3__KEY_COL3,
61 MX51_PAD_KEY_COL4__KEY_COL4,
62 MX51_PAD_KEY_COL5__KEY_COL5,
63
64 /* eCSPI2 */
65 MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
66 MX51_PAD_NANDF_RB3__ECSPI2_MISO,
67 MX51_PAD_NANDF_D15__ECSPI2_MOSI,
68 MX51_PAD_NANDF_D12__GPIO3_28,
69};
70
71/* Serial ports */
72static const struct imxuart_platform_data uart_pdata __initconst = {
73 .flags = IMXUART_HAVE_RTSCTS,
74};
75
76static int mx51_3ds_board_keymap[] = {
77 KEY(0, 0, KEY_1),
78 KEY(0, 1, KEY_2),
79 KEY(0, 2, KEY_3),
80 KEY(0, 3, KEY_F1),
81 KEY(0, 4, KEY_UP),
82 KEY(0, 5, KEY_F2),
83
84 KEY(1, 0, KEY_4),
85 KEY(1, 1, KEY_5),
86 KEY(1, 2, KEY_6),
87 KEY(1, 3, KEY_LEFT),
88 KEY(1, 4, KEY_SELECT),
89 KEY(1, 5, KEY_RIGHT),
90
91 KEY(2, 0, KEY_7),
92 KEY(2, 1, KEY_8),
93 KEY(2, 2, KEY_9),
94 KEY(2, 3, KEY_F3),
95 KEY(2, 4, KEY_DOWN),
96 KEY(2, 5, KEY_F4),
97
98 KEY(3, 0, KEY_0),
99 KEY(3, 1, KEY_OK),
100 KEY(3, 2, KEY_ESC),
101 KEY(3, 3, KEY_ENTER),
102 KEY(3, 4, KEY_MENU),
103 KEY(3, 5, KEY_BACK)
104};
105
106static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
107 .keymap = mx51_3ds_board_keymap,
108 .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap),
109};
110
111static int mx51_3ds_spi2_cs[] = {
112 MXC_SPI_CS(0),
113 MX51_3DS_ECSPI2_CS,
114};
115
116static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
117 .chipselect = mx51_3ds_spi2_cs,
118 .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
119};
120
121static struct spi_board_info mx51_3ds_spi_nor_device[] = {
122 {
123 .modalias = "m25p80",
124 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
125 .bus_num = 1,
126 .chip_select = 1,
127 .mode = SPI_MODE_0,
128 .platform_data = NULL,},
129};
130
131/*
132 * Board specific initialization.
133 */
134static void __init mx51_3ds_init(void)
135{
136 imx51_soc_init();
137
138 mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
139 ARRAY_SIZE(mx51_3ds_pads));
140
141 imx51_add_imx_uart(0, &uart_pdata);
142 imx51_add_imx_uart(1, &uart_pdata);
143 imx51_add_imx_uart(2, &uart_pdata);
144
145 imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
146 spi_register_board_info(mx51_3ds_spi_nor_device,
147 ARRAY_SIZE(mx51_3ds_spi_nor_device));
148
149 if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6)))
150 printk(KERN_WARNING "Init of the debugboard failed, all "
151 "devices on the board are unusable.\n");
152
153 imx51_add_sdhci_esdhc_imx(0, NULL);
154 imx51_add_imx_keypad(&mx51_3ds_map_data);
155 imx51_add_imx2_wdt(0);
156}
157
158static void __init mx51_3ds_timer_init(void)
159{
160 mx51_clocks_init(32768, 24000000, 22579200, 0);
161}
162
163static struct sys_timer mx51_3ds_timer = {
164 .init = mx51_3ds_timer_init,
165};
166
167MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
168 /* Maintainer: Freescale Semiconductor, Inc. */
169 .atag_offset = 0x100,
170 .map_io = mx51_map_io,
171 .init_early = imx51_init_early,
172 .init_irq = mx51_init_irq,
173 .handle_irq = imx51_handle_irq,
174 .timer = &mx51_3ds_timer,
175 .init_machine = mx51_3ds_init,
176 .init_late = imx51_init_late,
177 .restart = mxc_restart,
178MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index d9a84ca2199a..6c4d7feb4520 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -418,10 +418,6 @@ static void __init mx51_babbage_timer_init(void)
418 mx51_clocks_init(32768, 24000000, 22579200, 0); 418 mx51_clocks_init(32768, 24000000, 22579200, 0);
419} 419}
420 420
421static struct sys_timer mx51_babbage_timer = {
422 .init = mx51_babbage_timer_init,
423};
424
425MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") 421MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
426 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */ 422 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
427 .atag_offset = 0x100, 423 .atag_offset = 0x100,
@@ -429,7 +425,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
429 .init_early = imx51_init_early, 425 .init_early = imx51_init_early,
430 .init_irq = mx51_init_irq, 426 .init_irq = mx51_init_irq,
431 .handle_irq = imx51_handle_irq, 427 .handle_irq = imx51_handle_irq,
432 .timer = &mx51_babbage_timer, 428 .init_time = mx51_babbage_timer_init,
433 .init_machine = mx51_babbage_init, 429 .init_machine = mx51_babbage_init,
434 .init_late = imx51_init_late, 430 .init_late = imx51_init_late,
435 .restart = mxc_restart, 431 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index f4a8c7e108e1..a27faaba98ec 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -261,10 +261,6 @@ static void __init mxt_td60_timer_init(void)
261 mx27_clocks_init(26000000); 261 mx27_clocks_init(26000000);
262} 262}
263 263
264static struct sys_timer mxt_td60_timer = {
265 .init = mxt_td60_timer_init,
266};
267
268MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") 264MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
269 /* maintainer: Maxtrack Industrial */ 265 /* maintainer: Maxtrack Industrial */
270 .atag_offset = 0x100, 266 .atag_offset = 0x100,
@@ -272,7 +268,7 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
272 .init_early = imx27_init_early, 268 .init_early = imx27_init_early,
273 .init_irq = mx27_init_irq, 269 .init_irq = mx27_init_irq,
274 .handle_irq = imx27_handle_irq, 270 .handle_irq = imx27_handle_irq,
275 .timer = &mxt_td60_timer, 271 .init_time = mxt_td60_timer_init,
276 .init_machine = mxt_td60_board_init, 272 .init_machine = mxt_td60_board_init,
277 .restart = mxc_restart, 273 .restart = mxc_restart,
278MACHINE_END 274MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index eee369fa94a2..b8b15bb1ffdf 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -416,10 +416,6 @@ static void __init pca100_timer_init(void)
416 mx27_clocks_init(26000000); 416 mx27_clocks_init(26000000);
417} 417}
418 418
419static struct sys_timer pca100_timer = {
420 .init = pca100_timer_init,
421};
422
423MACHINE_START(PCA100, "phyCARD-i.MX27") 419MACHINE_START(PCA100, "phyCARD-i.MX27")
424 .atag_offset = 0x100, 420 .atag_offset = 0x100,
425 .map_io = mx27_map_io, 421 .map_io = mx27_map_io,
@@ -427,6 +423,6 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
427 .init_irq = mx27_init_irq, 423 .init_irq = mx27_init_irq,
428 .handle_irq = imx27_handle_irq, 424 .handle_irq = imx27_handle_irq,
429 .init_machine = pca100_init, 425 .init_machine = pca100_init,
430 .timer = &pca100_timer, 426 .init_time = pca100_timer_init,
431 .restart = mxc_restart, 427 .restart = mxc_restart,
432MACHINE_END 428MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 547fef133f65..bc0261e99d39 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -685,10 +685,6 @@ static void __init pcm037_timer_init(void)
685 mx31_clocks_init(26000000); 685 mx31_clocks_init(26000000);
686} 686}
687 687
688static struct sys_timer pcm037_timer = {
689 .init = pcm037_timer_init,
690};
691
692static void __init pcm037_reserve(void) 688static void __init pcm037_reserve(void)
693{ 689{
694 /* reserve 4 MiB for mx3-camera */ 690 /* reserve 4 MiB for mx3-camera */
@@ -709,7 +705,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
709 .init_early = imx31_init_early, 705 .init_early = imx31_init_early,
710 .init_irq = mx31_init_irq, 706 .init_irq = mx31_init_irq,
711 .handle_irq = imx31_handle_irq, 707 .handle_irq = imx31_handle_irq,
712 .timer = &pcm037_timer, 708 .init_time = pcm037_timer_init,
713 .init_machine = pcm037_init, 709 .init_machine = pcm037_init,
714 .init_late = pcm037_init_late, 710 .init_late = pcm037_init_late,
715 .restart = mxc_restart, 711 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 4aa0d0798605..e805ac273e9c 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -346,17 +346,13 @@ static void __init pcm038_timer_init(void)
346 mx27_clocks_init(26000000); 346 mx27_clocks_init(26000000);
347} 347}
348 348
349static struct sys_timer pcm038_timer = {
350 .init = pcm038_timer_init,
351};
352
353MACHINE_START(PCM038, "phyCORE-i.MX27") 349MACHINE_START(PCM038, "phyCORE-i.MX27")
354 .atag_offset = 0x100, 350 .atag_offset = 0x100,
355 .map_io = mx27_map_io, 351 .map_io = mx27_map_io,
356 .init_early = imx27_init_early, 352 .init_early = imx27_init_early,
357 .init_irq = mx27_init_irq, 353 .init_irq = mx27_init_irq,
358 .handle_irq = imx27_handle_irq, 354 .handle_irq = imx27_handle_irq,
359 .timer = &pcm038_timer, 355 .init_time = pcm038_timer_init,
360 .init_machine = pcm038_init, 356 .init_machine = pcm038_init,
361 .restart = mxc_restart, 357 .restart = mxc_restart,
362MACHINE_END 358MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 92445440221e..8ed533f0f8ca 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -394,10 +394,6 @@ static void __init pcm043_timer_init(void)
394 mx35_clocks_init(); 394 mx35_clocks_init();
395} 395}
396 396
397static struct sys_timer pcm043_timer = {
398 .init = pcm043_timer_init,
399};
400
401MACHINE_START(PCM043, "Phytec Phycore pcm043") 397MACHINE_START(PCM043, "Phytec Phycore pcm043")
402 /* Maintainer: Pengutronix */ 398 /* Maintainer: Pengutronix */
403 .atag_offset = 0x100, 399 .atag_offset = 0x100,
@@ -405,7 +401,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
405 .init_early = imx35_init_early, 401 .init_early = imx35_init_early,
406 .init_irq = mx35_init_irq, 402 .init_irq = mx35_init_irq,
407 .handle_irq = imx35_handle_irq, 403 .handle_irq = imx35_handle_irq,
408 .timer = &pcm043_timer, 404 .init_time = pcm043_timer_init,
409 .init_machine = pcm043_init, 405 .init_machine = pcm043_init,
410 .restart = mxc_restart, 406 .restart = mxc_restart,
411MACHINE_END 407MACHINE_END
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 96d9a91f8a3b..22af27ed457e 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -260,10 +260,6 @@ static void __init qong_timer_init(void)
260 mx31_clocks_init(26000000); 260 mx31_clocks_init(26000000);
261} 261}
262 262
263static struct sys_timer qong_timer = {
264 .init = qong_timer_init,
265};
266
267MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") 263MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
268 /* Maintainer: DENX Software Engineering GmbH */ 264 /* Maintainer: DENX Software Engineering GmbH */
269 .atag_offset = 0x100, 265 .atag_offset = 0x100,
@@ -271,7 +267,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
271 .init_early = imx31_init_early, 267 .init_early = imx31_init_early,
272 .init_irq = mx31_init_irq, 268 .init_irq = mx31_init_irq,
273 .handle_irq = imx31_handle_irq, 269 .handle_irq = imx31_handle_irq,
274 .timer = &qong_timer, 270 .init_time = qong_timer_init,
275 .init_machine = qong_init, 271 .init_machine = qong_init,
276 .restart = mxc_restart, 272 .restart = mxc_restart,
277MACHINE_END 273MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index fc970409dbaf..b0fa10dd79fe 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -131,10 +131,6 @@ static void __init scb9328_timer_init(void)
131 mx1_clocks_init(32000); 131 mx1_clocks_init(32000);
132} 132}
133 133
134static struct sys_timer scb9328_timer = {
135 .init = scb9328_timer_init,
136};
137
138MACHINE_START(SCB9328, "Synertronixx scb9328") 134MACHINE_START(SCB9328, "Synertronixx scb9328")
139 /* Sascha Hauer */ 135 /* Sascha Hauer */
140 .atag_offset = 100, 136 .atag_offset = 100,
@@ -142,7 +138,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
142 .init_early = imx1_init_early, 138 .init_early = imx1_init_early,
143 .init_irq = mx1_init_irq, 139 .init_irq = mx1_init_irq,
144 .handle_irq = imx1_handle_irq, 140 .handle_irq = imx1_handle_irq,
145 .timer = &scb9328_timer, 141 .init_time = scb9328_timer_init,
146 .init_machine = scb9328_init, 142 .init_machine = scb9328_init,
147 .restart = mxc_restart, 143 .restart = mxc_restart,
148MACHINE_END 144MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 3aecf91e4289..0910761e8280 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -305,17 +305,13 @@ static void __init vpr200_timer_init(void)
305 mx35_clocks_init(); 305 mx35_clocks_init();
306} 306}
307 307
308static struct sys_timer vpr200_timer = {
309 .init = vpr200_timer_init,
310};
311
312MACHINE_START(VPR200, "VPR200") 308MACHINE_START(VPR200, "VPR200")
313 /* Maintainer: Creative Product Design */ 309 /* Maintainer: Creative Product Design */
314 .map_io = mx35_map_io, 310 .map_io = mx35_map_io,
315 .init_early = imx35_init_early, 311 .init_early = imx35_init_early,
316 .init_irq = mx35_init_irq, 312 .init_irq = mx35_init_irq,
317 .handle_irq = imx35_handle_irq, 313 .handle_irq = imx35_handle_irq,
318 .timer = &vpr200_timer, 314 .init_time = vpr200_timer_init,
319 .init_machine = vpr200_board_init, 315 .init_machine = vpr200_board_init,
320 .restart = mxc_restart, 316 .restart = mxc_restart,
321MACHINE_END 317MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 79d71cf23a1d..cf34994cfe28 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -24,16 +24,6 @@
24#include "iomux-v3.h" 24#include "iomux-v3.h"
25 25
26/* 26/*
27 * Define the MX50 memory map.
28 */
29static struct map_desc mx50_io_desc[] __initdata = {
30 imx_map_entry(MX50, TZIC, MT_DEVICE),
31 imx_map_entry(MX50, SPBA0, MT_DEVICE),
32 imx_map_entry(MX50, AIPS1, MT_DEVICE),
33 imx_map_entry(MX50, AIPS2, MT_DEVICE),
34};
35
36/*
37 * Define the MX51 memory map. 27 * Define the MX51 memory map.
38 */ 28 */
39static struct map_desc mx51_io_desc[] __initdata = { 29static struct map_desc mx51_io_desc[] __initdata = {
@@ -59,11 +49,6 @@ static struct map_desc mx53_io_desc[] __initdata = {
59 * system startup to create static physical to virtual memory mappings 49 * system startup to create static physical to virtual memory mappings
60 * for the IO modules. 50 * for the IO modules.
61 */ 51 */
62void __init mx50_map_io(void)
63{
64 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
65}
66
67void __init mx51_map_io(void) 52void __init mx51_map_io(void)
68{ 53{
69 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); 54 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
@@ -74,13 +59,6 @@ void __init mx53_map_io(void)
74 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); 59 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
75} 60}
76 61
77void __init imx50_init_early(void)
78{
79 mxc_set_cpu_type(MXC_CPU_MX50);
80 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
81 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
82}
83
84/* 62/*
85 * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by 63 * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
86 * the Freescale marketing division. However this did not remove the 64 * the Freescale marketing division. However this did not remove the
@@ -115,11 +93,6 @@ void __init imx53_init_early(void)
115 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); 93 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
116} 94}
117 95
118void __init mx50_init_irq(void)
119{
120 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
121}
122
123void __init mx51_init_irq(void) 96void __init mx51_init_irq(void)
124{ 97{
125 tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); 98 tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
@@ -148,31 +121,10 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
148 .script_addrs = &imx51_sdma_script, 121 .script_addrs = &imx51_sdma_script,
149}; 122};
150 123
151static const struct resource imx50_audmux_res[] __initconst = {
152 DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
153};
154
155static const struct resource imx51_audmux_res[] __initconst = { 124static const struct resource imx51_audmux_res[] __initconst = {
156 DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), 125 DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
157}; 126};
158 127
159void __init imx50_soc_init(void)
160{
161 mxc_device_init();
162
163 /* i.mx50 has the i.mx35 type gpio */
164 mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
165 mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
166 mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
167 mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
168 mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
169 mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
170
171 /* i.mx50 has the i.mx31 type audmux */
172 platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
173 ARRAY_SIZE(imx50_audmux_res));
174}
175
176void __init imx51_soc_init(void) 128void __init imx51_soc_init(void)
177{ 129{
178 mxc_device_init(); 130 mxc_device_init();
diff --git a/arch/arm/mach-imx/mx50.h b/arch/arm/mach-imx/mx50.h
deleted file mode 100644
index 09ac19c1570c..000000000000
--- a/arch/arm/mach-imx/mx50.h
+++ /dev/null
@@ -1,290 +0,0 @@
1#ifndef __MACH_MX50_H__
2#define __MACH_MX50_H__
3
4/*
5 * IROM
6 */
7#define MX50_IROM_BASE_ADDR 0x0
8#define MX50_IROM_SIZE SZ_64K
9
10/* TZIC */
11#define MX50_TZIC_BASE_ADDR 0x0fffc000
12#define MX50_TZIC_SIZE SZ_16K
13
14/*
15 * IRAM
16 */
17#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
18#define MX50_IRAM_PARTITIONS 16
19#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
20
21/*
22 * Databahn
23 */
24#define MX50_DATABAHN_BASE_ADDR 0x14000000
25
26/*
27 * Graphics Memory of GPU
28 */
29#define MX50_GPU2D_BASE_ADDR 0x20000000
30
31#define MX50_DEBUG_BASE_ADDR 0x40000000
32#define MX50_DEBUG_SIZE SZ_1M
33#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
34#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
35#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
36#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
37#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
38#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
39#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
40#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
41
42#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
43#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
44#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
45#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
46#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
47#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
48#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
49#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
50#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
51#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
52#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
53#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
54#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
55#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
56
57/*
58 * SPBA global module enabled #0
59 */
60#define MX50_SPBA0_BASE_ADDR 0x50000000
61#define MX50_SPBA0_SIZE SZ_1M
62
63#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
64#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
65#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
66#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
67#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
68#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
69#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
70
71/*
72 * AIPS 1
73 */
74#define MX50_AIPS1_BASE_ADDR 0x53f00000
75#define MX50_AIPS1_SIZE SZ_1M
76
77#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
78#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
79#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
80#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
81#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
82#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
83#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
84#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
85#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
86#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
87#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
88#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
89#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
90#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
91#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
92#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
93#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
94#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
95#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
96#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
97#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
98#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
99
100#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
101#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
102
103/*
104 * AIPS 2
105 */
106#define MX50_AIPS2_BASE_ADDR 0x63f00000
107#define MX50_AIPS2_SIZE SZ_1M
108
109#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
110#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
111#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
112#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
113#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
114#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
115#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
116#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
117#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
118#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
119#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
120#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
121#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
122#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
123#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
124#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
125#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
126
127/*
128 * Memory regions and CS
129 */
130#define MX50_CSD0_BASE_ADDR 0x70000000
131#define MX50_CSD1_BASE_ADDR 0xb0000000
132#define MX50_CS0_BASE_ADDR 0xf0000000
133
134#define MX50_IO_P2V(x) IMX_IO_P2V(x)
135#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
136
137/*
138 * defines for SPBA modules
139 */
140#define MX50_SPBA_SDHC1 0x04
141#define MX50_SPBA_SDHC2 0x08
142#define MX50_SPBA_UART3 0x0c
143#define MX50_SPBA_CSPI1 0x10
144#define MX50_SPBA_SSI2 0x14
145#define MX50_SPBA_SDHC3 0x20
146#define MX50_SPBA_SDHC4 0x24
147#define MX50_SPBA_SPDIF 0x28
148#define MX50_SPBA_ATA 0x30
149#define MX50_SPBA_SLIM 0x34
150#define MX50_SPBA_HSI2C 0x38
151#define MX50_SPBA_CTRL 0x3c
152
153/*
154 * DMA request assignments
155 */
156#define MX50_DMA_REQ_GPC 1
157#define MX50_DMA_REQ_ATA_UART4_RX 2
158#define MX50_DMA_REQ_ATA_UART4_TX 3
159#define MX50_DMA_REQ_CSPI1_RX 6
160#define MX50_DMA_REQ_CSPI1_TX 7
161#define MX50_DMA_REQ_CSPI2_RX 8
162#define MX50_DMA_REQ_CSPI2_TX 9
163#define MX50_DMA_REQ_I2C3_SDHC3 10
164#define MX50_DMA_REQ_SDHC4 11
165#define MX50_DMA_REQ_UART2_FIRI_RX 12
166#define MX50_DMA_REQ_UART2_FIRI_TX 13
167#define MX50_DMA_REQ_EXT0 14
168#define MX50_DMA_REQ_EXT1 15
169#define MX50_DMA_REQ_UART5_RX 16
170#define MX50_DMA_REQ_UART5_TX 17
171#define MX50_DMA_REQ_UART1_RX 18
172#define MX50_DMA_REQ_UART1_TX 19
173#define MX50_DMA_REQ_I2C1_SDHC1 20
174#define MX50_DMA_REQ_I2C2_SDHC2 21
175#define MX50_DMA_REQ_SSI2_RX2 22
176#define MX50_DMA_REQ_SSI2_TX2 23
177#define MX50_DMA_REQ_SSI2_RX1 24
178#define MX50_DMA_REQ_SSI2_TX1 25
179#define MX50_DMA_REQ_SSI1_RX2 26
180#define MX50_DMA_REQ_SSI1_TX2 27
181#define MX50_DMA_REQ_SSI1_RX1 28
182#define MX50_DMA_REQ_SSI1_TX1 29
183#define MX50_DMA_REQ_CSPI_RX 38
184#define MX50_DMA_REQ_CSPI_TX 39
185#define MX50_DMA_REQ_UART3_RX 42
186#define MX50_DMA_REQ_UART3_TX 43
187
188/*
189 * Interrupt numbers
190 */
191#include <asm/irq.h>
192#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
193#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
194#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
195#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
196#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
197#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
198#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
199#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
200#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
201#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
202#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
203#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
204#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
205#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
206#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
207#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
208#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
209#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
210#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
211#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
212#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
213#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
214#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
215#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
216#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
217#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
218#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
219#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
220#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
221#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
222#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
223#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
224#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
225#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
226#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
227#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
228#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
229#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
230#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
231#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
232#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
233#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
234#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
235#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
236#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
237#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
238#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
239#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
240#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
241#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
242#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
243#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
244#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
245#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
246#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
247#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
248#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
249#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
250#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
251#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
252#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
253#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
254#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
255#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
256#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
257#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
258#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
259#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
260#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
261#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
262#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
263#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
264#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
265#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
266#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
267#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
268#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
269#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
270#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
271#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
272#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
273#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
274#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
275#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
276#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
277#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
278#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
279#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
280#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
281#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
282#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
283#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
284#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
285
286#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
287extern int mx50_revision(void);
288#endif
289
290#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index d78298366a91..7dce17a9fe6c 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -32,7 +32,6 @@
32#define MXC_CPU_MX27 27 32#define MXC_CPU_MX27 27
33#define MXC_CPU_MX31 31 33#define MXC_CPU_MX31 31
34#define MXC_CPU_MX35 35 34#define MXC_CPU_MX35 35
35#define MXC_CPU_MX50 50
36#define MXC_CPU_MX51 51 35#define MXC_CPU_MX51 51
37#define MXC_CPU_MX53 53 36#define MXC_CPU_MX53 53
38 37
@@ -126,18 +125,6 @@ extern unsigned int __mxc_cpu_type;
126# define cpu_is_mx35() (0) 125# define cpu_is_mx35() (0)
127#endif 126#endif
128 127
129#ifdef CONFIG_SOC_IMX50
130# ifdef mxc_cpu_type
131# undef mxc_cpu_type
132# define mxc_cpu_type __mxc_cpu_type
133# else
134# define mxc_cpu_type MXC_CPU_MX50
135# endif
136# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
137#else
138# define cpu_is_mx50() (0)
139#endif
140
141#ifdef CONFIG_SOC_IMX51 128#ifdef CONFIG_SOC_IMX51
142# ifdef mxc_cpu_type 129# ifdef mxc_cpu_type
143# undef mxc_cpu_type 130# undef mxc_cpu_type
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 66fae885c842..b2872ec614a4 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -12,9 +12,9 @@
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/smp.h> 14#include <linux/smp.h>
15#include <linux/irqchip/arm-gic.h>
15#include <asm/page.h> 16#include <asm/page.h>
16#include <asm/smp_scu.h> 17#include <asm/smp_scu.h>
17#include <asm/hardware/gic.h>
18#include <asm/mach/map.h> 18#include <asm/mach/map.h>
19 19
20#include "common.h" 20#include "common.h"
@@ -71,8 +71,6 @@ static void __init imx_smp_init_cpus(void)
71 71
72 for (i = 0; i < ncores; i++) 72 for (i = 0; i < ncores; i++)
73 set_cpu_possible(i, true); 73 set_cpu_possible(i, true);
74
75 set_smp_cross_call(gic_raise_softirq);
76} 74}
77 75
78void imx_smp_prepare(void) 76void imx_smp_prepare(void)
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 2e063c2deb9e..f67fd7ee8127 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -34,7 +34,7 @@
34 34
35/* 35/*
36 * set cpu low power mode before WFI instruction. This function is called 36 * set cpu low power mode before WFI instruction. This function is called
37 * mx5 because it can be used for mx50, mx51, and mx53. 37 * mx5 because it can be used for mx51, and mx53.
38 */ 38 */
39static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) 39static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
40{ 40{
@@ -85,10 +85,7 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
85 __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); 85 __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
86 __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); 86 __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
87 __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); 87 __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
88 88 __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
89 /* Enable NEON SRPG for all but MX50TO1.0. */
90 if (mx50_revision() != IMX_CHIP_REVISION_1_0)
91 __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
92 89
93 if (stop_mode) { 90 if (stop_mode) {
94 empgc0 |= MXC_SRPGCR_PCR; 91 empgc0 |= MXC_SRPGCR_PCR;
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index f017302f6d09..62769df36db1 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -256,7 +256,6 @@ static struct irqaction mxc_timer_irq = {
256static struct clock_event_device clockevent_mxc = { 256static struct clock_event_device clockevent_mxc = {
257 .name = "mxc_timer1", 257 .name = "mxc_timer1",
258 .features = CLOCK_EVT_FEAT_ONESHOT, 258 .features = CLOCK_EVT_FEAT_ONESHOT,
259 .shift = 32,
260 .set_mode = mxc_set_mode, 259 .set_mode = mxc_set_mode,
261 .set_next_event = mx1_2_set_next_event, 260 .set_next_event = mx1_2_set_next_event,
262 .rating = 200, 261 .rating = 200,
@@ -264,21 +263,13 @@ static struct clock_event_device clockevent_mxc = {
264 263
265static int __init mxc_clockevent_init(struct clk *timer_clk) 264static int __init mxc_clockevent_init(struct clk *timer_clk)
266{ 265{
267 unsigned int c = clk_get_rate(timer_clk);
268
269 if (timer_is_v2()) 266 if (timer_is_v2())
270 clockevent_mxc.set_next_event = v2_set_next_event; 267 clockevent_mxc.set_next_event = v2_set_next_event;
271 268
272 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
273 clockevent_mxc.shift);
274 clockevent_mxc.max_delta_ns =
275 clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
276 clockevent_mxc.min_delta_ns =
277 clockevent_delta2ns(0xff, &clockevent_mxc);
278
279 clockevent_mxc.cpumask = cpumask_of(0); 269 clockevent_mxc.cpumask = cpumask_of(0);
280 270 clockevents_config_and_register(&clockevent_mxc,
281 clockevents_register_device(&clockevent_mxc); 271 clk_get_rate(timer_clk),
272 0xff, 0xfffffffe);
282 273
283 return 0; 274 return 0;
284} 275}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 18:50:00 -0500