diff options
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r-- | arch/arm/mach-imx/Makefile | 4 | ||||
-rw-r--r-- | arch/arm/mach-imx/cpu-imx5.c | 36 | ||||
-rw-r--r-- | arch/arm/mach-imx/crmregs-imx3.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-imx/mm-imx3.c | 11 | ||||
-rw-r--r-- | arch/arm/mach-imx/mm-imx5.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-imx/pm-imx3.c | 37 |
6 files changed, 61 insertions, 38 deletions
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 190d57006163..1ca9558723c2 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
@@ -8,8 +8,8 @@ obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o | |||
8 | obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o | 8 | obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o |
9 | obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o | 9 | obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o |
10 | 10 | ||
11 | obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o | 11 | obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o |
12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o | 12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o |
13 | 13 | ||
14 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o | 14 | obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o |
15 | 15 | ||
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c index 5e2e7a843860..aa15c517d06e 100644 --- a/arch/arm/mach-imx/cpu-imx5.c +++ b/arch/arm/mach-imx/cpu-imx5.c | |||
@@ -149,39 +149,3 @@ int mx50_revision(void) | |||
149 | return mx5_cpu_rev; | 149 | return mx5_cpu_rev; |
150 | } | 150 | } |
151 | EXPORT_SYMBOL(mx50_revision); | 151 | EXPORT_SYMBOL(mx50_revision); |
152 | |||
153 | static int __init post_cpu_init(void) | ||
154 | { | ||
155 | unsigned int reg; | ||
156 | void __iomem *base; | ||
157 | |||
158 | if (cpu_is_mx51() || cpu_is_mx53()) { | ||
159 | if (cpu_is_mx51()) | ||
160 | base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); | ||
161 | else | ||
162 | base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR); | ||
163 | |||
164 | __raw_writel(0x0, base + 0x40); | ||
165 | __raw_writel(0x0, base + 0x44); | ||
166 | __raw_writel(0x0, base + 0x48); | ||
167 | __raw_writel(0x0, base + 0x4C); | ||
168 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; | ||
169 | __raw_writel(reg, base + 0x50); | ||
170 | |||
171 | if (cpu_is_mx51()) | ||
172 | base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); | ||
173 | else | ||
174 | base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR); | ||
175 | |||
176 | __raw_writel(0x0, base + 0x40); | ||
177 | __raw_writel(0x0, base + 0x44); | ||
178 | __raw_writel(0x0, base + 0x48); | ||
179 | __raw_writel(0x0, base + 0x4C); | ||
180 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; | ||
181 | __raw_writel(reg, base + 0x50); | ||
182 | } | ||
183 | |||
184 | return 0; | ||
185 | } | ||
186 | |||
187 | postcore_initcall(post_cpu_init); | ||
diff --git a/arch/arm/mach-imx/crmregs-imx3.h b/arch/arm/mach-imx/crmregs-imx3.h index d7691e2362c1..53141273df45 100644 --- a/arch/arm/mach-imx/crmregs-imx3.h +++ b/arch/arm/mach-imx/crmregs-imx3.h | |||
@@ -77,6 +77,7 @@ MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)) | |||
77 | #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) | 77 | #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) |
78 | #define MXC_CCM_CCMR_LPM_OFFSET 14 | 78 | #define MXC_CCM_CCMR_LPM_OFFSET 14 |
79 | #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) | 79 | #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) |
80 | #define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14) | ||
80 | #define MXC_CCM_CCMR_FIRS_OFFSET 11 | 81 | #define MXC_CCM_CCMR_FIRS_OFFSET 11 |
81 | #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) | 82 | #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) |
82 | #define MXC_CCM_CCMR_UPE (1 << 9) | 83 | #define MXC_CCM_CCMR_UPE (1 << 9) |
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index 07699196b461..f8ca96c354f2 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c | |||
@@ -34,6 +34,8 @@ static void imx3_idle(void) | |||
34 | { | 34 | { |
35 | unsigned long reg = 0; | 35 | unsigned long reg = 0; |
36 | 36 | ||
37 | mx3_cpu_lp_set(MX3_WAIT); | ||
38 | |||
37 | __asm__ __volatile__( | 39 | __asm__ __volatile__( |
38 | /* disable I and D cache */ | 40 | /* disable I and D cache */ |
39 | "mrc p15, 0, %0, c1, c0, 0\n" | 41 | "mrc p15, 0, %0, c1, c0, 0\n" |
@@ -177,6 +179,10 @@ void __init imx31_soc_init(void) | |||
177 | } | 179 | } |
178 | 180 | ||
179 | imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); | 181 | imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); |
182 | |||
183 | imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); | ||
184 | imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR)); | ||
185 | |||
180 | platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, | 186 | platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, |
181 | ARRAY_SIZE(imx31_audmux_res)); | 187 | ARRAY_SIZE(imx31_audmux_res)); |
182 | } | 188 | } |
@@ -267,6 +273,11 @@ void __init imx35_soc_init(void) | |||
267 | } | 273 | } |
268 | 274 | ||
269 | imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); | 275 | imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); |
276 | |||
277 | /* Setup AIPS registers */ | ||
278 | imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR)); | ||
279 | imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR)); | ||
280 | |||
270 | /* i.mx35 has the i.mx31 type audmux */ | 281 | /* i.mx35 has the i.mx31 type audmux */ |
271 | platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, | 282 | platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, |
272 | ARRAY_SIZE(imx35_audmux_res)); | 283 | ARRAY_SIZE(imx35_audmux_res)); |
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index dc7c4ed81531..51af9fa56944 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c | |||
@@ -201,6 +201,11 @@ void __init imx51_soc_init(void) | |||
201 | 201 | ||
202 | /* i.mx51 has the i.mx35 type sdma */ | 202 | /* i.mx51 has the i.mx35 type sdma */ |
203 | imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); | 203 | imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); |
204 | |||
205 | /* Setup AIPS registers */ | ||
206 | imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR)); | ||
207 | imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR)); | ||
208 | |||
204 | /* i.mx51 has the i.mx31 type audmux */ | 209 | /* i.mx51 has the i.mx31 type audmux */ |
205 | platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res, | 210 | platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res, |
206 | ARRAY_SIZE(imx51_audmux_res)); | 211 | ARRAY_SIZE(imx51_audmux_res)); |
@@ -219,6 +224,11 @@ void __init imx53_soc_init(void) | |||
219 | 224 | ||
220 | /* i.mx53 has the i.mx35 type sdma */ | 225 | /* i.mx53 has the i.mx35 type sdma */ |
221 | imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); | 226 | imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); |
227 | |||
228 | /* Setup AIPS registers */ | ||
229 | imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR)); | ||
230 | imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR)); | ||
231 | |||
222 | /* i.mx53 has the i.mx31 type audmux */ | 232 | /* i.mx53 has the i.mx31 type audmux */ |
223 | platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res, | 233 | platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res, |
224 | ARRAY_SIZE(imx53_audmux_res)); | 234 | ARRAY_SIZE(imx53_audmux_res)); |
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c new file mode 100644 index 000000000000..b3752439632e --- /dev/null +++ b/arch/arm/mach-imx/pm-imx3.c | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | #include <linux/io.h> | ||
12 | #include <mach/common.h> | ||
13 | #include <mach/hardware.h> | ||
14 | #include <mach/devices-common.h> | ||
15 | #include "crmregs-imx3.h" | ||
16 | |||
17 | /* | ||
18 | * Set cpu low power mode before WFI instruction. This function is called | ||
19 | * mx3 because it can be used for mx31 and mx35. | ||
20 | * Currently only WAIT_MODE is supported. | ||
21 | */ | ||
22 | void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode) | ||
23 | { | ||
24 | int reg = __raw_readl(MXC_CCM_CCMR); | ||
25 | reg &= ~MXC_CCM_CCMR_LPM_MASK; | ||
26 | |||
27 | switch (mode) { | ||
28 | case MX3_WAIT: | ||
29 | if (cpu_is_mx35()) | ||
30 | reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; | ||
31 | __raw_writel(reg, MXC_CCM_CCMR); | ||
32 | break; | ||
33 | default: | ||
34 | pr_err("Unknown cpu power mode: %d\n", mode); | ||
35 | return; | ||
36 | } | ||
37 | } | ||