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-rw-r--r--arch/arm/mach-imx/system.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 5e3027d3692f..3b0733edb68c 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -124,7 +124,7 @@ void __init imx_init_l2cache(void)
124 } 124 }
125 125
126 /* Configure the L2 PREFETCH and POWER registers */ 126 /* Configure the L2 PREFETCH and POWER registers */
127 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); 127 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
128 val |= 0x70800000; 128 val |= 0x70800000;
129 /* 129 /*
130 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 130 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
@@ -137,14 +137,12 @@ void __init imx_init_l2cache(void)
137 */ 137 */
138 if (cpu_is_imx6q()) 138 if (cpu_is_imx6q())
139 val &= ~(1 << 30 | 1 << 23); 139 val &= ~(1 << 30 | 1 << 23);
140 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); 140 writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
141 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
142 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
143 141
144 iounmap(l2x0_base); 142 iounmap(l2x0_base);
145 of_node_put(np); 143 of_node_put(np);
146 144
147out: 145out:
148 l2x0_of_init(0, ~0UL); 146 l2x0_of_init(0, ~0);
149} 147}
150#endif 148#endif