diff options
Diffstat (limited to 'arch/arm/mach-imx/mx35.h')
| -rw-r--r-- | arch/arm/mach-imx/mx35.h | 190 |
1 files changed, 190 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx35.h b/arch/arm/mach-imx/mx35.h new file mode 100644 index 000000000000..2af5d3a699c7 --- /dev/null +++ b/arch/arm/mach-imx/mx35.h | |||
| @@ -0,0 +1,190 @@ | |||
| 1 | #ifndef __MACH_MX35_H__ | ||
| 2 | #define __MACH_MX35_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * IRAM | ||
| 6 | */ | ||
| 7 | #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ | ||
| 8 | #define MX35_IRAM_SIZE SZ_128K | ||
| 9 | |||
| 10 | #define MX35_L2CC_BASE_ADDR 0x30000000 | ||
| 11 | #define MX35_L2CC_SIZE SZ_1M | ||
| 12 | |||
| 13 | #define MX35_AIPS1_BASE_ADDR 0x43f00000 | ||
| 14 | #define MX35_AIPS1_SIZE SZ_1M | ||
| 15 | #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) | ||
| 16 | #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) | ||
| 17 | #define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000) | ||
| 18 | #define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) | ||
| 19 | #define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) | ||
| 20 | #define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) | ||
| 21 | #define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) | ||
| 22 | #define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) | ||
| 23 | #define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) | ||
| 24 | #define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) | ||
| 25 | #define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000) | ||
| 26 | #define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000) | ||
| 27 | #define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000) | ||
| 28 | #define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000) | ||
| 29 | #define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000) | ||
| 30 | #define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000) | ||
| 31 | #define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000) | ||
| 32 | #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) | ||
| 33 | |||
| 34 | #define MX35_SPBA0_BASE_ADDR 0x50000000 | ||
| 35 | #define MX35_SPBA0_SIZE SZ_1M | ||
| 36 | #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) | ||
| 37 | #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) | ||
| 38 | #define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) | ||
| 39 | #define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) | ||
| 40 | #define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) | ||
| 41 | #define MX35_FEC_BASE_ADDR 0x50038000 | ||
| 42 | #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) | ||
| 43 | |||
| 44 | #define MX35_AIPS2_BASE_ADDR 0x53f00000 | ||
| 45 | #define MX35_AIPS2_SIZE SZ_1M | ||
| 46 | #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) | ||
| 47 | #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) | ||
| 48 | #define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000) | ||
| 49 | #define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000) | ||
| 50 | #define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) | ||
| 51 | #define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) | ||
| 52 | #define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) | ||
| 53 | #define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000) | ||
| 54 | #define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000) | ||
| 55 | #define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000) | ||
| 56 | #define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) | ||
| 57 | #define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) | ||
| 58 | #define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) | ||
| 59 | #define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000) | ||
| 60 | #define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000) | ||
| 61 | #define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) | ||
| 62 | #define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) | ||
| 63 | #define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) | ||
| 64 | #define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) | ||
| 65 | #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) | ||
| 66 | #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) | ||
| 67 | #define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) | ||
| 68 | #define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) | ||
| 69 | #define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) | ||
| 70 | /* | ||
| 71 | * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for | ||
| 72 | * HS. When host support was implemented only a preliminary document was | ||
| 73 | * available, which told 0x400. This works fine. | ||
| 74 | */ | ||
| 75 | #define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) | ||
| 76 | |||
| 77 | #define MX35_ROMP_BASE_ADDR 0x60000000 | ||
| 78 | #define MX35_ROMP_SIZE SZ_1M | ||
| 79 | |||
| 80 | #define MX35_AVIC_BASE_ADDR 0x68000000 | ||
| 81 | #define MX35_AVIC_SIZE SZ_1M | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Memory regions and CS | ||
| 85 | */ | ||
| 86 | #define MX35_IPU_MEM_BASE_ADDR 0x70000000 | ||
| 87 | #define MX35_CSD0_BASE_ADDR 0x80000000 | ||
| 88 | #define MX35_CSD1_BASE_ADDR 0x90000000 | ||
| 89 | |||
| 90 | #define MX35_CS0_BASE_ADDR 0xa0000000 | ||
| 91 | #define MX35_CS1_BASE_ADDR 0xa8000000 | ||
| 92 | #define MX35_CS2_BASE_ADDR 0xb0000000 | ||
| 93 | #define MX35_CS3_BASE_ADDR 0xb2000000 | ||
| 94 | |||
| 95 | #define MX35_CS4_BASE_ADDR 0xb4000000 | ||
| 96 | #define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 | ||
| 97 | #define MX35_CS4_SIZE SZ_32M | ||
| 98 | |||
| 99 | #define MX35_CS5_BASE_ADDR 0xb6000000 | ||
| 100 | #define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 | ||
| 101 | #define MX35_CS5_SIZE SZ_32M | ||
| 102 | |||
| 103 | /* | ||
| 104 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 105 | */ | ||
| 106 | #define MX35_X_MEMC_BASE_ADDR 0xb8000000 | ||
| 107 | #define MX35_X_MEMC_SIZE SZ_64K | ||
| 108 | #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) | ||
| 109 | #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) | ||
| 110 | #define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000) | ||
| 111 | #define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000) | ||
| 112 | #define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR | ||
| 113 | |||
| 114 | #define MX35_NFC_BASE_ADDR 0xbb000000 | ||
| 115 | #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 | ||
| 116 | |||
| 117 | #define MX35_IO_P2V(x) IMX_IO_P2V(x) | ||
| 118 | #define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) | ||
| 119 | |||
| 120 | /* | ||
| 121 | * Interrupt numbers | ||
| 122 | */ | ||
| 123 | #include <asm/irq.h> | ||
| 124 | #define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2) | ||
| 125 | #define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3) | ||
| 126 | #define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4) | ||
| 127 | #define MX35_INT_RTIC (NR_IRQS_LEGACY + 6) | ||
| 128 | #define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7) | ||
| 129 | #define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8) | ||
| 130 | #define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9) | ||
| 131 | #define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10) | ||
| 132 | #define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11) | ||
| 133 | #define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12) | ||
| 134 | #define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13) | ||
| 135 | #define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14) | ||
| 136 | #define MX35_INT_ATA (NR_IRQS_LEGACY + 15) | ||
| 137 | #define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16) | ||
| 138 | #define MX35_INT_ASRC (NR_IRQS_LEGACY + 17) | ||
| 139 | #define MX35_INT_UART3 (NR_IRQS_LEGACY + 18) | ||
| 140 | #define MX35_INT_IIM (NR_IRQS_LEGACY + 19) | ||
| 141 | #define MX35_INT_RNGA (NR_IRQS_LEGACY + 22) | ||
| 142 | #define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23) | ||
| 143 | #define MX35_INT_KPP (NR_IRQS_LEGACY + 24) | ||
| 144 | #define MX35_INT_RTC (NR_IRQS_LEGACY + 25) | ||
| 145 | #define MX35_INT_PWM (NR_IRQS_LEGACY + 26) | ||
| 146 | #define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27) | ||
| 147 | #define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28) | ||
| 148 | #define MX35_INT_GPT (NR_IRQS_LEGACY + 29) | ||
| 149 | #define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) | ||
| 150 | #define MX35_INT_UART2 (NR_IRQS_LEGACY + 32) | ||
| 151 | #define MX35_INT_NFC (NR_IRQS_LEGACY + 33) | ||
| 152 | #define MX35_INT_SDMA (NR_IRQS_LEGACY + 34) | ||
| 153 | #define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35) | ||
| 154 | #define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37) | ||
| 155 | #define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39) | ||
| 156 | #define MX35_INT_ESAI (NR_IRQS_LEGACY + 40) | ||
| 157 | #define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41) | ||
| 158 | #define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42) | ||
| 159 | #define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43) | ||
| 160 | #define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44) | ||
| 161 | #define MX35_INT_UART1 (NR_IRQS_LEGACY + 45) | ||
| 162 | #define MX35_INT_MLB (NR_IRQS_LEGACY + 46) | ||
| 163 | #define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47) | ||
| 164 | #define MX35_INT_ECT (NR_IRQS_LEGACY + 48) | ||
| 165 | #define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49) | ||
| 166 | #define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50) | ||
| 167 | #define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51) | ||
| 168 | #define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52) | ||
| 169 | #define MX35_INT_WDOG (NR_IRQS_LEGACY + 55) | ||
| 170 | #define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56) | ||
| 171 | #define MX35_INT_FEC (NR_IRQS_LEGACY + 57) | ||
| 172 | #define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58) | ||
| 173 | #define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) | ||
| 174 | #define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) | ||
| 175 | #define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) | ||
| 176 | #define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) | ||
| 177 | #define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63) | ||
| 178 | |||
| 179 | #define MX35_DMA_REQ_SSI2_RX1 22 | ||
| 180 | #define MX35_DMA_REQ_SSI2_TX1 23 | ||
| 181 | #define MX35_DMA_REQ_SSI2_RX0 24 | ||
| 182 | #define MX35_DMA_REQ_SSI2_TX0 25 | ||
| 183 | #define MX35_DMA_REQ_SSI1_RX1 26 | ||
| 184 | #define MX35_DMA_REQ_SSI1_TX1 27 | ||
| 185 | #define MX35_DMA_REQ_SSI1_RX0 28 | ||
| 186 | #define MX35_DMA_REQ_SSI1_TX0 29 | ||
| 187 | |||
| 188 | #define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ | ||
| 189 | |||
| 190 | #endif /* ifndef __MACH_MX35_H__ */ | ||