diff options
Diffstat (limited to 'arch/arm/mach-imx/mx25.h')
| -rw-r--r-- | arch/arm/mach-imx/mx25.h | 117 |
1 files changed, 0 insertions, 117 deletions
diff --git a/arch/arm/mach-imx/mx25.h b/arch/arm/mach-imx/mx25.h deleted file mode 100644 index ec466400a200..000000000000 --- a/arch/arm/mach-imx/mx25.h +++ /dev/null | |||
| @@ -1,117 +0,0 @@ | |||
| 1 | #ifndef __MACH_MX25_H__ | ||
| 2 | #define __MACH_MX25_H__ | ||
| 3 | |||
| 4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 | ||
| 5 | #define MX25_AIPS1_SIZE SZ_1M | ||
| 6 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 | ||
| 7 | #define MX25_AIPS2_SIZE SZ_1M | ||
| 8 | #define MX25_AVIC_BASE_ADDR 0x68000000 | ||
| 9 | #define MX25_AVIC_SIZE SZ_1M | ||
| 10 | |||
| 11 | #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) | ||
| 12 | #define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) | ||
| 13 | #define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) | ||
| 14 | #define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) | ||
| 15 | #define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) | ||
| 16 | #define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) | ||
| 17 | #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) | ||
| 18 | |||
| 19 | #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) | ||
| 20 | #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) | ||
| 21 | #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) | ||
| 22 | #define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) | ||
| 23 | #define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) | ||
| 24 | #define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) | ||
| 25 | #define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) | ||
| 26 | #define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) | ||
| 27 | #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) | ||
| 28 | #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) | ||
| 29 | #define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) | ||
| 30 | |||
| 31 | #define MX25_UART1_BASE_ADDR 0x43f90000 | ||
| 32 | #define MX25_UART2_BASE_ADDR 0x43f94000 | ||
| 33 | #define MX25_AUDMUX_BASE_ADDR 0x43fb0000 | ||
| 34 | #define MX25_UART3_BASE_ADDR 0x5000c000 | ||
| 35 | #define MX25_UART4_BASE_ADDR 0x50008000 | ||
| 36 | #define MX25_UART5_BASE_ADDR 0x5002c000 | ||
| 37 | |||
| 38 | #define MX25_CSPI3_BASE_ADDR 0x50004000 | ||
| 39 | #define MX25_CSPI2_BASE_ADDR 0x50010000 | ||
| 40 | #define MX25_FEC_BASE_ADDR 0x50038000 | ||
| 41 | #define MX25_SSI2_BASE_ADDR 0x50014000 | ||
| 42 | #define MX25_SSI1_BASE_ADDR 0x50034000 | ||
| 43 | #define MX25_NFC_BASE_ADDR 0xbb000000 | ||
| 44 | #define MX25_IIM_BASE_ADDR 0x53ff0000 | ||
| 45 | #define MX25_DRYICE_BASE_ADDR 0x53ffc000 | ||
| 46 | #define MX25_ESDHC1_BASE_ADDR 0x53fb4000 | ||
| 47 | #define MX25_ESDHC2_BASE_ADDR 0x53fb8000 | ||
| 48 | #define MX25_LCDC_BASE_ADDR 0x53fbc000 | ||
| 49 | #define MX25_KPP_BASE_ADDR 0x43fa8000 | ||
| 50 | #define MX25_SDMA_BASE_ADDR 0x53fd4000 | ||
| 51 | #define MX25_USB_BASE_ADDR 0x53ff4000 | ||
| 52 | #define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) | ||
| 53 | /* | ||
| 54 | * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 | ||
| 55 | * for the host controller. Early documentation drafts specified 0x400 and | ||
| 56 | * Freescale internal sources confirm only the latter value to work. | ||
| 57 | */ | ||
| 58 | #define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) | ||
| 59 | #define MX25_CSI_BASE_ADDR 0x53ff8000 | ||
| 60 | |||
| 61 | #define MX25_IO_P2V(x) IMX_IO_P2V(x) | ||
| 62 | #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) | ||
| 63 | |||
| 64 | /* | ||
| 65 | * Interrupt numbers | ||
| 66 | */ | ||
| 67 | #include <asm/irq.h> | ||
| 68 | #define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0) | ||
| 69 | #define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3) | ||
| 70 | #define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4) | ||
| 71 | #define MX25_INT_UART4 (NR_IRQS_LEGACY + 5) | ||
| 72 | #define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8) | ||
| 73 | #define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9) | ||
| 74 | #define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10) | ||
| 75 | #define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11) | ||
| 76 | #define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12) | ||
| 77 | #define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13) | ||
| 78 | #define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14) | ||
| 79 | #define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16) | ||
| 80 | #define MX25_INT_CSI (NR_IRQS_LEGACY + 17) | ||
| 81 | #define MX25_INT_UART3 (NR_IRQS_LEGACY + 18) | ||
| 82 | #define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23) | ||
| 83 | #define MX25_INT_KPP (NR_IRQS_LEGACY + 24) | ||
| 84 | #define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25) | ||
| 85 | #define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26) | ||
| 86 | #define MX25_INT_UART2 (NR_IRQS_LEGACY + 32) | ||
| 87 | #define MX25_INT_NFC (NR_IRQS_LEGACY + 33) | ||
| 88 | #define MX25_INT_SDMA (NR_IRQS_LEGACY + 34) | ||
| 89 | #define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35) | ||
| 90 | #define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36) | ||
| 91 | #define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37) | ||
| 92 | #define MX25_INT_LCDC (NR_IRQS_LEGACY + 39) | ||
| 93 | #define MX25_INT_UART5 (NR_IRQS_LEGACY + 40) | ||
| 94 | #define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41) | ||
| 95 | #define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42) | ||
| 96 | #define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43) | ||
| 97 | #define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44) | ||
| 98 | #define MX25_INT_UART1 (NR_IRQS_LEGACY + 45) | ||
| 99 | #define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51) | ||
| 100 | #define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52) | ||
| 101 | #define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54) | ||
| 102 | #define MX25_INT_FEC (NR_IRQS_LEGACY + 57) | ||
| 103 | |||
| 104 | #define MX25_DMA_REQ_SSI2_RX1 22 | ||
| 105 | #define MX25_DMA_REQ_SSI2_TX1 23 | ||
| 106 | #define MX25_DMA_REQ_SSI2_RX0 24 | ||
| 107 | #define MX25_DMA_REQ_SSI2_TX0 25 | ||
| 108 | #define MX25_DMA_REQ_SSI1_RX1 26 | ||
| 109 | #define MX25_DMA_REQ_SSI1_TX1 27 | ||
| 110 | #define MX25_DMA_REQ_SSI1_RX0 28 | ||
| 111 | #define MX25_DMA_REQ_SSI1_TX0 29 | ||
| 112 | |||
| 113 | #ifndef __ASSEMBLY__ | ||
| 114 | extern int mx25_revision(void); | ||
| 115 | #endif | ||
| 116 | |||
| 117 | #endif /* ifndef __MACH_MX25_H__ */ | ||