diff options
Diffstat (limited to 'arch/arm/mach-imx/mm-imx5.c')
-rw-r--r-- | arch/arm/mach-imx/mm-imx5.c | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index acb0aadb4255..79d71cf23a1d 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c | |||
@@ -18,10 +18,10 @@ | |||
18 | 18 | ||
19 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
20 | 20 | ||
21 | #include <mach/hardware.h> | 21 | #include "common.h" |
22 | #include <mach/common.h> | 22 | #include "devices/devices-common.h" |
23 | #include <mach/devices-common.h> | 23 | #include "hardware.h" |
24 | #include <mach/iomux-v3.h> | 24 | #include "iomux-v3.h" |
25 | 25 | ||
26 | /* | 26 | /* |
27 | * Define the MX50 memory map. | 27 | * Define the MX50 memory map. |
@@ -81,8 +81,28 @@ void __init imx50_init_early(void) | |||
81 | mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); | 81 | mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); |
82 | } | 82 | } |
83 | 83 | ||
84 | /* | ||
85 | * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by | ||
86 | * the Freescale marketing division. However this did not remove the | ||
87 | * hardware from the chip which still needs to be configured for proper | ||
88 | * IPU support. | ||
89 | */ | ||
90 | static void __init imx51_ipu_mipi_setup(void) | ||
91 | { | ||
92 | void __iomem *hsc_addr; | ||
93 | hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR); | ||
94 | |||
95 | /* setup MIPI module to legacy mode */ | ||
96 | __raw_writel(0xf00, hsc_addr); | ||
97 | |||
98 | /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ | ||
99 | __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, | ||
100 | hsc_addr + 0x800); | ||
101 | } | ||
102 | |||
84 | void __init imx51_init_early(void) | 103 | void __init imx51_init_early(void) |
85 | { | 104 | { |
105 | imx51_ipu_mipi_setup(); | ||
86 | mxc_set_cpu_type(MXC_CPU_MX51); | 106 | mxc_set_cpu_type(MXC_CPU_MX51); |
87 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); | 107 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); |
88 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); | 108 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); |
@@ -138,6 +158,8 @@ static const struct resource imx51_audmux_res[] __initconst = { | |||
138 | 158 | ||
139 | void __init imx50_soc_init(void) | 159 | void __init imx50_soc_init(void) |
140 | { | 160 | { |
161 | mxc_device_init(); | ||
162 | |||
141 | /* i.mx50 has the i.mx35 type gpio */ | 163 | /* i.mx50 has the i.mx35 type gpio */ |
142 | mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); | 164 | mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); |
143 | mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); | 165 | mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); |
@@ -153,6 +175,8 @@ void __init imx50_soc_init(void) | |||
153 | 175 | ||
154 | void __init imx51_soc_init(void) | 176 | void __init imx51_soc_init(void) |
155 | { | 177 | { |
178 | mxc_device_init(); | ||
179 | |||
156 | /* i.mx51 has the i.mx35 type gpio */ | 180 | /* i.mx51 has the i.mx35 type gpio */ |
157 | mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); | 181 | mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); |
158 | mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); | 182 | mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); |