1 files changed, 28 insertions, 25 deletions
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 9f0e82ec3398..6d01de326f90 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -33,29 +33,32 @@
 static void imx3_idle(void)
 {
        unsigned long reg = 0;
-        __asm__ __volatile__(
-                /* disable I and D cache */
+        if (!need_resched())
-                "mrc p15, 0, %0, c1, c0, 0\n"
+                __asm__ __volatile__(
-                "bic %0, %0, #0x00001000\n"
+                        /* disable I and D cache */
-                "bic %0, %0, #0x00000004\n"
+                        "mrc p15, 0, %0, c1, c0, 0\n"
-                "mcr p15, 0, %0, c1, c0, 0\n"
+                        "bic %0, %0, #0x00001000\n"
-                /* invalidate I cache */
+                        "bic %0, %0, #0x00000004\n"
-                "mov %0, #0\n"
+                        "mcr p15, 0, %0, c1, c0, 0\n"
-                "mcr p15, 0, %0, c7, c5, 0\n"
+                        /* invalidate I cache */
-                /* clear and invalidate D cache */
+                        "mov %0, #0\n"
-                "mov %0, #0\n"
+                        "mcr p15, 0, %0, c7, c5, 0\n"
-                "mcr p15, 0, %0, c7, c14, 0\n"
+                        /* clear and invalidate D cache */
-                /* WFI */
+                        "mov %0, #0\n"
-                "mov %0, #0\n"
+                        "mcr p15, 0, %0, c7, c14, 0\n"
-                "mcr p15, 0, %0, c7, c0, 4\n"
+                        /* WFI */
-                "nop\n" "nop\n" "nop\n" "nop\n"
+                        "mov %0, #0\n"
-                "nop\n" "nop\n" "nop\n"
+                        "mcr p15, 0, %0, c7, c0, 4\n"
-                /* enable I and D cache */
+                        "nop\n" "nop\n" "nop\n" "nop\n"
-                "mrc p15, 0, %0, c1, c0, 0\n"
+                        "nop\n" "nop\n" "nop\n"
-                "orr %0, %0, #0x00001000\n"
+                        /* enable I and D cache */
-                "orr %0, %0, #0x00000004\n"
+                        "mrc p15, 0, %0, c1, c0, 0\n"
-                "mcr p15, 0, %0, c1, c0, 0\n"
+                        "orr %0, %0, #0x00001000\n"
-                : "=r" (reg));
+                        "orr %0, %0, #0x00000004\n"
+                        "mcr p15, 0, %0, c1, c0, 0\n"
+                        : "=r" (reg));
+        local_irq_enable();
 }
 static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@ -143,7 +146,7 @@ void __init imx31_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX31);
        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-        imx_idle = imx3_idle;
+        pm_idle = imx3_idle;
        imx_ioremap = imx3_ioremap;
 }
@@ -152,7 +155,7 @@ void __init imx35_init_early(void)
        mxc_set_cpu_type(MXC_CPU_MX35);
        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-        imx_idle = imx3_idle;
+        pm_idle = imx3_idle;
        imx_ioremap = imx3_ioremap;
 }

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index 9f0e82ec3398..6d01de326f90 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c
@@ -33,29 +33,32 @@
33	static void imx3_idle(void)	33	static void imx3_idle(void)
34	{	34	{
35	unsigned long reg = 0;	35	unsigned long reg = 0;
36	__asm__ __volatile__(	36
37	/* disable I and D cache */	37	if (!need_resched())
38	"mrc p15, 0, %0, c1, c0, 0\n"	38	__asm__ __volatile__(
39	"bic %0, %0, #0x00001000\n"	39	/* disable I and D cache */
40	"bic %0, %0, #0x00000004\n"	40	"mrc p15, 0, %0, c1, c0, 0\n"
41	"mcr p15, 0, %0, c1, c0, 0\n"	41	"bic %0, %0, #0x00001000\n"
42	/* invalidate I cache */	42	"bic %0, %0, #0x00000004\n"
43	"mov %0, #0\n"	43	"mcr p15, 0, %0, c1, c0, 0\n"
44	"mcr p15, 0, %0, c7, c5, 0\n"	44	/* invalidate I cache */
45	/* clear and invalidate D cache */	45	"mov %0, #0\n"
46	"mov %0, #0\n"	46	"mcr p15, 0, %0, c7, c5, 0\n"
47	"mcr p15, 0, %0, c7, c14, 0\n"	47	/* clear and invalidate D cache */
48	/* WFI */	48	"mov %0, #0\n"
49	"mov %0, #0\n"	49	"mcr p15, 0, %0, c7, c14, 0\n"
50	"mcr p15, 0, %0, c7, c0, 4\n"	50	/* WFI */
51	"nop\n" "nop\n" "nop\n" "nop\n"	51	"mov %0, #0\n"
52	"nop\n" "nop\n" "nop\n"	52	"mcr p15, 0, %0, c7, c0, 4\n"
53	/* enable I and D cache */	53	"nop\n" "nop\n" "nop\n" "nop\n"
54	"mrc p15, 0, %0, c1, c0, 0\n"	54	"nop\n" "nop\n" "nop\n"
55	"orr %0, %0, #0x00001000\n"	55	/* enable I and D cache */
56	"orr %0, %0, #0x00000004\n"	56	"mrc p15, 0, %0, c1, c0, 0\n"
57	"mcr p15, 0, %0, c1, c0, 0\n"	57	"orr %0, %0, #0x00001000\n"
58	: "=r" (reg));	58	"orr %0, %0, #0x00000004\n"
		59	"mcr p15, 0, %0, c1, c0, 0\n"
		60	: "=r" (reg));
		61	local_irq_enable();
59	}	62	}
60		63
61	static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,	64	static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@ -143,7 +146,7 @@ void __init imx31_init_early(void)
143	{	146	{
144	mxc_set_cpu_type(MXC_CPU_MX31);	147	mxc_set_cpu_type(MXC_CPU_MX31);
145	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));	148	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
146	imx_idle = imx3_idle;	149	pm_idle = imx3_idle;
147	imx_ioremap = imx3_ioremap;	150	imx_ioremap = imx3_ioremap;
148	}	151	}
149		152
@@ -152,7 +155,7 @@ void __init imx35_init_early(void)
152	mxc_set_cpu_type(MXC_CPU_MX35);	155	mxc_set_cpu_type(MXC_CPU_MX35);
153	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));	156	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
154	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));	157	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
155	imx_idle = imx3_idle;	158	pm_idle = imx3_idle;
156	imx_ioremap = imx3_ioremap;	159	imx_ioremap = imx3_ioremap;
157	}	160	}
158		161