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Diffstat (limited to 'arch/arm/mach-imx/irq.c')
-rw-r--r--arch/arm/mach-imx/irq.c38
1 files changed, 30 insertions, 8 deletions
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index 798f221eb3b7..531b95deadc0 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -26,20 +26,17 @@
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/list.h> 27#include <linux/list.h>
28#include <linux/timer.h> 28#include <linux/timer.h>
29#include <linux/io.h>
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
31#include <asm/irq.h> 32#include <asm/irq.h>
32#include <asm/io.h>
33 33
34#include <asm/mach/irq.h> 34#include <asm/mach/irq.h>
35 35
36/* 36/*
37 * 37 *
38 * We simply use the ENABLE DISABLE registers inside of the IMX 38 * We simply use the ENABLE DISABLE registers inside of the IMX
39 * to turn on/off specific interrupts. FIXME- We should 39 * to turn on/off specific interrupts.
40 * also add support for the accelerated interrupt controller
41 * by putting offets to irq jump code in the appropriate
42 * places.
43 * 40 *
44 */ 41 */
45 42
@@ -102,6 +99,28 @@ imx_unmask_irq(unsigned int irq)
102 __raw_writel(irq, IMX_AITC_INTENNUM); 99 __raw_writel(irq, IMX_AITC_INTENNUM);
103} 100}
104 101
102#ifdef CONFIG_FIQ
103int imx_set_irq_fiq(unsigned int irq, unsigned int type)
104{
105 unsigned int irqt;
106
107 if (irq >= IMX_IRQS)
108 return -EINVAL;
109
110 if (irq < IMX_IRQS / 2) {
111 irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq);
112 __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL);
113 } else {
114 irq -= IMX_IRQS / 2;
115 irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq);
116 __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH);
117 }
118
119 return 0;
120}
121EXPORT_SYMBOL(imx_set_irq_fiq);
122#endif /* CONFIG_FIQ */
123
105static int 124static int
106imx_gpio_irq_type(unsigned int _irq, unsigned int type) 125imx_gpio_irq_type(unsigned int _irq, unsigned int type)
107{ 126{
@@ -182,14 +201,12 @@ static void
182imx_gpio_handler(unsigned int mask, unsigned int irq, 201imx_gpio_handler(unsigned int mask, unsigned int irq,
183 struct irq_desc *desc) 202 struct irq_desc *desc)
184{ 203{
185 desc = irq_desc + irq;
186 while (mask) { 204 while (mask) {
187 if (mask & 1) { 205 if (mask & 1) {
188 DEBUG_IRQ("handling irq %d\n", irq); 206 DEBUG_IRQ("handling irq %d\n", irq);
189 desc_handle_irq(irq, desc); 207 generic_handle_irq(irq);
190 } 208 }
191 irq++; 209 irq++;
192 desc++;
193 mask >>= 1; 210 mask >>= 1;
194 } 211 }
195} 212}
@@ -286,4 +303,9 @@ imx_init_irq(void)
286 303
287 /* Release masking of interrupts according to priority */ 304 /* Release masking of interrupts according to priority */
288 __raw_writel(-1, IMX_AITC_NIMASK); 305 __raw_writel(-1, IMX_AITC_NIMASK);
306
307#ifdef CONFIG_FIQ
308 /* Initialize FIQ */
309 init_FIQ();
310#endif
289} 311}