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-rw-r--r--arch/arm/mach-imx/include/mach/debug-macro.S34
-rw-r--r--arch/arm/mach-imx/include/mach/dma.h56
-rw-r--r--arch/arm/mach-imx/include/mach/entry-macro.S32
-rw-r--r--arch/arm/mach-imx/include/mach/gpio.h102
-rw-r--r--arch/arm/mach-imx/include/mach/hardware.h91
-rw-r--r--arch/arm/mach-imx/include/mach/imx-dma.h94
-rw-r--r--arch/arm/mach-imx/include/mach/imx-regs.h482
-rw-r--r--arch/arm/mach-imx/include/mach/imx-uart.h12
-rw-r--r--arch/arm/mach-imx/include/mach/imxfb.h37
-rw-r--r--arch/arm/mach-imx/include/mach/io.h30
-rw-r--r--arch/arm/mach-imx/include/mach/irqs.h116
-rw-r--r--arch/arm/mach-imx/include/mach/memory.h36
-rw-r--r--arch/arm/mach-imx/include/mach/mmc.h15
-rw-r--r--arch/arm/mach-imx/include/mach/mx1ads.h36
-rw-r--r--arch/arm/mach-imx/include/mach/spi_imx.h72
-rw-r--r--arch/arm/mach-imx/include/mach/system.h40
-rw-r--r--arch/arm/mach-imx/include/mach/timex.h26
-rw-r--r--arch/arm/mach-imx/include/mach/uncompress.h71
-rw-r--r--arch/arm/mach-imx/include/mach/vmalloc.h20
19 files changed, 1402 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/include/mach/debug-macro.S b/arch/arm/mach-imx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..87802bbfe633
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/debug-macro.S
@@ -0,0 +1,34 @@
1/* arch/arm/mach-imx/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 moveq \rx, #0x00000000 @ physical
18 movne \rx, #0xe0000000 @ virtual
19 orreq \rx, \rx, #0x00200000 @ physical
20 orr \rx, \rx, #0x00006000 @ UART1 offset
21 .endm
22
23 .macro senduart,rd,rx
24 str \rd, [\rx, #0x40] @ TXDATA
25 .endm
26
27 .macro waituart,rd,rx
28 .endm
29
30 .macro busyuart,rd,rx
311002: ldr \rd, [\rx, #0x98] @ SR2
32 tst \rd, #1 << 3 @ TXDC
33 beq 1002b @ wait until transmit done
34 .endm
diff --git a/arch/arm/mach-imx/include/mach/dma.h b/arch/arm/mach-imx/include/mach/dma.h
new file mode 100644
index 000000000000..621ff2c730f2
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/dma.h
@@ -0,0 +1,56 @@
1/*
2 * linux/include/asm-arm/imxads/dma.h
3 *
4 * Copyright (C) 1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24typedef enum {
25 DMA_PRIO_HIGH = 0,
26 DMA_PRIO_MEDIUM = 1,
27 DMA_PRIO_LOW = 2
28} imx_dma_prio;
29
30#define DMA_REQ_UART3_T 2
31#define DMA_REQ_UART3_R 3
32#define DMA_REQ_SSI2_T 4
33#define DMA_REQ_SSI2_R 5
34#define DMA_REQ_CSI_STAT 6
35#define DMA_REQ_CSI_R 7
36#define DMA_REQ_MSHC 8
37#define DMA_REQ_DSPA_DCT_DOUT 9
38#define DMA_REQ_DSPA_DCT_DIN 10
39#define DMA_REQ_DSPA_MAC 11
40#define DMA_REQ_EXT 12
41#define DMA_REQ_SDHC 13
42#define DMA_REQ_SPI1_R 14
43#define DMA_REQ_SPI1_T 15
44#define DMA_REQ_SSI_T 16
45#define DMA_REQ_SSI_R 17
46#define DMA_REQ_ASP_DAC 18
47#define DMA_REQ_ASP_ADC 19
48#define DMA_REQ_USP_EP(x) (20+(x))
49#define DMA_REQ_SPI2_R 26
50#define DMA_REQ_SPI2_T 27
51#define DMA_REQ_UART2_T 28
52#define DMA_REQ_UART2_R 29
53#define DMA_REQ_UART1_T 30
54#define DMA_REQ_UART1_R 31
55
56#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-imx/include/mach/entry-macro.S b/arch/arm/mach-imx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..e4db679f7766
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/entry-macro.S
@@ -0,0 +1,32 @@
1/*
2 * arch/arm/mach-imx/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for iMX-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/hardware.h>
11
12 .macro disable_fiq
13 .endm
14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro arch_ret_to_user, tmp1, tmp2
19 .endm
20
21#define AITC_NIVECSR 0x40
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23 ldr \base, =IO_ADDRESS(IMX_AITC_BASE)
24 @ Load offset & priority of the highest priority
25 @ interrupt pending.
26 ldr \irqstat, [\base, #AITC_NIVECSR]
27 @ Shift off the priority leaving the offset or
28 @ "interrupt number", use arithmetic shift to
29 @ transform illegal source (0xffff) as -1
30 mov \irqnr, \irqstat, asr #16
31 adds \tmp, \irqnr, #1
32 .endm
diff --git a/arch/arm/mach-imx/include/mach/gpio.h b/arch/arm/mach-imx/include/mach/gpio.h
new file mode 100644
index 000000000000..6e3d795f2264
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/gpio.h
@@ -0,0 +1,102 @@
1#ifndef _IMX_GPIO_H
2
3#include <mach/imx-regs.h>
4
5#define IMX_GPIO_ALLOC_MODE_NORMAL 0
6#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1
7#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2
8#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4
9#define IMX_GPIO_ALLOC_MODE_RELEASE 8
10
11extern int imx_gpio_request(unsigned gpio, const char *label);
12
13extern void imx_gpio_free(unsigned gpio);
14
15extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
16 int alloc_mode, const char *label);
17
18extern int imx_gpio_direction_input(unsigned gpio);
19
20extern int imx_gpio_direction_output(unsigned gpio, int value);
21
22extern void __imx_gpio_set_value(unsigned gpio, int value);
23
24static inline int imx_gpio_get_value(unsigned gpio)
25{
26 return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK));
27}
28
29static inline void imx_gpio_set_value_inline(unsigned gpio, int value)
30{
31 unsigned long flags;
32
33 raw_local_irq_save(flags);
34 if(value)
35 DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK));
36 else
37 DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK));
38 raw_local_irq_restore(flags);
39}
40
41static inline void imx_gpio_set_value(unsigned gpio, int value)
42{
43 if(__builtin_constant_p(gpio))
44 imx_gpio_set_value_inline(gpio, value);
45 else
46 __imx_gpio_set_value(gpio, value);
47}
48
49extern int imx_gpio_to_irq(unsigned gpio);
50
51extern int imx_irq_to_gpio(unsigned irq);
52
53/*-------------------------------------------------------------------------*/
54
55/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions
56 * to allow future extension of GPIO logic.
57 */
58
59static inline int gpio_request(unsigned gpio, const char *label)
60{
61 return imx_gpio_request(gpio, label);
62}
63
64static inline void gpio_free(unsigned gpio)
65{
66 imx_gpio_free(gpio);
67}
68
69static inline int gpio_direction_input(unsigned gpio)
70{
71 return imx_gpio_direction_input(gpio);
72}
73
74static inline int gpio_direction_output(unsigned gpio, int value)
75{
76 return imx_gpio_direction_output(gpio, value);
77}
78
79static inline int gpio_get_value(unsigned gpio)
80{
81 return imx_gpio_get_value(gpio);
82}
83
84static inline void gpio_set_value(unsigned gpio, int value)
85{
86 imx_gpio_set_value(gpio, value);
87}
88
89#include <asm-generic/gpio.h> /* cansleep wrappers */
90
91static inline int gpio_to_irq(unsigned gpio)
92{
93 return imx_gpio_to_irq(gpio);
94}
95
96static inline int irq_to_gpio(unsigned irq)
97{
98 return imx_irq_to_gpio(irq);
99}
100
101
102#endif
diff --git a/arch/arm/mach-imx/include/mach/hardware.h b/arch/arm/mach-imx/include/mach/hardware.h
new file mode 100644
index 000000000000..c73e9e724c75
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/hardware.h
@@ -0,0 +1,91 @@
1/*
2 * arch/arm/mach-imx/include/mach/hardware.h
3 *
4 * Copyright (C) 1999 ARM Limited.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_HARDWARE_H
21#define __ASM_ARCH_HARDWARE_H
22
23#include <asm/sizes.h>
24#include "imx-regs.h"
25
26#ifndef __ASSEMBLY__
27# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x)))
28
29# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
30#endif
31
32/*
33 * Memory map
34 */
35
36#define IMX_IO_PHYS 0x00200000
37#define IMX_IO_SIZE 0x00100000
38#define IMX_IO_BASE 0xe0000000
39
40#define IMX_CS0_PHYS 0x10000000
41#define IMX_CS0_SIZE 0x02000000
42#define IMX_CS0_VIRT 0xe8000000
43
44#define IMX_CS1_PHYS 0x12000000
45#define IMX_CS1_SIZE 0x01000000
46#define IMX_CS1_VIRT 0xea000000
47
48#define IMX_CS2_PHYS 0x13000000
49#define IMX_CS2_SIZE 0x01000000
50#define IMX_CS2_VIRT 0xeb000000
51
52#define IMX_CS3_PHYS 0x14000000
53#define IMX_CS3_SIZE 0x01000000
54#define IMX_CS3_VIRT 0xec000000
55
56#define IMX_CS4_PHYS 0x15000000
57#define IMX_CS4_SIZE 0x01000000
58#define IMX_CS4_VIRT 0xed000000
59
60#define IMX_CS5_PHYS 0x16000000
61#define IMX_CS5_SIZE 0x01000000
62#define IMX_CS5_VIRT 0xee000000
63
64#define IMX_FB_VIRT 0xF1000000
65#define IMX_FB_SIZE (256*1024)
66
67/* macro to get at IO space when running virtually */
68#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
69
70#ifndef __ASSEMBLY__
71/*
72 * Handy routine to set GPIO functions
73 */
74extern void imx_gpio_mode( int gpio_mode );
75
76#endif
77
78#define MAXIRQNUM 62
79#define MAXFIQNUM 62
80#define MAXSWINUM 62
81
82/*
83 * Use SDRAM for memory
84 */
85#define MEM_SIZE 0x01000000
86
87#ifdef CONFIG_ARCH_MX1ADS
88#include "mx1ads.h"
89#endif
90
91#endif
diff --git a/arch/arm/mach-imx/include/mach/imx-dma.h b/arch/arm/mach-imx/include/mach/imx-dma.h
new file mode 100644
index 000000000000..44d89c35539a
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx-dma.h
@@ -0,0 +1,94 @@
1/*
2 * linux/include/asm-arm/imxads/dma.h
3 *
4 * Copyright (C) 1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <asm/dma.h>
22
23#ifndef __ASM_ARCH_IMX_DMA_H
24#define __ASM_ARCH_IMX_DMA_H
25
26#define IMX_DMA_CHANNELS 11
27
28/*
29 * struct imx_dma_channel - i.MX specific DMA extension
30 * @name: name specified by DMA client
31 * @irq_handler: client callback for end of transfer
32 * @err_handler: client callback for error condition
33 * @data: clients context data for callbacks
34 * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
35 * @sg: pointer to the actual read/written chunk for scatter-gather emulation
36 * @sgbc: counter of processed bytes in the actual read/written chunk
37 * @resbytes: total residual number of bytes to transfer
38 * (it can be lower or same as sum of SG mapped chunk sizes)
39 * @sgcount: number of chunks to be read/written
40 *
41 * Structure is used for IMX DMA processing. It would be probably good
42 * @struct dma_struct in the future for external interfacing and use
43 * @struct imx_dma_channel only as extension to it.
44 */
45
46struct imx_dma_channel {
47 const char *name;
48 void (*irq_handler) (int, void *);
49 void (*err_handler) (int, void *, int errcode);
50 void *data;
51 dmamode_t dma_mode;
52 struct scatterlist *sg;
53 unsigned int sgbc;
54 unsigned int sgcount;
55 unsigned int resbytes;
56 int dma_num;
57};
58
59extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
60
61#define IMX_DMA_ERR_BURST 1
62#define IMX_DMA_ERR_REQUEST 2
63#define IMX_DMA_ERR_TRANSFER 4
64#define IMX_DMA_ERR_BUFFER 8
65
66/* The type to distinguish channel numbers parameter from ordinal int type */
67typedef int imx_dmach_t;
68
69int
70imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
71 unsigned int dma_length, unsigned int dev_addr, dmamode_t dmamode);
72
73int
74imx_dma_setup_sg(imx_dmach_t dma_ch,
75 struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
76 unsigned int dev_addr, dmamode_t dmamode);
77
78int
79imx_dma_setup_handlers(imx_dmach_t dma_ch,
80 void (*irq_handler) (int, void *),
81 void (*err_handler) (int, void *, int), void *data);
82
83void imx_dma_enable(imx_dmach_t dma_ch);
84
85void imx_dma_disable(imx_dmach_t dma_ch);
86
87int imx_dma_request(imx_dmach_t dma_ch, const char *name);
88
89void imx_dma_free(imx_dmach_t dma_ch);
90
91imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio);
92
93
94#endif /* _ASM_ARCH_IMX_DMA_H */
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
new file mode 100644
index 000000000000..fb9de2733879
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx-regs.h
@@ -0,0 +1,482 @@
1#ifndef _IMX_REGS_H
2#define _IMX_REGS_H
3/* ------------------------------------------------------------------------
4 * Motorola IMX system registers
5 * ------------------------------------------------------------------------
6 *
7 */
8
9/*
10 * Register BASEs, based on OFFSETs
11 *
12 */
13#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
14#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
15#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
16#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
17#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
18#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
19#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
20#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
21#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
22#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
23#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
24#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
25#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
26#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
27#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
28#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
29#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
30#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
31#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
32#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
33#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
34#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
35#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
36#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
37#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
38#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
39#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
40#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
41
42/* PLL registers */
43#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
44#define CSCR_SPLL_RESTART (1<<22)
45#define CSCR_MPLL_RESTART (1<<21)
46#define CSCR_SYSTEM_SEL (1<<16)
47#define CSCR_BCLK_DIV (0xf<<10)
48#define CSCR_MPU_PRESC (1<<15)
49#define CSCR_SPEN (1<<1)
50#define CSCR_MPEN (1<<0)
51
52#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
53#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
54#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
55#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
56#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
57
58/*
59 * GPIO Module and I/O Multiplexer
60 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
61 */
62#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
63#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
64#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
65#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
66#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
67#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
68#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
69#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
70#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
71#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
72#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
73#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
74#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
75#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
76#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
77#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
78#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
79
80#define GPIO_PORT_MAX 3
81
82#define GPIO_PIN_MASK 0x1f
83#define GPIO_PORT_MASK (0x3 << 5)
84
85#define GPIO_PORT_SHIFT 5
86#define GPIO_PORTA (0<<5)
87#define GPIO_PORTB (1<<5)
88#define GPIO_PORTC (2<<5)
89#define GPIO_PORTD (3<<5)
90
91#define GPIO_OUT (1<<7)
92#define GPIO_IN (0<<7)
93#define GPIO_PUEN (1<<8)
94
95#define GPIO_PF (0<<9)
96#define GPIO_AF (1<<9)
97
98#define GPIO_OCR_SHIFT 10
99#define GPIO_OCR_MASK (3<<10)
100#define GPIO_AIN (0<<10)
101#define GPIO_BIN (1<<10)
102#define GPIO_CIN (2<<10)
103#define GPIO_DR (3<<10)
104
105#define GPIO_AOUT_SHIFT 12
106#define GPIO_AOUT_MASK (3<<12)
107#define GPIO_AOUT (0<<12)
108#define GPIO_AOUT_ISR (1<<12)
109#define GPIO_AOUT_0 (2<<12)
110#define GPIO_AOUT_1 (3<<12)
111
112#define GPIO_BOUT_SHIFT 14
113#define GPIO_BOUT_MASK (3<<14)
114#define GPIO_BOUT (0<<14)
115#define GPIO_BOUT_ISR (1<<14)
116#define GPIO_BOUT_0 (2<<14)
117#define GPIO_BOUT_1 (3<<14)
118
119#define GPIO_GIUS (1<<16)
120
121/* assignements for GPIO alternate/primary functions */
122
123/* FIXME: This list is not completed. The correct directions are
124 * missing on some (many) pins
125 */
126#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
127#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
128#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
129#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
130#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
131#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
132#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
133#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
134#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
135#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
136#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
137#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
138#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
139#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
140#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
141#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
142#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
143#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
144#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
145#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
146#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
147#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
148#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
149#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
150#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
151#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
152#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
153#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
154#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
155#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
156#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
157#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
158#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
159#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
160#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
161#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
162#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
163#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
164#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
165#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
166#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
167#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
168#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
169#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
170#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
171#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
172#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
173#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
174#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
175#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 )
176#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
177#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 )
178#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
179#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
180#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
181#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
182#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
183#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
184#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
185#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
186#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
187#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
188#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
189#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
190#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
191#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
192#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
193#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
194#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
195#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
196#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
197#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
198#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
199#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
200#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
201#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
202#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
203#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
204#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
205#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
206#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
207#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
208#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
209#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
210#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
211#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
212#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
213#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
214#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
215#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
216#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
217#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
218#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
219#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
220#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
221#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
222#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
223#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
224#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
225#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
226#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
227#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
228#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
229#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
230#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
231#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
232#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
233#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
234#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
235#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
236#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
237#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
238#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
239#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
240#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
241#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
242#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
243#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
244#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
245#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
246#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
247#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
248#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
249#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
250#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
251#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
252#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
253#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
254#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
255#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
256#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
257
258/*
259 * PWM controller
260 */
261#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */
262#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */
263#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */
264#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */
265
266#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */
267#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */
268#define PWMC_SWR (0x01<<16) /* Software Reset */
269#define PWMC_CLKSRC (0x01<<15) /* Clock Source */
270#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */
271#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */
272#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */
273#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */
274#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */
275#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
276#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */
277
278#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
279#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
280#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
281
282/*
283 * DMA Controller
284 */
285#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
286#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
287#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
288#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
289#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
290#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
291#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
292#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
293#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
294#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
295#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
296#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
297#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
298#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
299#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
300#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
301#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
302#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
303#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
304#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
305#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
306#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
307
308#define DCR_DRST (1<<1)
309#define DCR_DEN (1<<0)
310#define DBTOCR_EN (1<<15)
311#define DBTOCR_CNT(x) ((x) & 0x7fff )
312#define CNTR_CNT(x) ((x) & 0xffffff )
313#define CCR_DMOD_LINEAR ( 0x0 << 12 )
314#define CCR_DMOD_2D ( 0x1 << 12 )
315#define CCR_DMOD_FIFO ( 0x2 << 12 )
316#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
317#define CCR_SMOD_LINEAR ( 0x0 << 10 )
318#define CCR_SMOD_2D ( 0x1 << 10 )
319#define CCR_SMOD_FIFO ( 0x2 << 10 )
320#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
321#define CCR_MDIR_DEC (1<<9)
322#define CCR_MSEL_B (1<<8)
323#define CCR_DSIZ_32 ( 0x0 << 6 )
324#define CCR_DSIZ_8 ( 0x1 << 6 )
325#define CCR_DSIZ_16 ( 0x2 << 6 )
326#define CCR_SSIZ_32 ( 0x0 << 4 )
327#define CCR_SSIZ_8 ( 0x1 << 4 )
328#define CCR_SSIZ_16 ( 0x2 << 4 )
329#define CCR_REN (1<<3)
330#define CCR_RPT (1<<2)
331#define CCR_FRC (1<<1)
332#define CCR_CEN (1<<0)
333#define RTOR_EN (1<<15)
334#define RTOR_CLK (1<<14)
335#define RTOR_PSC (1<<13)
336
337/*
338 * Interrupt controller
339 */
340
341#define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00)
342#define INTCNTL_FIAD (1<<19)
343#define INTCNTL_NIAD (1<<20)
344
345#define IMX_NIMASK __REG(IMX_AITC_BASE+0x04)
346#define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08)
347#define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c)
348#define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10)
349#define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14)
350
351/*
352 * General purpose timers
353 */
354#define IMX_TCTL(x) __REG( 0x00 + (x))
355#define TCTL_SWR (1<<15)
356#define TCTL_FRR (1<<8)
357#define TCTL_CAP_RIS (1<<6)
358#define TCTL_CAP_FAL (2<<6)
359#define TCTL_CAP_RIS_FAL (3<<6)
360#define TCTL_OM (1<<5)
361#define TCTL_IRQEN (1<<4)
362#define TCTL_CLK_PCLK1 (1<<1)
363#define TCTL_CLK_PCLK1_16 (2<<1)
364#define TCTL_CLK_TIN (3<<1)
365#define TCTL_CLK_32 (4<<1)
366#define TCTL_TEN (1<<0)
367
368#define IMX_TPRER(x) __REG( 0x04 + (x))
369#define IMX_TCMP(x) __REG( 0x08 + (x))
370#define IMX_TCR(x) __REG( 0x0C + (x))
371#define IMX_TCN(x) __REG( 0x10 + (x))
372#define IMX_TSTAT(x) __REG( 0x14 + (x))
373#define TSTAT_CAPT (1<<1)
374#define TSTAT_COMP (1<<0)
375
376/*
377 * LCD Controller
378 */
379
380#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
381
382#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
383#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
384#define SIZE_YMAX(y) ( (y) & 0x1ff )
385
386#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
387#define VPW_VPW(x) ( (x) & 0x3ff )
388
389#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
390#define CPOS_CC1 (1<<31)
391#define CPOS_CC0 (1<<30)
392#define CPOS_OP (1<<28)
393#define CPOS_CXP(x) (((x) & 3ff) << 16)
394#define CPOS_CYP(y) ((y) & 0x1ff)
395
396#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
397#define LCWHB_BK_EN (1<<31)
398#define LCWHB_CW(w) (((w) & 0x1f) << 24)
399#define LCWHB_CH(h) (((h) & 0x1f) << 16)
400#define LCWHB_BD(x) ((x) & 0xff)
401
402#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
403#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
404#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
405#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
406
407#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
408#define PCR_TFT (1<<31)
409#define PCR_COLOR (1<<30)
410#define PCR_PBSIZ_1 (0<<28)
411#define PCR_PBSIZ_2 (1<<28)
412#define PCR_PBSIZ_4 (2<<28)
413#define PCR_PBSIZ_8 (3<<28)
414#define PCR_BPIX_1 (0<<25)
415#define PCR_BPIX_2 (1<<25)
416#define PCR_BPIX_4 (2<<25)
417#define PCR_BPIX_8 (3<<25)
418#define PCR_BPIX_12 (4<<25)
419#define PCR_BPIX_16 (4<<25)
420#define PCR_PIXPOL (1<<24)
421#define PCR_FLMPOL (1<<23)
422#define PCR_LPPOL (1<<22)
423#define PCR_CLKPOL (1<<21)
424#define PCR_OEPOL (1<<20)
425#define PCR_SCLKIDLE (1<<19)
426#define PCR_END_SEL (1<<18)
427#define PCR_END_BYTE_SWAP (1<<17)
428#define PCR_REV_VS (1<<16)
429#define PCR_ACD_SEL (1<<15)
430#define PCR_ACD(x) (((x) & 0x7f) << 8)
431#define PCR_SCLK_SEL (1<<7)
432#define PCR_SHARP (1<<6)
433#define PCR_PCD(x) ((x) & 0x3f)
434
435#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
436#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
437#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
438#define HCR_H_WAIT_2(x) ((x) & 0xff)
439
440#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
441#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
442#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
443#define VCR_V_WAIT_2(x) ((x) & 0xff)
444
445#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
446#define POS_POS(x) ((x) & 1f)
447
448#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
449#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
450#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
451#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
452#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
453#define LSCR1_GRAY1(x) (((x) & 0xf))
454
455#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
456#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
457#define PWMR_LDMSK (1<<15)
458#define PWMR_SCR1 (1<<10)
459#define PWMR_SCR0 (1<<9)
460#define PWMR_CC_EN (1<<8)
461#define PWMR_PW(x) ((x) & 0xff)
462
463#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
464#define DMACR_BURST (1<<31)
465#define DMACR_HM(x) (((x) & 0xf) << 16)
466#define DMACR_TM(x) ((x) &0xf)
467
468#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
469#define RMCR_LCDC_EN (1<<1)
470#define RMCR_SELF_REF (1<<0)
471
472#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
473#define LCDICR_INT_SYN (1<<2)
474#define LCDICR_INT_CON (1)
475
476#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
477#define LCDISR_UDR_ERR (1<<3)
478#define LCDISR_ERR_RES (1<<2)
479#define LCDISR_EOF (1<<1)
480#define LCDISR_BOF (1<<0)
481
482#endif // _IMX_REGS_H
diff --git a/arch/arm/mach-imx/include/mach/imx-uart.h b/arch/arm/mach-imx/include/mach/imx-uart.h
new file mode 100644
index 000000000000..d54eb1d48026
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx-uart.h
@@ -0,0 +1,12 @@
1#ifndef ASMARM_ARCH_UART_H
2#define ASMARM_ARCH_UART_H
3
4#define IMXUART_HAVE_RTSCTS (1<<0)
5
6struct imxuart_platform_data {
7 int (*init)(struct platform_device *pdev);
8 void (*exit)(struct platform_device *pdev);
9 unsigned int flags;
10};
11
12#endif
diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h
new file mode 100644
index 000000000000..3ed9ec8b9f00
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imxfb.h
@@ -0,0 +1,37 @@
1/*
2 * This structure describes the machine which we are running on.
3 */
4struct imxfb_mach_info {
5 u_long pixclock;
6
7 u_short xres;
8 u_short yres;
9
10 u_int nonstd;
11 u_char bpp;
12 u_char hsync_len;
13 u_char left_margin;
14 u_char right_margin;
15
16 u_char vsync_len;
17 u_char upper_margin;
18 u_char lower_margin;
19 u_char sync;
20
21 u_int cmap_greyscale:1,
22 cmap_inverse:1,
23 cmap_static:1,
24 unused:29;
25
26 u_int pcr;
27 u_int pwmr;
28 u_int lscr1;
29 u_int dmacr;
30
31 u_char * fixed_screen_cpu;
32 dma_addr_t fixed_screen_dma;
33
34 void (*lcd_power)(int);
35 void (*backlight_power)(int);
36};
37void set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info);
diff --git a/arch/arm/mach-imx/include/mach/io.h b/arch/arm/mach-imx/include/mach/io.h
new file mode 100644
index 000000000000..c50c5fa6fb81
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/io.h
@@ -0,0 +1,30 @@
1/*
2 * arch/arm/mach-imxads/include/mach/io.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H
22
23#include <mach/hardware.h>
24
25#define IO_SPACE_LIMIT 0xffffffff
26
27#define __io(a) ((void __iomem *)(a))
28#define __mem_pci(a) (a)
29
30#endif
diff --git a/arch/arm/mach-imx/include/mach/irqs.h b/arch/arm/mach-imx/include/mach/irqs.h
new file mode 100644
index 000000000000..eb8d5bd05d56
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/irqs.h
@@ -0,0 +1,116 @@
1/*
2 * arch/arm/mach-imxads/include/mach/irqs.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __ARM_IRQS_H__
23#define __ARM_IRQS_H__
24
25/* Use the imx definitions */
26#include <mach/hardware.h>
27
28/*
29 * IMX Interrupt numbers
30 *
31 */
32#define INT_SOFTINT 0
33#define CSI_INT 6
34#define DSPA_MAC_INT 7
35#define DSPA_INT 8
36#define COMP_INT 9
37#define MSHC_XINT 10
38#define GPIO_INT_PORTA 11
39#define GPIO_INT_PORTB 12
40#define GPIO_INT_PORTC 13
41#define LCDC_INT 14
42#define SIM_INT 15
43#define SIM_DATA_INT 16
44#define RTC_INT 17
45#define RTC_SAMINT 18
46#define UART2_MINT_PFERR 19
47#define UART2_MINT_RTS 20
48#define UART2_MINT_DTR 21
49#define UART2_MINT_UARTC 22
50#define UART2_MINT_TX 23
51#define UART2_MINT_RX 24
52#define UART1_MINT_PFERR 25
53#define UART1_MINT_RTS 26
54#define UART1_MINT_DTR 27
55#define UART1_MINT_UARTC 28
56#define UART1_MINT_TX 29
57#define UART1_MINT_RX 30
58#define VOICE_DAC_INT 31
59#define VOICE_ADC_INT 32
60#define PEN_DATA_INT 33
61#define PWM_INT 34
62#define SDHC_INT 35
63#define I2C_INT 39
64#define CSPI_INT 41
65#define SSI_TX_INT 42
66#define SSI_TX_ERR_INT 43
67#define SSI_RX_INT 44
68#define SSI_RX_ERR_INT 45
69#define TOUCH_INT 46
70#define USBD_INT0 47
71#define USBD_INT1 48
72#define USBD_INT2 49
73#define USBD_INT3 50
74#define USBD_INT4 51
75#define USBD_INT5 52
76#define USBD_INT6 53
77#define BTSYS_INT 55
78#define BTTIM_INT 56
79#define BTWUI_INT 57
80#define TIM2_INT 58
81#define TIM1_INT 59
82#define DMA_ERR 60
83#define DMA_INT 61
84#define GPIO_INT_PORTD 62
85
86#define IMX_IRQS (64)
87
88/* note: the IMX has four gpio ports (A-D), but only
89 * the following pins are connected to the outside
90 * world:
91 *
92 * PORT A: bits 0-31
93 * PORT B: bits 8-31
94 * PORT C: bits 3-17
95 * PORT D: bits 6-31
96 *
97 * We map these interrupts straight on. As a result we have
98 * several holes in the interrupt mapping. We do this for two
99 * reasons:
100 * - mapping the interrupts without holes would get
101 * far more complicated
102 * - Motorola could well decide to bring some processor
103 * with more pins connected
104 */
105
106#define IRQ_GPIOA(x) (IMX_IRQS + x)
107#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
108#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
109#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
110
111/* decode irq number to use with IMR(x), ISR(x) and friends */
112#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5)
113
114#define NR_IRQS (IRQ_GPIOD(32) + 1)
115#define IRQ_GPIO(x)
116#endif
diff --git a/arch/arm/mach-imx/include/mach/memory.h b/arch/arm/mach-imx/include/mach/memory.h
new file mode 100644
index 000000000000..5c453063c0ed
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/memory.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/mach-imx/include/mach/memory.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_MMU_H
22#define __ASM_ARCH_MMU_H
23
24#define PHYS_OFFSET UL(0x08000000)
25
26/*
27 * Virtual view <-> DMA view memory address translations
28 * virt_to_bus: Used to translate the virtual address to an
29 * address suitable to be passed to set_dma_addr
30 * bus_to_virt: Used to convert an address for DMA operations
31 * to an address that the kernel can use.
32 */
33#define __virt_to_bus(x) (x - PAGE_OFFSET + PHYS_OFFSET)
34#define __bus_to_virt(x) (x - PHYS_OFFSET + PAGE_OFFSET)
35
36#endif
diff --git a/arch/arm/mach-imx/include/mach/mmc.h b/arch/arm/mach-imx/include/mach/mmc.h
new file mode 100644
index 000000000000..4712f354dcca
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mmc.h
@@ -0,0 +1,15 @@
1#ifndef ASMARM_ARCH_MMC_H
2#define ASMARM_ARCH_MMC_H
3
4#include <linux/mmc/host.h>
5
6struct device;
7
8struct imxmmc_platform_data {
9 int (*card_present)(struct device *);
10 int (*get_ro)(struct device *);
11};
12
13extern void imx_set_mmc_info(struct imxmmc_platform_data *info);
14
15#endif
diff --git a/arch/arm/mach-imx/include/mach/mx1ads.h b/arch/arm/mach-imx/include/mach/mx1ads.h
new file mode 100644
index 000000000000..def05d510eb3
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/mx1ads.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/mach-imx/include/mach/mx1ads.h
3 *
4 * Copyright (C) 2004 Robert Schwebel, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#ifndef __ASM_ARCH_MX1ADS_H
23#define __ASM_ARCH_MX1ADS_H
24
25/* ------------------------------------------------------------------------ */
26/* Memory Map for the M9328MX1ADS (MX1ADS) Board */
27/* ------------------------------------------------------------------------ */
28
29#define MX1ADS_FLASH_PHYS 0x10000000
30#define MX1ADS_FLASH_SIZE (16*1024*1024)
31
32#define IMX_FB_PHYS (0x0C000000 - 0x40000)
33
34#define CLK32 32000
35
36#endif /* __ASM_ARCH_MX1ADS_H */
diff --git a/arch/arm/mach-imx/include/mach/spi_imx.h b/arch/arm/mach-imx/include/mach/spi_imx.h
new file mode 100644
index 000000000000..4186430feecf
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/spi_imx.h
@@ -0,0 +1,72 @@
1/*
2 * arch/arm/mach-imx/include/mach/spi_imx.h
3 *
4 * Copyright (C) 2006 SWAPP
5 * Andrea Paterniani <a.paterniani@swapp-eng.it>
6 *
7 * Initial version inspired by:
8 * linux-2.6.17-rc3-mm1/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef SPI_IMX_H_
26#define SPI_IMX_H_
27
28
29/*-------------------------------------------------------------------------*/
30/**
31 * struct spi_imx_master - device.platform_data for SPI controller devices.
32 * @num_chipselect: chipselects are used to distinguish individual
33 * SPI slaves, and are numbered from zero to num_chipselects - 1.
34 * each slave has a chipselect signal, but it's common that not
35 * every chipselect is connected to a slave.
36 * @enable_dma: if true enables DMA driven transfers.
37*/
38struct spi_imx_master {
39 u8 num_chipselect;
40 u8 enable_dma:1;
41};
42/*-------------------------------------------------------------------------*/
43
44
45/*-------------------------------------------------------------------------*/
46/**
47 * struct spi_imx_chip - spi_board_info.controller_data for SPI
48 * slave devices, copied to spi_device.controller_data.
49 * @enable_loopback : used for test purpouse to internally connect RX and TX
50 * sections.
51 * @enable_dma : enables dma transfer (provided that controller driver has
52 * dma enabled too).
53 * @ins_ss_pulse : enable /SS pulse insertion between SPI burst.
54 * @bclk_wait : number of bclk waits between each bits_per_word SPI burst.
55 * @cs_control : function pointer to board-specific function to assert/deassert
56 * I/O port to control HW generation of devices chip-select.
57*/
58struct spi_imx_chip {
59 u8 enable_loopback:1;
60 u8 enable_dma:1;
61 u8 ins_ss_pulse:1;
62 u16 bclk_wait:15;
63 void (*cs_control)(u32 control);
64};
65
66/* Chip-select state */
67#define SPI_CS_ASSERT (1 << 0)
68#define SPI_CS_DEASSERT (1 << 1)
69/*-------------------------------------------------------------------------*/
70
71
72#endif /* SPI_IMX_H_*/
diff --git a/arch/arm/mach-imx/include/mach/system.h b/arch/arm/mach-imx/include/mach/system.h
new file mode 100644
index 000000000000..adee7e51bab2
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/system.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/mach-imxads/include/mach/system.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24static void
25arch_idle(void)
26{
27 /*
28 * This should do all the clock switching
29 * and wait for interrupt tricks
30 */
31 cpu_do_idle();
32}
33
34static inline void
35arch_reset(char mode)
36{
37 cpu_reset(0);
38}
39
40#endif
diff --git a/arch/arm/mach-imx/include/mach/timex.h b/arch/arm/mach-imx/include/mach/timex.h
new file mode 100644
index 000000000000..e22ba789546c
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/timex.h
@@ -0,0 +1,26 @@
1/*
2 * linux/include/asm-arm/imx/timex.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_TIMEX_H
22#define __ASM_ARCH_TIMEX_H
23
24#define CLOCK_TICK_RATE (16000000)
25
26#endif
diff --git a/arch/arm/mach-imx/include/mach/uncompress.h b/arch/arm/mach-imx/include/mach/uncompress.h
new file mode 100644
index 000000000000..70523e67a8f6
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/uncompress.h
@@ -0,0 +1,71 @@
1/*
2 * arch/arm/mach-imxads/include/mach/uncompress.h
3 *
4 *
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) Shane Nay (shane@minirl.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
25
26#define UART1_BASE 0x206000
27#define UART2_BASE 0x207000
28#define USR2 0x98
29#define USR2_TXFE (1<<14)
30#define TXR 0x40
31#define UCR1 0x80
32#define UCR1_UARTEN 1
33
34/*
35 * The following code assumes the serial port has already been
36 * initialized by the bootloader. We search for the first enabled
37 * port in the most probable order. If you didn't setup a port in
38 * your bootloader then nothing will appear (which might be desired).
39 *
40 * This does not append a newline
41 */
42static void putc(int c)
43{
44 unsigned long serial_port;
45
46 do {
47 serial_port = UART1_BASE;
48 if ( UART(UCR1) & UCR1_UARTEN )
49 break;
50 serial_port = UART2_BASE;
51 if ( UART(UCR1) & UCR1_UARTEN )
52 break;
53 return;
54 } while(0);
55
56 while (!(UART(USR2) & USR2_TXFE))
57 barrier();
58
59 UART(TXR) = c;
60}
61
62static inline void flush(void)
63{
64}
65
66/*
67 * nothing to do
68 */
69#define arch_decomp_setup()
70
71#define arch_decomp_wdog()
diff --git a/arch/arm/mach-imx/include/mach/vmalloc.h b/arch/arm/mach-imx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..7d7cb0bde3e8
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-imx/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 21:12:42 -0500