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1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_HARDWARE_H__
21#define __ASM_ARCH_MXC_HARDWARE_H__
22
23#include <asm/sizes.h>
24
25#define addr_in_module(addr, mod) \
26 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
27
28#define IMX_IO_P2V_MODULE(addr, module) \
29 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
30 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
31
32/*
33 * This is rather complicated for humans and ugly to verify, but for a machine
34 * it's OK. Still more as it is usually only applied to constants. The upsides
35 * on using this approach are:
36 *
37 * - same mapping on all i.MX machines
38 * - works for assembler, too
39 * - no need to nurture #defines for virtual addresses
40 *
41 * The downside it, it's hard to verify (but I have a script for that).
42 *
43 * Obviously this needs to be injective for each SoC. In general it maps the
44 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
45 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
46 *
47 * It applies the following mappings for the different SoCs:
48 *
49 * mx1:
50 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
51 * mx21:
52 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
53 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
54 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
55 * mx25:
56 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
57 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
58 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
59 * mx27:
60 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
61 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
62 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
63 * mx31:
64 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
65 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
66 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
67 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
68 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
69 * mx35:
70 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
71 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
72 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
73 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
74 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
75 * mx50:
76 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
77 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
78 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
79 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
80 * mx51:
81 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
82 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
83 * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
84 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
85 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
86 * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000
87 * mx53:
88 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
89 * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000
90 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
91 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
92 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
93 * mx6q:
94 * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000
95 * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
96 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000
97 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
98 */
99#define IMX_IO_P2V(x) ( \
100 (((x) & 0x80000000) >> 7) | \
101 (0xf4000000 + \
102 (((x) & 0x50000000) >> 6) + \
103 (((x) & 0x0b000000) >> 4) + \
104 (((x) & 0x000fffff))))
105
106#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
107
108#include "mxc.h"
109
110#include "mx6q.h"
111#include "mx50.h"
112#include "mx51.h"
113#include "mx53.h"
114#include "mx3x.h"
115#include "mx31.h"
116#include "mx35.h"
117#include "mx2x.h"
118#include "mx21.h"
119#include "mx27.h"
120#include "mx1.h"
121#include "mx25.h"
122
123#define imx_map_entry(soc, name, _type) { \
124 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
125 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
126 .length = soc ## _ ## name ## _SIZE, \
127 .type = _type, \
128}
129
130/* There's a off-by-one betweem the gpio bank number and the gpiochip */
131/* range e.g. GPIO_1_5 is gpio 5 under linux */
132#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
133
134#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
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