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-rw-r--r--arch/arm/mach-imx/ehci-imx5.c171
1 files changed, 0 insertions, 171 deletions
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
deleted file mode 100644
index e49710b10c68..000000000000
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/platform_data/usb-ehci-mxc.h>
19
20#include "hardware.h"
21
22#define MXC_OTG_OFFSET 0
23#define MXC_H1_OFFSET 0x200
24#define MXC_H2_OFFSET 0x400
25
26/* USB_CTRL */
27#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
28#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
29#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
30#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
31#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
32
33/* USB_PHY_CTRL_FUNC */
34#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */
35#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
36#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */
37#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
38#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */
39
40/* USBH2CTRL */
41#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
42#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
43#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
44
45#define MXC_USBCMD_OFFSET 0x140
46
47/* USBCMD */
48#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
49
50int mx51_initialize_usb_hw(int port, unsigned int flags)
51{
52 unsigned int v;
53 void __iomem *usb_base;
54 void __iomem *usbotg_base;
55 void __iomem *usbother_base;
56 int ret = 0;
57
58 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
59 if (!usb_base) {
60 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
61 return -ENOMEM;
62 }
63
64 switch (port) {
65 case 0: /* OTG port */
66 usbotg_base = usb_base + MXC_OTG_OFFSET;
67 break;
68 case 1: /* Host 1 port */
69 usbotg_base = usb_base + MXC_H1_OFFSET;
70 break;
71 case 2: /* Host 2 port */
72 usbotg_base = usb_base + MXC_H2_OFFSET;
73 break;
74 default:
75 printk(KERN_ERR"%s no such port %d\n", __func__, port);
76 ret = -ENOENT;
77 goto error;
78 }
79 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
80
81 switch (port) {
82 case 0: /*OTG port */
83 if (flags & MXC_EHCI_INTERNAL_PHY) {
84 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
85
86 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
87 v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
88 else
89 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
90 if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
91 /* OC/USBPWR is used */
92 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
93 } else {
94 /* OC/USBPWR is not used */
95 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
96 }
97 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
98 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
99 else
100 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
101 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
102
103 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
104 if (flags & MXC_EHCI_WAKEUP_ENABLED)
105 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
106 else
107 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
108 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
109 v &= ~MXC_OTG_UCTRL_OPM_BIT;
110 else
111 v |= MXC_OTG_UCTRL_OPM_BIT;
112 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
113 }
114 break;
115 case 1: /* Host 1 */
116 /*Host ULPI */
117 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
118 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
119 /* HOST1 wakeup/ULPI intr enable */
120 v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
121 } else {
122 /* HOST1 wakeup/ULPI intr disable */
123 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
124 }
125
126 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
127 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
128 else
129 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
130 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
131
132 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
133 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
134 v |= MXC_H1_OC_POL_BIT;
135 else
136 v &= ~MXC_H1_OC_POL_BIT;
137 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
138 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
139 else
140 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
141 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
142
143 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
144 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
145 /* Interrupt Threshold Control:Immediate (no threshold) */
146 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
147 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
148 break;
149 case 2: /* Host 2 ULPI */
150 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
151 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
152 /* HOST1 wakeup/ULPI intr enable */
153 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
154 } else {
155 /* HOST1 wakeup/ULPI intr disable */
156 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
157 }
158
159 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
160 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
161 else
162 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
163 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
164 break;
165 }
166
167error:
168 iounmap(usb_base);
169 return ret;
170}
171
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