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Diffstat (limited to 'arch/arm/mach-imx/dma-v1.c')
-rw-r--r--arch/arm/mach-imx/dma-v1.c25
1 files changed, 3 insertions, 22 deletions
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index f8aa5be0eb15..42afc29a7da8 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -476,7 +476,6 @@ void imx_dma_enable(int channel)
476 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN | 476 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
477 CCR_ACRPT, DMA_CCR(channel)); 477 CCR_ACRPT, DMA_CCR(channel));
478 478
479#ifdef CONFIG_ARCH_MX2
480 if ((cpu_is_mx21() || cpu_is_mx27()) && 479 if ((cpu_is_mx21() || cpu_is_mx27()) &&
481 imxdma->sg && imx_dma_hw_chain(imxdma)) { 480 imxdma->sg && imx_dma_hw_chain(imxdma)) {
482 imxdma->sg = sg_next(imxdma->sg); 481 imxdma->sg = sg_next(imxdma->sg);
@@ -488,7 +487,6 @@ void imx_dma_enable(int channel)
488 DMA_CCR(channel)); 487 DMA_CCR(channel));
489 } 488 }
490 } 489 }
491#endif
492 imxdma->in_use = 1; 490 imxdma->in_use = 1;
493 491
494 local_irq_restore(flags); 492 local_irq_restore(flags);
@@ -519,7 +517,6 @@ void imx_dma_disable(int channel)
519} 517}
520EXPORT_SYMBOL(imx_dma_disable); 518EXPORT_SYMBOL(imx_dma_disable);
521 519
522#ifdef CONFIG_ARCH_MX2
523static void imx_dma_watchdog(unsigned long chno) 520static void imx_dma_watchdog(unsigned long chno)
524{ 521{
525 struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; 522 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
@@ -531,7 +528,6 @@ static void imx_dma_watchdog(unsigned long chno)
531 if (imxdma->err_handler) 528 if (imxdma->err_handler)
532 imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT); 529 imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
533} 530}
534#endif
535 531
536static irqreturn_t dma_err_handler(int irq, void *dev_id) 532static irqreturn_t dma_err_handler(int irq, void *dev_id)
537{ 533{
@@ -655,10 +651,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
655{ 651{
656 int i, disr; 652 int i, disr;
657 653
658#ifdef CONFIG_ARCH_MX2
659 if (cpu_is_mx21() || cpu_is_mx27()) 654 if (cpu_is_mx21() || cpu_is_mx27())
660 dma_err_handler(irq, dev_id); 655 dma_err_handler(irq, dev_id);
661#endif
662 656
663 disr = imx_dmav1_readl(DMA_DISR); 657 disr = imx_dmav1_readl(DMA_DISR);
664 658
@@ -704,7 +698,6 @@ int imx_dma_request(int channel, const char *name)
704 imxdma->name = name; 698 imxdma->name = name;
705 local_irq_restore(flags); /* request_irq() can block */ 699 local_irq_restore(flags); /* request_irq() can block */
706 700
707#ifdef CONFIG_ARCH_MX2
708 if (cpu_is_mx21() || cpu_is_mx27()) { 701 if (cpu_is_mx21() || cpu_is_mx27()) {
709 ret = request_irq(MX2x_INT_DMACH0 + channel, 702 ret = request_irq(MX2x_INT_DMACH0 + channel,
710 dma_irq_handler, 0, "DMA", NULL); 703 dma_irq_handler, 0, "DMA", NULL);
@@ -718,7 +711,6 @@ int imx_dma_request(int channel, const char *name)
718 imxdma->watchdog.function = &imx_dma_watchdog; 711 imxdma->watchdog.function = &imx_dma_watchdog;
719 imxdma->watchdog.data = channel; 712 imxdma->watchdog.data = channel;
720 } 713 }
721#endif
722 714
723 return ret; 715 return ret;
724} 716}
@@ -745,10 +737,8 @@ void imx_dma_free(int channel)
745 imx_dma_disable(channel); 737 imx_dma_disable(channel);
746 imxdma->name = NULL; 738 imxdma->name = NULL;
747 739
748#ifdef CONFIG_ARCH_MX2
749 if (cpu_is_mx21() || cpu_is_mx27()) 740 if (cpu_is_mx21() || cpu_is_mx27())
750 free_irq(MX2x_INT_DMACH0 + channel, NULL); 741 free_irq(MX2x_INT_DMACH0 + channel, NULL);
751#endif
752 742
753 local_irq_restore(flags); 743 local_irq_restore(flags);
754} 744}
@@ -804,21 +794,13 @@ static int __init imx_dma_init(void)
804 int ret = 0; 794 int ret = 0;
805 int i; 795 int i;
806 796
807#ifdef CONFIG_ARCH_MX1
808 if (cpu_is_mx1()) 797 if (cpu_is_mx1())
809 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); 798 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
810 else 799 else if (cpu_is_mx21())
811#endif
812#ifdef CONFIG_MACH_MX21
813 if (cpu_is_mx21())
814 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); 800 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
815 else 801 else if (cpu_is_mx27())
816#endif
817#ifdef CONFIG_MACH_MX27
818 if (cpu_is_mx27())
819 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); 802 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
820 else 803 else
821#endif
822 return 0; 804 return 0;
823 805
824 dma_clk = clk_get(NULL, "dma"); 806 dma_clk = clk_get(NULL, "dma");
@@ -829,7 +811,6 @@ static int __init imx_dma_init(void)
829 /* reset DMA module */ 811 /* reset DMA module */
830 imx_dmav1_writel(DCR_DRST, DMA_DCR); 812 imx_dmav1_writel(DCR_DRST, DMA_DCR);
831 813
832#ifdef CONFIG_ARCH_MX1
833 if (cpu_is_mx1()) { 814 if (cpu_is_mx1()) {
834 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL); 815 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
835 if (ret) { 816 if (ret) {
@@ -844,7 +825,7 @@ static int __init imx_dma_init(void)
844 return ret; 825 return ret;
845 } 826 }
846 } 827 }
847#endif 828
848 /* enable DMA module */ 829 /* enable DMA module */
849 imx_dmav1_writel(DCR_DEN, DMA_DCR); 830 imx_dmav1_writel(DCR_DEN, DMA_DCR);
850 831