diff options
Diffstat (limited to 'arch/arm/mach-imx/cpu-imx31.c')
-rw-r--r-- | arch/arm/mach-imx/cpu-imx31.c | 49 |
1 files changed, 27 insertions, 22 deletions
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c index a3780700a882..3f2345f0cdaf 100644 --- a/arch/arm/mach-imx/cpu-imx31.c +++ b/arch/arm/mach-imx/cpu-imx31.c | |||
@@ -13,45 +13,50 @@ | |||
13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
15 | #include <mach/iim.h> | 15 | #include <mach/iim.h> |
16 | #include <mach/common.h> | ||
16 | 17 | ||
17 | unsigned int mx31_cpu_rev; | 18 | static int mx31_cpu_rev = -1; |
18 | EXPORT_SYMBOL(mx31_cpu_rev); | ||
19 | 19 | ||
20 | static struct { | 20 | static struct { |
21 | u8 srev; | 21 | u8 srev; |
22 | const char *name; | 22 | const char *name; |
23 | const char *v; | ||
24 | unsigned int rev; | 23 | unsigned int rev; |
25 | } mx31_cpu_type[] __initdata = { | 24 | } mx31_cpu_type[] = { |
26 | { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 }, | 25 | { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 }, |
27 | { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, | 26 | { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 }, |
28 | { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, | 27 | { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 }, |
29 | { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, | 28 | { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 }, |
30 | { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, | 29 | { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 }, |
31 | { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, | 30 | { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 }, |
32 | { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, | 31 | { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 }, |
33 | { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, | 32 | { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 }, |
34 | { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, | 33 | { .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 }, |
35 | }; | 34 | }; |
36 | 35 | ||
37 | void __init mx31_read_cpu_rev(void) | 36 | static int mx31_read_cpu_rev(void) |
38 | { | 37 | { |
39 | u32 i, srev; | 38 | u32 i, srev; |
40 | 39 | ||
41 | /* read SREV register from IIM module */ | 40 | /* read SREV register from IIM module */ |
42 | srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); | 41 | srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); |
42 | srev &= 0xff; | ||
43 | 43 | ||
44 | for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) | 44 | for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) |
45 | if (srev == mx31_cpu_type[i].srev) { | 45 | if (srev == mx31_cpu_type[i].srev) { |
46 | printk(KERN_INFO | 46 | imx_print_silicon_rev(mx31_cpu_type[i].name, |
47 | "CPU identified as %s, silicon rev %s\n", | 47 | mx31_cpu_type[i].rev); |
48 | mx31_cpu_type[i].name, mx31_cpu_type[i].v); | 48 | return mx31_cpu_type[i].rev; |
49 | |||
50 | mx31_cpu_rev = mx31_cpu_type[i].rev; | ||
51 | return; | ||
52 | } | 49 | } |
53 | 50 | ||
54 | mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; | 51 | imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN); |
52 | return IMX_CHIP_REVISION_UNKNOWN; | ||
53 | } | ||
54 | |||
55 | int mx31_revision(void) | ||
56 | { | ||
57 | if (mx31_cpu_rev == -1) | ||
58 | mx31_cpu_rev = mx31_read_cpu_rev(); | ||
55 | 59 | ||
56 | printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); | 60 | return mx31_cpu_rev; |
57 | } | 61 | } |
62 | EXPORT_SYMBOL(mx31_revision); | ||