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-rw-r--r--arch/arm/mach-imx/clk-pllv3.c419
1 files changed, 419 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
new file mode 100644
index 000000000000..36aac947bce1
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -0,0 +1,419 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/clk.h>
14#include <linux/clk-provider.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/jiffies.h>
18#include <linux/err.h>
19#include "clk.h"
20
21#define PLL_NUM_OFFSET 0x10
22#define PLL_DENOM_OFFSET 0x20
23
24#define BM_PLL_POWER (0x1 << 12)
25#define BM_PLL_ENABLE (0x1 << 13)
26#define BM_PLL_BYPASS (0x1 << 16)
27#define BM_PLL_LOCK (0x1 << 31)
28
29/**
30 * struct clk_pllv3 - IMX PLL clock version 3
31 * @clk_hw: clock source
32 * @base: base address of PLL registers
33 * @powerup_set: set POWER bit to power up the PLL
34 * @gate_mask: mask of gate bits
35 * @div_mask: mask of divider bits
36 *
37 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
38 * is actually a multiplier, and always sits at bit 0.
39 */
40struct clk_pllv3 {
41 struct clk_hw hw;
42 void __iomem *base;
43 bool powerup_set;
44 u32 gate_mask;
45 u32 div_mask;
46};
47
48#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
49
50static int clk_pllv3_prepare(struct clk_hw *hw)
51{
52 struct clk_pllv3 *pll = to_clk_pllv3(hw);
53 unsigned long timeout = jiffies + msecs_to_jiffies(10);
54 u32 val;
55
56 val = readl_relaxed(pll->base);
57 val &= ~BM_PLL_BYPASS;
58 if (pll->powerup_set)
59 val |= BM_PLL_POWER;
60 else
61 val &= ~BM_PLL_POWER;
62 writel_relaxed(val, pll->base);
63
64 /* Wait for PLL to lock */
65 while (!(readl_relaxed(pll->base) & BM_PLL_LOCK))
66 if (time_after(jiffies, timeout))
67 return -ETIMEDOUT;
68
69 return 0;
70}
71
72static void clk_pllv3_unprepare(struct clk_hw *hw)
73{
74 struct clk_pllv3 *pll = to_clk_pllv3(hw);
75 u32 val;
76
77 val = readl_relaxed(pll->base);
78 val |= BM_PLL_BYPASS;
79 if (pll->powerup_set)
80 val &= ~BM_PLL_POWER;
81 else
82 val |= BM_PLL_POWER;
83 writel_relaxed(val, pll->base);
84}
85
86static int clk_pllv3_enable(struct clk_hw *hw)
87{
88 struct clk_pllv3 *pll = to_clk_pllv3(hw);
89 u32 val;
90
91 val = readl_relaxed(pll->base);
92 val |= pll->gate_mask;
93 writel_relaxed(val, pll->base);
94
95 return 0;
96}
97
98static void clk_pllv3_disable(struct clk_hw *hw)
99{
100 struct clk_pllv3 *pll = to_clk_pllv3(hw);
101 u32 val;
102
103 val = readl_relaxed(pll->base);
104 val &= ~pll->gate_mask;
105 writel_relaxed(val, pll->base);
106}
107
108static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
109 unsigned long parent_rate)
110{
111 struct clk_pllv3 *pll = to_clk_pllv3(hw);
112 u32 div = readl_relaxed(pll->base) & pll->div_mask;
113
114 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
115}
116
117static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
118 unsigned long *prate)
119{
120 unsigned long parent_rate = *prate;
121
122 return (rate >= parent_rate * 22) ? parent_rate * 22 :
123 parent_rate * 20;
124}
125
126static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
127 unsigned long parent_rate)
128{
129 struct clk_pllv3 *pll = to_clk_pllv3(hw);
130 u32 val, div;
131
132 if (rate == parent_rate * 22)
133 div = 1;
134 else if (rate == parent_rate * 20)
135 div = 0;
136 else
137 return -EINVAL;
138
139 val = readl_relaxed(pll->base);
140 val &= ~pll->div_mask;
141 val |= div;
142 writel_relaxed(val, pll->base);
143
144 return 0;
145}
146
147static const struct clk_ops clk_pllv3_ops = {
148 .prepare = clk_pllv3_prepare,
149 .unprepare = clk_pllv3_unprepare,
150 .enable = clk_pllv3_enable,
151 .disable = clk_pllv3_disable,
152 .recalc_rate = clk_pllv3_recalc_rate,
153 .round_rate = clk_pllv3_round_rate,
154 .set_rate = clk_pllv3_set_rate,
155};
156
157static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
158 unsigned long parent_rate)
159{
160 struct clk_pllv3 *pll = to_clk_pllv3(hw);
161 u32 div = readl_relaxed(pll->base) & pll->div_mask;
162
163 return parent_rate * div / 2;
164}
165
166static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
167 unsigned long *prate)
168{
169 unsigned long parent_rate = *prate;
170 unsigned long min_rate = parent_rate * 54 / 2;
171 unsigned long max_rate = parent_rate * 108 / 2;
172 u32 div;
173
174 if (rate > max_rate)
175 rate = max_rate;
176 else if (rate < min_rate)
177 rate = min_rate;
178 div = rate * 2 / parent_rate;
179
180 return parent_rate * div / 2;
181}
182
183static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
184 unsigned long parent_rate)
185{
186 struct clk_pllv3 *pll = to_clk_pllv3(hw);
187 unsigned long min_rate = parent_rate * 54 / 2;
188 unsigned long max_rate = parent_rate * 108 / 2;
189 u32 val, div;
190
191 if (rate < min_rate || rate > max_rate)
192 return -EINVAL;
193
194 div = rate * 2 / parent_rate;
195 val = readl_relaxed(pll->base);
196 val &= ~pll->div_mask;
197 val |= div;
198 writel_relaxed(val, pll->base);
199
200 return 0;
201}
202
203static const struct clk_ops clk_pllv3_sys_ops = {
204 .prepare = clk_pllv3_prepare,
205 .unprepare = clk_pllv3_unprepare,
206 .enable = clk_pllv3_enable,
207 .disable = clk_pllv3_disable,
208 .recalc_rate = clk_pllv3_sys_recalc_rate,
209 .round_rate = clk_pllv3_sys_round_rate,
210 .set_rate = clk_pllv3_sys_set_rate,
211};
212
213static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
214 unsigned long parent_rate)
215{
216 struct clk_pllv3 *pll = to_clk_pllv3(hw);
217 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
218 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
219 u32 div = readl_relaxed(pll->base) & pll->div_mask;
220
221 return (parent_rate * div) + ((parent_rate / mfd) * mfn);
222}
223
224static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
225 unsigned long *prate)
226{
227 unsigned long parent_rate = *prate;
228 unsigned long min_rate = parent_rate * 27;
229 unsigned long max_rate = parent_rate * 54;
230 u32 div;
231 u32 mfn, mfd = 1000000;
232 s64 temp64;
233
234 if (rate > max_rate)
235 rate = max_rate;
236 else if (rate < min_rate)
237 rate = min_rate;
238
239 div = rate / parent_rate;
240 temp64 = (u64) (rate - div * parent_rate);
241 temp64 *= mfd;
242 do_div(temp64, parent_rate);
243 mfn = temp64;
244
245 return parent_rate * div + parent_rate / mfd * mfn;
246}
247
248static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
249 unsigned long parent_rate)
250{
251 struct clk_pllv3 *pll = to_clk_pllv3(hw);
252 unsigned long min_rate = parent_rate * 27;
253 unsigned long max_rate = parent_rate * 54;
254 u32 val, div;
255 u32 mfn, mfd = 1000000;
256 s64 temp64;
257
258 if (rate < min_rate || rate > max_rate)
259 return -EINVAL;
260
261 div = rate / parent_rate;
262 temp64 = (u64) (rate - div * parent_rate);
263 temp64 *= mfd;
264 do_div(temp64, parent_rate);
265 mfn = temp64;
266
267 val = readl_relaxed(pll->base);
268 val &= ~pll->div_mask;
269 val |= div;
270 writel_relaxed(val, pll->base);
271 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
272 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
273
274 return 0;
275}
276
277static const struct clk_ops clk_pllv3_av_ops = {
278 .prepare = clk_pllv3_prepare,
279 .unprepare = clk_pllv3_unprepare,
280 .enable = clk_pllv3_enable,
281 .disable = clk_pllv3_disable,
282 .recalc_rate = clk_pllv3_av_recalc_rate,
283 .round_rate = clk_pllv3_av_round_rate,
284 .set_rate = clk_pllv3_av_set_rate,
285};
286
287static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
288 unsigned long parent_rate)
289{
290 struct clk_pllv3 *pll = to_clk_pllv3(hw);
291 u32 div = readl_relaxed(pll->base) & pll->div_mask;
292
293 switch (div) {
294 case 0:
295 return 25000000;
296 case 1:
297 return 50000000;
298 case 2:
299 return 100000000;
300 case 3:
301 return 125000000;
302 }
303
304 return 0;
305}
306
307static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
308 unsigned long *prate)
309{
310 if (rate >= 125000000)
311 rate = 125000000;
312 else if (rate >= 100000000)
313 rate = 100000000;
314 else if (rate >= 50000000)
315 rate = 50000000;
316 else
317 rate = 25000000;
318 return rate;
319}
320
321static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
322 unsigned long parent_rate)
323{
324 struct clk_pllv3 *pll = to_clk_pllv3(hw);
325 u32 val, div;
326
327 switch (rate) {
328 case 25000000:
329 div = 0;
330 break;
331 case 50000000:
332 div = 1;
333 break;
334 case 100000000:
335 div = 2;
336 break;
337 case 125000000:
338 div = 3;
339 break;
340 default:
341 return -EINVAL;
342 }
343
344 val = readl_relaxed(pll->base);
345 val &= ~pll->div_mask;
346 val |= div;
347 writel_relaxed(val, pll->base);
348
349 return 0;
350}
351
352static const struct clk_ops clk_pllv3_enet_ops = {
353 .prepare = clk_pllv3_prepare,
354 .unprepare = clk_pllv3_unprepare,
355 .enable = clk_pllv3_enable,
356 .disable = clk_pllv3_disable,
357 .recalc_rate = clk_pllv3_enet_recalc_rate,
358 .round_rate = clk_pllv3_enet_round_rate,
359 .set_rate = clk_pllv3_enet_set_rate,
360};
361
362static const struct clk_ops clk_pllv3_mlb_ops = {
363 .prepare = clk_pllv3_prepare,
364 .unprepare = clk_pllv3_unprepare,
365 .enable = clk_pllv3_enable,
366 .disable = clk_pllv3_disable,
367};
368
369struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
370 const char *parent_name, void __iomem *base,
371 u32 gate_mask, u32 div_mask)
372{
373 struct clk_pllv3 *pll;
374 const struct clk_ops *ops;
375 struct clk *clk;
376 struct clk_init_data init;
377
378 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
379 if (!pll)
380 return ERR_PTR(-ENOMEM);
381
382 switch (type) {
383 case IMX_PLLV3_SYS:
384 ops = &clk_pllv3_sys_ops;
385 break;
386 case IMX_PLLV3_USB:
387 ops = &clk_pllv3_ops;
388 pll->powerup_set = true;
389 break;
390 case IMX_PLLV3_AV:
391 ops = &clk_pllv3_av_ops;
392 break;
393 case IMX_PLLV3_ENET:
394 ops = &clk_pllv3_enet_ops;
395 break;
396 case IMX_PLLV3_MLB:
397 ops = &clk_pllv3_mlb_ops;
398 break;
399 default:
400 ops = &clk_pllv3_ops;
401 }
402 pll->base = base;
403 pll->gate_mask = gate_mask;
404 pll->div_mask = div_mask;
405
406 init.name = name;
407 init.ops = ops;
408 init.flags = 0;
409 init.parent_names = &parent_name;
410 init.num_parents = 1;
411
412 pll->hw.init = &init;
413
414 clk = clk_register(NULL, &pll->hw);
415 if (IS_ERR(clk))
416 kfree(pll);
417
418 return clk;
419}
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 16:48:49 -0500