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-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c256
1 files changed, 114 insertions, 142 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 21d2b111c83d..72d65214223e 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -18,11 +18,54 @@
18#include <linux/of_irq.h> 18#include <linux/of_irq.h>
19#include <dt-bindings/clock/imx5-clock.h> 19#include <dt-bindings/clock/imx5-clock.h>
20 20
21#include "crm-regs-imx5.h"
22#include "clk.h" 21#include "clk.h"
23#include "common.h" 22#include "common.h"
24#include "hardware.h" 23#include "hardware.h"
25 24
25#define MX51_DPLL1_BASE 0x83f80000
26#define MX51_DPLL2_BASE 0x83f84000
27#define MX51_DPLL3_BASE 0x83f88000
28
29#define MX53_DPLL1_BASE 0x63f80000
30#define MX53_DPLL2_BASE 0x63f84000
31#define MX53_DPLL3_BASE 0x63f88000
32#define MX53_DPLL4_BASE 0x63f8c000
33
34#define MXC_CCM_CCR (ccm_base + 0x00)
35#define MXC_CCM_CCDR (ccm_base + 0x04)
36#define MXC_CCM_CSR (ccm_base + 0x08)
37#define MXC_CCM_CCSR (ccm_base + 0x0c)
38#define MXC_CCM_CACRR (ccm_base + 0x10)
39#define MXC_CCM_CBCDR (ccm_base + 0x14)
40#define MXC_CCM_CBCMR (ccm_base + 0x18)
41#define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
42#define MXC_CCM_CSCMR2 (ccm_base + 0x20)
43#define MXC_CCM_CSCDR1 (ccm_base + 0x24)
44#define MXC_CCM_CS1CDR (ccm_base + 0x28)
45#define MXC_CCM_CS2CDR (ccm_base + 0x2c)
46#define MXC_CCM_CDCDR (ccm_base + 0x30)
47#define MXC_CCM_CHSCDR (ccm_base + 0x34)
48#define MXC_CCM_CSCDR2 (ccm_base + 0x38)
49#define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
50#define MXC_CCM_CSCDR4 (ccm_base + 0x40)
51#define MXC_CCM_CWDR (ccm_base + 0x44)
52#define MXC_CCM_CDHIPR (ccm_base + 0x48)
53#define MXC_CCM_CDCR (ccm_base + 0x4c)
54#define MXC_CCM_CTOR (ccm_base + 0x50)
55#define MXC_CCM_CLPCR (ccm_base + 0x54)
56#define MXC_CCM_CISR (ccm_base + 0x58)
57#define MXC_CCM_CIMR (ccm_base + 0x5c)
58#define MXC_CCM_CCOSR (ccm_base + 0x60)
59#define MXC_CCM_CGPR (ccm_base + 0x64)
60#define MXC_CCM_CCGR0 (ccm_base + 0x68)
61#define MXC_CCM_CCGR1 (ccm_base + 0x6c)
62#define MXC_CCM_CCGR2 (ccm_base + 0x70)
63#define MXC_CCM_CCGR3 (ccm_base + 0x74)
64#define MXC_CCM_CCGR4 (ccm_base + 0x78)
65#define MXC_CCM_CCGR5 (ccm_base + 0x7c)
66#define MXC_CCM_CCGR6 (ccm_base + 0x80)
67#define MXC_CCM_CCGR7 (ccm_base + 0x84)
68
26/* Low-power Audio Playback Mode clock */ 69/* Low-power Audio Playback Mode clock */
27static const char *lp_apm_sel[] = { "osc", }; 70static const char *lp_apm_sel[] = { "osc", };
28 71
@@ -86,17 +129,15 @@ static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
86static struct clk *clk[IMX5_CLK_END]; 129static struct clk *clk[IMX5_CLK_END];
87static struct clk_onecell_data clk_data; 130static struct clk_onecell_data clk_data;
88 131
89static void __init mx5_clocks_common_init(unsigned long rate_ckil, 132static void __init mx5_clocks_common_init(void __iomem *ccm_base)
90 unsigned long rate_osc, unsigned long rate_ckih1,
91 unsigned long rate_ckih2)
92{ 133{
93 int i; 134 imx5_pm_set_ccm_base(ccm_base);
94 135
95 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 136 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
96 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil); 137 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
97 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc); 138 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
98 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); 139 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
99 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); 140 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
100 141
101 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, 142 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
102 periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); 143 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
@@ -244,58 +285,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
244 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); 285 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
245 clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); 286 clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
246 287
247 for (i = 0; i < ARRAY_SIZE(clk); i++)
248 if (IS_ERR(clk[i]))
249 pr_err("i.MX5 clk %d: register failed with %ld\n",
250 i, PTR_ERR(clk[i]));
251
252 clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
253 clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
254 clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
255 clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
256 clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
257 clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
258 clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
259 clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
260 clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
261 clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
262 clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
263 clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
264 clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
265 clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
266 clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
267 clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
268 clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
269 clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
270 clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
271 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
272 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
273 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
274 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
275 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
276 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
277 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
278 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
279 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
280 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
281 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
282 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
283 clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
284 clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
285 clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
286 clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
287 clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
288 clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0"); 288 clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
289 clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
290 clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
291 clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
292 clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
293 clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
294 clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); 289 clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
295 clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
296 clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
297 clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
298 clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
299 290
300 /* Set SDHC parents to be PLL2 */ 291 /* Set SDHC parents to be PLL2 */
301 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); 292 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
@@ -322,12 +313,26 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
322 313
323static void __init mx50_clocks_init(struct device_node *np) 314static void __init mx50_clocks_init(struct device_node *np)
324{ 315{
316 void __iomem *ccm_base;
317 void __iomem *pll_base;
325 unsigned long r; 318 unsigned long r;
326 int i;
327 319
328 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); 320 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
329 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); 321 WARN_ON(!pll_base);
330 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); 322 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
323
324 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
325 WARN_ON(!pll_base);
326 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
327
328 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
329 WARN_ON(!pll_base);
330 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
331
332 ccm_base = of_iomap(np, 0);
333 WARN_ON(!ccm_base);
334
335 mx5_clocks_common_init(ccm_base);
331 336
332 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, 337 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
333 lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); 338 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -349,17 +354,12 @@ static void __init mx50_clocks_init(struct device_node *np)
349 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); 354 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
350 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); 355 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
351 356
352 for (i = 0; i < ARRAY_SIZE(clk); i++) 357 imx_check_clocks(clk, ARRAY_SIZE(clk));
353 if (IS_ERR(clk[i]))
354 pr_err("i.MX50 clk %d: register failed with %ld\n",
355 i, PTR_ERR(clk[i]));
356 358
357 clk_data.clks = clk; 359 clk_data.clks = clk;
358 clk_data.clk_num = ARRAY_SIZE(clk); 360 clk_data.clk_num = ARRAY_SIZE(clk);
359 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 361 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
360 362
361 mx5_clocks_common_init(0, 0, 0, 0);
362
363 /* set SDHC root clock to 200MHZ*/ 363 /* set SDHC root clock to 200MHZ*/
364 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); 364 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
365 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); 365 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@@ -370,21 +370,32 @@ static void __init mx50_clocks_init(struct device_node *np)
370 370
371 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); 371 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
372 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); 372 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
373
374 mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
375} 373}
376CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); 374CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
377 375
378int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, 376static void __init mx51_clocks_init(struct device_node *np)
379 unsigned long rate_ckih1, unsigned long rate_ckih2)
380{ 377{
381 int i; 378 void __iomem *ccm_base;
379 void __iomem *pll_base;
382 u32 val; 380 u32 val;
383 struct device_node *np;
384 381
385 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); 382 pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
386 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); 383 WARN_ON(!pll_base);
387 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE); 384 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
385
386 pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
387 WARN_ON(!pll_base);
388 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
389
390 pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
391 WARN_ON(!pll_base);
392 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
393
394 ccm_base = of_iomap(np, 0);
395 WARN_ON(!ccm_base);
396
397 mx5_clocks_common_init(ccm_base);
398
388 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, 399 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
389 lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); 400 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
390 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, 401 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
@@ -417,35 +428,12 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
417 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); 428 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
418 clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); 429 clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
419 430
420 for (i = 0; i < ARRAY_SIZE(clk); i++) 431 imx_check_clocks(clk, ARRAY_SIZE(clk));
421 if (IS_ERR(clk[i]))
422 pr_err("i.MX51 clk %d: register failed with %ld\n",
423 i, PTR_ERR(clk[i]));
424 432
425 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
426 clk_data.clks = clk; 433 clk_data.clks = clk;
427 clk_data.clk_num = ARRAY_SIZE(clk); 434 clk_data.clk_num = ARRAY_SIZE(clk);
428 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 435 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
429 436
430 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
431
432 clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
433 clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
434 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
435 clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
436 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
437 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
438 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
439 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
440 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
441 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
442 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
443 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
444 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
445 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
446 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
447 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
448
449 /* set the usboh3 parent to pll2_sw */ 437 /* set the usboh3 parent to pll2_sw */
450 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); 438 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
451 439
@@ -453,9 +441,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
453 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); 441 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
454 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); 442 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
455 443
456 /* System timer */
457 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
458
459 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); 444 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
460 imx_print_silicon_rev("i.MX51", mx51_revision()); 445 imx_print_silicon_rev("i.MX51", mx51_revision());
461 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); 446 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
@@ -474,25 +459,35 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
474 val = readl(MXC_CCM_CLPCR); 459 val = readl(MXC_CCM_CLPCR);
475 val |= 1 << 23; 460 val |= 1 << 23;
476 writel(val, MXC_CCM_CLPCR); 461 writel(val, MXC_CCM_CLPCR);
477
478 return 0;
479}
480
481static void __init mx51_clocks_init_dt(struct device_node *np)
482{
483 mx51_clocks_init(0, 0, 0, 0);
484} 462}
485CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); 463CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
486 464
487static void __init mx53_clocks_init(struct device_node *np) 465static void __init mx53_clocks_init(struct device_node *np)
488{ 466{
489 int i; 467 void __iomem *ccm_base;
468 void __iomem *pll_base;
490 unsigned long r; 469 unsigned long r;
491 470
492 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); 471 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
493 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); 472 WARN_ON(!pll_base);
494 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); 473 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
495 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); 474
475 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
476 WARN_ON(!pll_base);
477 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
478
479 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
480 WARN_ON(!pll_base);
481 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
482
483 pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
484 WARN_ON(!pll_base);
485 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base);
486
487 ccm_base = of_iomap(np, 0);
488 WARN_ON(!ccm_base);
489
490 mx5_clocks_common_init(ccm_base);
496 491
497 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, 492 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
498 lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); 493 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -543,33 +538,12 @@ static void __init mx53_clocks_init(struct device_node *np)
543 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, 538 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
544 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); 539 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
545 540
546 for (i = 0; i < ARRAY_SIZE(clk); i++) 541 imx_check_clocks(clk, ARRAY_SIZE(clk));
547 if (IS_ERR(clk[i]))
548 pr_err("i.MX53 clk %d: register failed with %ld\n",
549 i, PTR_ERR(clk[i]));
550 542
551 clk_data.clks = clk; 543 clk_data.clks = clk;
552 clk_data.clk_num = ARRAY_SIZE(clk); 544 clk_data.clk_num = ARRAY_SIZE(clk);
553 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 545 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
554 546
555 mx5_clocks_common_init(0, 0, 0, 0);
556
557 clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
558 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
559 clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
560 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
561 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
562 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
563 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
564 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
565 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
566 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
567 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
568 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
569 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
570 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
571 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
572
573 /* set SDHC root clock to 200MHZ*/ 547 /* set SDHC root clock to 200MHZ*/
574 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); 548 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
575 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); 549 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@@ -583,7 +557,5 @@ static void __init mx53_clocks_init(struct device_node *np)
583 557
584 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); 558 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
585 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); 559 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
586
587 mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
588} 560}
589CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); 561CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 03:06:17 -0500