1 files changed, 21 insertions, 14 deletions

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index fcd94f3b0f0e..f6086693ebd2 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -58,7 +58,7 @@ enum imx5_clks {
         tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
         uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
         gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
-        gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
+        gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
         esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
         ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
         ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
@@ -81,6 +81,7 @@ enum imx5_clks {
         ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
         ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
         ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
+        epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
         clk_max
 };
 
@@ -104,12 +105,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
                                 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
         clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
                                 main_bus_sel, ARRAY_SIZE(main_bus_sel));
-        clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1,
+        clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
                                 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
         clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
         clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
         clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
-        clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0,
+        clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
                                 per_root_sel, ARRAY_SIZE(per_root_sel));
         clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
         clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
@@ -167,12 +168,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
         clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
         clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
-        clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20);
         clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
-        clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
+        clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
         clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
-        clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
-        clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18);
+        clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
+        clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
+        clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
         clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
         clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
         clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
@@ -226,13 +227,17 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
         clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
         clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
+        clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
+        clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
+        clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
+        clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
                         pr_err("i.MX5 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
         
-        clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
         clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
         clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
         clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
@@ -248,7 +253,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
         clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
         clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
-        clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx51-cspi.0");
+        clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
         clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
         clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
         clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
@@ -279,6 +284,11 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
         clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
         clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
+        clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
+        clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
+        clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
+        clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
+        clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
 
         /* Set SDHC parents to be PLL2 */
         clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
@@ -336,7 +346,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
         clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
         clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
         clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
         clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
         clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
@@ -366,8 +375,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_set_rate(clk[esdhc_b_podf], 166250000);
 
         /* System timer */
-        mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-                MX51_INT_GPT);
+        mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
 
         clk_prepare_enable(clk[iim_gate]);
         imx_print_silicon_rev("i.MX51", mx51_revision());
@@ -452,8 +460,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_set_rate(clk[esdhc_b_podf], 200000000);
 
         /* System timer */
-        mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
-                MX53_INT_GPT);
+        mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
 
         clk_prepare_enable(clk[iim_gate]);
         imx_print_silicon_rev("i.MX53", mx53_revision());