diff options
Diffstat (limited to 'arch/arm/mach-imx/clk-imx51-imx53.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx51-imx53.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index fcd94f3b0f0e..a2200c77bf70 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c | |||
| @@ -104,12 +104,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |||
| 104 | periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); | 104 | periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); |
| 105 | clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, | 105 | clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, |
| 106 | main_bus_sel, ARRAY_SIZE(main_bus_sel)); | 106 | main_bus_sel, ARRAY_SIZE(main_bus_sel)); |
| 107 | clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1, | 107 | clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, |
| 108 | per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); | 108 | per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); |
| 109 | clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); | 109 | clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); |
| 110 | clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); | 110 | clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); |
| 111 | clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); | 111 | clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); |
| 112 | clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0, | 112 | clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, |
| 113 | per_root_sel, ARRAY_SIZE(per_root_sel)); | 113 | per_root_sel, ARRAY_SIZE(per_root_sel)); |
| 114 | clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); | 114 | clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); |
| 115 | clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); | 115 | clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); |
| @@ -172,7 +172,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |||
| 172 | clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12); | 172 | clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12); |
| 173 | clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); | 173 | clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); |
| 174 | clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16); | 174 | clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16); |
| 175 | clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18); | 175 | clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18); |
| 176 | clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); | 176 | clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); |
| 177 | clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); | 177 | clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); |
| 178 | clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); | 178 | clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); |
| @@ -366,8 +366,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, | |||
| 366 | clk_set_rate(clk[esdhc_b_podf], 166250000); | 366 | clk_set_rate(clk[esdhc_b_podf], 166250000); |
| 367 | 367 | ||
| 368 | /* System timer */ | 368 | /* System timer */ |
| 369 | mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), | 369 | mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); |
| 370 | MX51_INT_GPT); | ||
| 371 | 370 | ||
| 372 | clk_prepare_enable(clk[iim_gate]); | 371 | clk_prepare_enable(clk[iim_gate]); |
| 373 | imx_print_silicon_rev("i.MX51", mx51_revision()); | 372 | imx_print_silicon_rev("i.MX51", mx51_revision()); |
| @@ -452,8 +451,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, | |||
| 452 | clk_set_rate(clk[esdhc_b_podf], 200000000); | 451 | clk_set_rate(clk[esdhc_b_podf], 200000000); |
| 453 | 452 | ||
| 454 | /* System timer */ | 453 | /* System timer */ |
| 455 | mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), | 454 | mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT); |
| 456 | MX53_INT_GPT); | ||
| 457 | 455 | ||
| 458 | clk_prepare_enable(clk[iim_gate]); | 456 | clk_prepare_enable(clk[iim_gate]); |
| 459 | imx_print_silicon_rev("i.MX53", mx53_revision()); | 457 | imx_print_silicon_rev("i.MX53", mx53_revision()); |
