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-rw-r--r--arch/arm/mach-imx/clk-imx27.c452
1 files changed, 204 insertions, 248 deletions
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 317a662626d6..ab6349ec23b9 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -1,61 +1,36 @@
1#include <linux/clk.h> 1#include <linux/clk.h>
2#include <linux/io.h> 2#include <linux/clk-provider.h>
3#include <linux/module.h>
4#include <linux/clkdev.h> 3#include <linux/clkdev.h>
5#include <linux/err.h> 4#include <linux/err.h>
6#include <linux/clk-provider.h>
7#include <linux/of.h> 5#include <linux/of.h>
6#include <linux/of_address.h>
7#include <dt-bindings/clock/imx27-clock.h>
8 8
9#include "clk.h" 9#include "clk.h"
10#include "common.h" 10#include "common.h"
11#include "hardware.h" 11#include "hardware.h"
12 12
13#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) 13static void __iomem *ccm __initdata;
14 14
15/* Register offsets */ 15/* Register offsets */
16#define CCM_CSCR IO_ADDR_CCM(0x0) 16#define CCM_CSCR (ccm + 0x00)
17#define CCM_MPCTL0 IO_ADDR_CCM(0x4) 17#define CCM_MPCTL0 (ccm + 0x04)
18#define CCM_MPCTL1 IO_ADDR_CCM(0x8) 18#define CCM_MPCTL1 (ccm + 0x08)
19#define CCM_SPCTL0 IO_ADDR_CCM(0xc) 19#define CCM_SPCTL0 (ccm + 0x0c)
20#define CCM_SPCTL1 IO_ADDR_CCM(0x10) 20#define CCM_SPCTL1 (ccm + 0x10)
21#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) 21#define CCM_PCDR0 (ccm + 0x18)
22#define CCM_PCDR0 IO_ADDR_CCM(0x18) 22#define CCM_PCDR1 (ccm + 0x1c)
23#define CCM_PCDR1 IO_ADDR_CCM(0x1c) 23#define CCM_PCCR0 (ccm + 0x20)
24#define CCM_PCCR0 IO_ADDR_CCM(0x20) 24#define CCM_PCCR1 (ccm + 0x24)
25#define CCM_PCCR1 IO_ADDR_CCM(0x24) 25#define CCM_CCSR (ccm + 0x28)
26#define CCM_CCSR IO_ADDR_CCM(0x28)
27#define CCM_PMCTL IO_ADDR_CCM(0x2c)
28#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
29#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
30
31#define CCM_CSCR_UPDATE_DIS (1 << 31)
32#define CCM_CSCR_SSI2 (1 << 23)
33#define CCM_CSCR_SSI1 (1 << 22)
34#define CCM_CSCR_VPU (1 << 21)
35#define CCM_CSCR_MSHC (1 << 20)
36#define CCM_CSCR_SPLLRES (1 << 19)
37#define CCM_CSCR_MPLLRES (1 << 18)
38#define CCM_CSCR_SP (1 << 17)
39#define CCM_CSCR_MCU (1 << 16)
40#define CCM_CSCR_OSC26MDIV (1 << 4)
41#define CCM_CSCR_OSC26M (1 << 3)
42#define CCM_CSCR_FPM (1 << 2)
43#define CCM_CSCR_SPEN (1 << 1)
44#define CCM_CSCR_MPEN (1 << 0)
45
46/* i.MX27 TO 2+ */
47#define CCM_CSCR_ARM_SRC (1 << 15)
48
49#define CCM_SPCTL1_LF (1 << 15)
50#define CCM_SPCTL1_BRMO (1 << 6)
51 26
52static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; 27static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
53static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; 28static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
54static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", }; 29static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
55static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", }; 30static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
56static const char *clko_sel_clks[] = { 31static const char *clko_sel_clks[] = {
57 "ckil", "fpm", "ckih", "ckih", 32 "ckil", "fpm", "ckih_gate", "ckih_gate",
58 "ckih", "mpll", "spll", "cpu_div", 33 "ckih_gate", "mpll", "spll", "cpu_div",
59 "ahb", "ipg", "per1_div", "per2_div", 34 "ahb", "ipg", "per1_div", "per2_div",
60 "per3_div", "per4_div", "ssi1_div", "ssi2_div", 35 "per3_div", "per4_div", "ssi1_div", "ssi2_div",
61 "nfc_div", "mshc_div", "vpu_div", "60m", 36 "nfc_div", "mshc_div", "vpu_div", "60m",
@@ -64,239 +39,220 @@ static const char *clko_sel_clks[] = {
64 39
65static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; 40static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
66 41
67enum mx27_clks { 42static struct clk *clk[IMX27_CLK_MAX];
68 dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
69 per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
70 clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
71 clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
72 sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
73 rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
74 kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
75 gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
76 gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
77 emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
78 cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
79 vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
80 usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
81 vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
82 csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
83 uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
84 uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
85 mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
86 rtic_ahb_gate, mshc_baud_gate, clk_max
87};
88
89static struct clk *clk[clk_max];
90static struct clk_onecell_data clk_data; 43static struct clk_onecell_data clk_data;
91 44
92int __init mx27_clocks_init(unsigned long fref) 45static void __init _mx27_clocks_init(unsigned long fref)
93{ 46{
94 int i; 47 BUG_ON(!ccm);
95 struct device_node *np;
96
97 clk[dummy] = imx_clk_fixed("dummy", 0);
98 clk[ckih] = imx_clk_fixed("ckih", fref);
99 clk[ckil] = imx_clk_fixed("ckil", 32768);
100 clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
101 clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
102 48
103 clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, 49 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
104 mpll_osc_sel_clks, 50 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref);
105 ARRAY_SIZE(mpll_osc_sel_clks)); 51 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768);
106 clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, 52 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
107 ARRAY_SIZE(mpll_sel_clks)); 53 clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
108 clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); 54 clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
109 clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0); 55 clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
110 clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); 56 clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
111 clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); 57 clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
58 clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0);
59 clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
60 clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
112 61
113 if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { 62 if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
114 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); 63 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
115 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); 64 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
116 } else { 65 } else {
117 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); 66 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
118 clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); 67 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
119 } 68 }
120 69
121 clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); 70 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
122 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); 71 clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
123 clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); 72 clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
124 clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); 73 clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
125 clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); 74 clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
126 clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); 75 clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
127 clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); 76 clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
128 clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); 77 clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
129 clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); 78 clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
130 clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); 79 clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
131 clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); 80 clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
81
132 if (mx27_revision() >= IMX_CHIP_REVISION_2_0) 82 if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
133 clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); 83 clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
134 else 84 else
135 clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); 85 clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
136 clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
137 clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
138 clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
139 clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
140 clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
141 clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
142 clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
143 clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
144 clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
145 clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
146 clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
147 clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
148 clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
149 clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
150 clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
151 clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
152 clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
153 clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
154 clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
155 clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
156 clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
157 clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
158 clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
159 clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
160 clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
161 clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
162 clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
163 clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
164 clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
165 clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
166 clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
167 clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
168 clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
169 clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
170 clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
171 clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
172 clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
173 clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
174 clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
175 clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
176 clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
177 clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
178 clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
179 clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
180 clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
181 clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
182 clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
183 clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
184 clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
185 clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
186 clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
187 clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
188 clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
189 clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
190 clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
191 clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
192 clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
193 clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
194 clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
195 clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
196 clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
197 clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
198 clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
199 clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
200 clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
201 clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
202 clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
203 86
204 for (i = 0; i < ARRAY_SIZE(clk); i++) 87 clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
205 if (IS_ERR(clk[i])) 88 clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
206 pr_err("i.MX27 clk %d: register failed with %ld\n", 89 clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
207 i, PTR_ERR(clk[i])); 90 clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
91 clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
92 clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
93 clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
94 clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
95 clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
96 clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
97 clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
98 clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
99 clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
100 clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
101 clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
102 clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
103 clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
104 clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
105 clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
106 clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
107 clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
108 clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
109 clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
110 clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
111 clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
112 clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
113 clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
114 clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
115 clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
116 clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
117 clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
118 clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
119 clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
120 clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
121 clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
122 clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
123 clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
124 clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
125 clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
126 clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
127 clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
128 clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
129 clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
130 clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
131 clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
132 clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
133 clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
134 clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
135 clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
136 clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
137 clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
138 clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
139 clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
140 clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
141 clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
142 clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
143 clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
144 clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
145 clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
146 clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
147 clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
148 clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
149 clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
150 clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
151 clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
152 clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
153 clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
208 154
209 np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); 155 imx_check_clocks(clk, ARRAY_SIZE(clk));
210 if (np) {
211 clk_data.clks = clk;
212 clk_data.clk_num = ARRAY_SIZE(clk);
213 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
214 }
215 156
216 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); 157 clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0");
217 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
218 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
219 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
220 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
221 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
222 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
223 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
224 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
225 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
226 clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
227 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
228 clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
229 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
230 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
231 clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
232 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
233 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
234 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
235 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
236 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
237 clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
238 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
239 clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
240 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
241 clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
242 clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
243 clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
244 clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
245 clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
246 clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
247 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
248 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
249 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
250 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
251 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
252 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
253 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
254 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
255 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
256 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
257 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
258 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
259 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
260 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
261 clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
262 clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
263 clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
264 clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
265 clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
266 clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
267 clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
268 clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
269 clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
270 clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
271 clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
272 clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
273 clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
274 clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
275 clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
276 clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
277 clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
278 158
279 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); 159 clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
280
281 clk_prepare_enable(clk[emi_ahb_gate]);
282 160
283 imx_print_silicon_rev("i.MX27", mx27_revision()); 161 imx_print_silicon_rev("i.MX27", mx27_revision());
162}
163
164int __init mx27_clocks_init(unsigned long fref)
165{
166 ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
167
168 _mx27_clocks_init(fref);
169
170 clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
171 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0");
172 clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
173 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1");
174 clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
175 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2");
176 clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
177 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3");
178 clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
179 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4");
180 clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5");
181 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5");
182 clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
183 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0");
184 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0");
185 clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0");
186 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1");
187 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1");
188 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2");
189 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2");
190 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0");
191 clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0");
192 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1");
193 clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1");
194 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2");
195 clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2");
196 clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0");
197 clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
198 clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0");
199 clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0");
200 clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0");
201 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27");
202 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27");
203 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27");
204 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0");
205 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0");
206 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0");
207 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1");
208 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1");
209 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1");
210 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2");
211 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2");
212 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2");
213 clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
214 clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
215 clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0");
216 clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0");
217 clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0");
218 clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma");
219 clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma");
220 clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0");
221 clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0");
222 clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0");
223 clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0");
224 clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1");
225 clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0");
226 clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad");
227 clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0");
228 clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0");
229 clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");
230 clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");
231
232 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
284 233
285 return 0; 234 return 0;
286} 235}
287 236
288int __init mx27_clocks_init_dt(void) 237static void __init mx27_clocks_init_dt(struct device_node *np)
289{ 238{
290 struct device_node *np; 239 struct device_node *refnp;
291 u32 fref = 26000000; /* default */ 240 u32 fref = 26000000; /* default */
292 241
293 for_each_compatible_node(np, NULL, "fixed-clock") { 242 for_each_compatible_node(refnp, NULL, "fixed-clock") {
294 if (!of_device_is_compatible(np, "fsl,imx-osc26m")) 243 if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
295 continue; 244 continue;
296 245
297 if (!of_property_read_u32(np, "clock-frequency", &fref)) 246 if (!of_property_read_u32(refnp, "clock-frequency", &fref))
298 break; 247 break;
299 } 248 }
300 249
301 return mx27_clocks_init(fref); 250 ccm = of_iomap(np, 0);
251
252 _mx27_clocks_init(fref);
253
254 clk_data.clks = clk;
255 clk_data.clk_num = ARRAY_SIZE(clk);
256 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
302} 257}
258CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);
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