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-rw-r--r--arch/arm/mach-h720x/Kconfig40
-rw-r--r--arch/arm/mach-h720x/Makefile16
-rw-r--r--arch/arm/mach-h720x/Makefile.boot2
-rw-r--r--arch/arm/mach-h720x/common.c268
-rw-r--r--arch/arm/mach-h720x/common.h30
-rw-r--r--arch/arm/mach-h720x/cpu-h7201.c57
-rw-r--r--arch/arm/mach-h720x/cpu-h7202.c225
-rw-r--r--arch/arm/mach-h720x/h7201-eval.c38
-rw-r--r--arch/arm/mach-h720x/h7202-eval.c81
-rw-r--r--arch/arm/mach-h720x/include/mach/boards.h53
-rw-r--r--arch/arm/mach-h720x/include/mach/debug-macro.S40
-rw-r--r--arch/arm/mach-h720x/include/mach/entry-macro.S57
-rw-r--r--arch/arm/mach-h720x/include/mach/h7201-regs.h67
-rw-r--r--arch/arm/mach-h720x/include/mach/h7202-regs.h155
-rw-r--r--arch/arm/mach-h720x/include/mach/hardware.h190
-rw-r--r--arch/arm/mach-h720x/include/mach/irqs.h116
-rw-r--r--arch/arm/mach-h720x/include/mach/isa-dma.h19
-rw-r--r--arch/arm/mach-h720x/include/mach/timex.h15
-rw-r--r--arch/arm/mach-h720x/include/mach/uncompress.h36
19 files changed, 0 insertions, 1505 deletions
diff --git a/arch/arm/mach-h720x/Kconfig b/arch/arm/mach-h720x/Kconfig
deleted file mode 100644
index 6bb755bcb6f5..000000000000
--- a/arch/arm/mach-h720x/Kconfig
+++ /dev/null
@@ -1,40 +0,0 @@
1if ARCH_H720X
2
3menu "h720x Implementations"
4
5config ARCH_H7201
6 bool "gms30c7201"
7 depends on ARCH_H720X
8 select CPU_H7201
9 select ZONE_DMA
10 help
11 Say Y here if you are using the Hynix GMS30C7201 Reference Board
12
13config ARCH_H7202
14 bool "hms30c7202"
15 depends on ARCH_H720X
16 select CPU_H7202
17 select ZONE_DMA
18 help
19 Say Y here if you are using the Hynix HMS30C7202 Reference Board
20
21endmenu
22
23config CPU_H7201
24 bool
25 help
26 Select code specific to h7201 variants
27
28config CPU_H7202
29 bool
30 help
31 Select code specific to h7202 variants
32config H7202_SERIAL23
33 depends on CPU_H7202
34 bool "Use serial ports 2+3"
35 help
36 Say Y here if you wish to use serial ports 2+3. They share their
37 pins with the keyboard matrix controller, so you have to decide.
38
39
40endif
diff --git a/arch/arm/mach-h720x/Makefile b/arch/arm/mach-h720x/Makefile
deleted file mode 100644
index e4cf728948eb..000000000000
--- a/arch/arm/mach-h720x/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Common support
6obj-y := common.o
7obj-m :=
8obj-n :=
9obj- :=
10
11# Specific board support
12
13obj-$(CONFIG_ARCH_H7201) += h7201-eval.o
14obj-$(CONFIG_ARCH_H7202) += h7202-eval.o
15obj-$(CONFIG_CPU_H7201) += cpu-h7201.o
16obj-$(CONFIG_CPU_H7202) += cpu-h7202.o
diff --git a/arch/arm/mach-h720x/Makefile.boot b/arch/arm/mach-h720x/Makefile.boot
deleted file mode 100644
index d875a7094dfe..000000000000
--- a/arch/arm/mach-h720x/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-$(CONFIG_ARCH_H720X) += 0x40008000
2
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
deleted file mode 100644
index 17ef91fa3d56..000000000000
--- a/arch/arm/mach-h720x/common.c
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * linux/arch/arm/mach-h720x/common.c
3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * common stuff for Hynix h720x processors
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/sched.h>
17#include <linux/mman.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21
22#include <asm/page.h>
23#include <asm/pgtable.h>
24#include <asm/dma.h>
25#include <mach/hardware.h>
26#include <asm/irq.h>
27#include <asm/system_misc.h>
28#include <asm/mach/irq.h>
29#include <asm/mach/map.h>
30#include <mach/irqs.h>
31
32#include <asm/mach/dma.h>
33
34#if 0
35#define IRQDBG(args...) printk(args)
36#else
37#define IRQDBG(args...) do {} while(0)
38#endif
39
40void __init arch_dma_init(dma_t *dma)
41{
42}
43
44/*
45 * Return nsecs since last timer reload
46 * (timercount * (usecs perjiffie)) / (ticks per jiffie)
47 */
48u32 h720x_gettimeoffset(void)
49{
50 return ((CPU_REG(TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH) * 1000;
51}
52
53/*
54 * mask Global irq's
55 */
56static void mask_global_irq(struct irq_data *d)
57{
58 CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << d->irq);
59}
60
61/*
62 * unmask Global irq's
63 */
64static void unmask_global_irq(struct irq_data *d)
65{
66 CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq);
67}
68
69
70/*
71 * ack GPIO irq's
72 * Ack only for edge triggered int's valid
73 */
74static void inline ack_gpio_irq(struct irq_data *d)
75{
76 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
77 u32 bit = IRQ_TO_BIT(d->irq);
78 if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
79 CPU_REG (reg_base, GPIO_CLR) = bit;
80}
81
82/*
83 * mask GPIO irq's
84 */
85static void inline mask_gpio_irq(struct irq_data *d)
86{
87 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
88 u32 bit = IRQ_TO_BIT(d->irq);
89 CPU_REG (reg_base, GPIO_MASK) &= ~bit;
90}
91
92/*
93 * unmask GPIO irq's
94 */
95static void inline unmask_gpio_irq(struct irq_data *d)
96{
97 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
98 u32 bit = IRQ_TO_BIT(d->irq);
99 CPU_REG (reg_base, GPIO_MASK) |= bit;
100}
101
102static void
103h720x_gpio_handler(unsigned int mask, unsigned int irq,
104 struct irq_desc *desc)
105{
106 IRQDBG("%s irq: %d\n", __func__, irq);
107 while (mask) {
108 if (mask & 1) {
109 IRQDBG("handling irq %d\n", irq);
110 generic_handle_irq(irq);
111 }
112 irq++;
113 mask >>= 1;
114 }
115}
116
117static void
118h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
119{
120 unsigned int mask, irq;
121
122 mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
123 irq = IRQ_CHAINED_GPIOA(0);
124 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
125 h720x_gpio_handler(mask, irq, desc);
126}
127
128static void
129h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
130{
131 unsigned int mask, irq;
132 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
133 irq = IRQ_CHAINED_GPIOB(0);
134 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
135 h720x_gpio_handler(mask, irq, desc);
136}
137
138static void
139h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
140{
141 unsigned int mask, irq;
142
143 mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
144 irq = IRQ_CHAINED_GPIOC(0);
145 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
146 h720x_gpio_handler(mask, irq, desc);
147}
148
149static void
150h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
151{
152 unsigned int mask, irq;
153
154 mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
155 irq = IRQ_CHAINED_GPIOD(0);
156 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
157 h720x_gpio_handler(mask, irq, desc);
158}
159
160#ifdef CONFIG_CPU_H7202
161static void
162h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
163{
164 unsigned int mask, irq;
165
166 mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
167 irq = IRQ_CHAINED_GPIOE(0);
168 IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
169 h720x_gpio_handler(mask, irq, desc);
170}
171#endif
172
173static struct irq_chip h720x_global_chip = {
174 .irq_ack = mask_global_irq,
175 .irq_mask = mask_global_irq,
176 .irq_unmask = unmask_global_irq,
177};
178
179static struct irq_chip h720x_gpio_chip = {
180 .irq_ack = ack_gpio_irq,
181 .irq_mask = mask_gpio_irq,
182 .irq_unmask = unmask_gpio_irq,
183};
184
185/*
186 * Initialize IRQ's, mask all, enable multiplexed irq's
187 */
188void __init h720x_init_irq (void)
189{
190 int irq;
191
192 /* Mask global irq's */
193 CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
194
195 /* Mask all multiplexed irq's */
196 CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
197 CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
198 CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
199 CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
200
201 /* Initialize global IRQ's, fast path */
202 for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
203 irq_set_chip_and_handler(irq, &h720x_global_chip,
204 handle_level_irq);
205 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
206 }
207
208 /* Initialize multiplexed IRQ's, slow path */
209 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
210 irq_set_chip_and_handler(irq, &h720x_gpio_chip,
211 handle_edge_irq);
212 set_irq_flags(irq, IRQF_VALID );
213 }
214 irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
215 irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
216 irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
217 irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
218
219#ifdef CONFIG_CPU_H7202
220 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
221 irq_set_chip_and_handler(irq, &h720x_gpio_chip,
222 handle_edge_irq);
223 set_irq_flags(irq, IRQF_VALID );
224 }
225 irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
226#endif
227
228 /* Enable multiplexed irq's */
229 CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
230}
231
232static struct map_desc h720x_io_desc[] __initdata = {
233 {
234 .virtual = IO_VIRT,
235 .pfn = __phys_to_pfn(IO_PHYS),
236 .length = IO_SIZE,
237 .type = MT_DEVICE
238 },
239};
240
241/* Initialize io tables */
242void __init h720x_map_io(void)
243{
244 iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
245}
246
247void h720x_restart(char mode, const char *cmd)
248{
249 CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
250}
251
252static void h720x__idle(void)
253{
254 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
255 nop();
256 nop();
257 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
258 nop();
259 nop();
260}
261
262static int __init h720x_idle_init(void)
263{
264 arm_pm_idle = h720x__idle;
265 return 0;
266}
267
268arch_initcall(h720x_idle_init);
diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h
deleted file mode 100644
index 7e738410ca93..000000000000
--- a/arch/arm/mach-h720x/common.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * linux/arch/arm/mach-h720x/common.h
3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * Architecture specific stuff for Hynix GMS30C7201 development board
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16extern u32 h720x_gettimeoffset(void);
17extern void __init h720x_init_irq(void);
18extern void __init h720x_map_io(void);
19extern void h720x_restart(char, const char *);
20
21#ifdef CONFIG_ARCH_H7202
22extern void h7202_timer_init(void);
23extern void __init init_hw_h7202(void);
24extern void __init h7202_init_irq(void);
25extern void __init h7202_init_time(void);
26#endif
27
28#ifdef CONFIG_ARCH_H7201
29extern void h7201_timer_init(void);
30#endif
diff --git a/arch/arm/mach-h720x/cpu-h7201.c b/arch/arm/mach-h720x/cpu-h7201.c
deleted file mode 100644
index 13c741215387..000000000000
--- a/arch/arm/mach-h720x/cpu-h7201.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * linux/arch/arm/mach-h720x/cpu-h7201.c
3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * processor specific stuff for the Hynix h7201
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <asm/types.h>
20#include <mach/hardware.h>
21#include <asm/irq.h>
22#include <mach/irqs.h>
23#include <asm/mach/irq.h>
24#include <asm/mach/time.h>
25#include "common.h"
26/*
27 * Timer interrupt handler
28 */
29static irqreturn_t
30h7201_timer_interrupt(int irq, void *dev_id)
31{
32 CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
33 timer_tick();
34
35 return IRQ_HANDLED;
36}
37
38static struct irqaction h7201_timer_irq = {
39 .name = "h7201 Timer Tick",
40 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
41 .handler = h7201_timer_interrupt,
42};
43
44/*
45 * Setup TIMER0 as system timer
46 */
47void __init h7201_timer_init(void)
48{
49 arch_gettimeoffset = h720x_gettimeoffset;
50
51 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
52 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
53 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
54 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
55
56 setup_irq(IRQ_TIMER0, &h7201_timer_irq);
57}
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
deleted file mode 100644
index e2ae7e898f9d..000000000000
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ /dev/null
@@ -1,225 +0,0 @@
1/*
2 * linux/arch/arm/mach-h720x/cpu-h7202.c
3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * processor specific stuff for the Hynix h7202
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <asm/types.h>
20#include <mach/hardware.h>
21#include <asm/irq.h>
22#include <mach/irqs.h>
23#include <asm/mach/irq.h>
24#include <asm/mach/time.h>
25#include <linux/device.h>
26#include <linux/serial_8250.h>
27#include "common.h"
28
29static struct resource h7202ps2_resources[] = {
30 [0] = {
31 .start = 0x8002c000,
32 .end = 0x8002c040,
33 .flags = IORESOURCE_MEM,
34 },
35 [1] = {
36 .start = IRQ_PS2,
37 .end = IRQ_PS2,
38 .flags = IORESOURCE_IRQ,
39 },
40};
41
42static struct platform_device h7202ps2_device = {
43 .name = "h7202ps2",
44 .id = -1,
45 .num_resources = ARRAY_SIZE(h7202ps2_resources),
46 .resource = h7202ps2_resources,
47};
48
49static struct plat_serial8250_port serial_platform_data[] = {
50 {
51 .membase = (void*)SERIAL0_VIRT,
52 .mapbase = SERIAL0_BASE,
53 .irq = IRQ_UART0,
54 .uartclk = 2*1843200,
55 .regshift = 2,
56 .iotype = UPIO_MEM,
57 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
58 },
59 {
60 .membase = (void*)SERIAL1_VIRT,
61 .mapbase = SERIAL1_BASE,
62 .irq = IRQ_UART1,
63 .uartclk = 2*1843200,
64 .regshift = 2,
65 .iotype = UPIO_MEM,
66 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
67 },
68#ifdef CONFIG_H7202_SERIAL23
69 {
70 .membase = (void*)SERIAL2_VIRT,
71 .mapbase = SERIAL2_BASE,
72 .irq = IRQ_UART2,
73 .uartclk = 2*1843200,
74 .regshift = 2,
75 .iotype = UPIO_MEM,
76 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
77 },
78 {
79 .membase = (void*)SERIAL3_VIRT,
80 .mapbase = SERIAL3_BASE,
81 .irq = IRQ_UART3,
82 .uartclk = 2*1843200,
83 .regshift = 2,
84 .iotype = UPIO_MEM,
85 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
86 },
87#endif
88 { },
89};
90
91static struct platform_device serial_device = {
92 .name = "serial8250",
93 .id = PLAT8250_DEV_PLATFORM,
94 .dev = {
95 .platform_data = serial_platform_data,
96 },
97};
98
99static struct platform_device *devices[] __initdata = {
100 &h7202ps2_device,
101 &serial_device,
102};
103
104/* Although we have two interrupt lines for the timers, we only have one
105 * status register which clears all pending timer interrupts on reading. So
106 * we have to handle all timer interrupts in one place.
107 */
108static void
109h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
110{
111 unsigned int mask, irq;
112
113 mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
114
115 if ( mask & TSTAT_T0INT ) {
116 timer_tick();
117 if( mask == TSTAT_T0INT )
118 return;
119 }
120
121 mask >>= 1;
122 irq = IRQ_TIMER1;
123 while (mask) {
124 if (mask & 1)
125 generic_handle_irq(irq);
126 irq++;
127 mask >>= 1;
128 }
129}
130
131/*
132 * Timer interrupt handler
133 */
134static irqreturn_t
135h7202_timer_interrupt(int irq, void *dev_id)
136{
137 h7202_timerx_demux_handler(0, NULL);
138 return IRQ_HANDLED;
139}
140
141/*
142 * mask multiplexed timer IRQs
143 */
144static void inline __mask_timerx_irq(unsigned int irq)
145{
146 unsigned int bit;
147 bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
148 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
149}
150
151static void inline mask_timerx_irq(struct irq_data *d)
152{
153 __mask_timerx_irq(d->irq);
154}
155
156/*
157 * unmask multiplexed timer IRQs
158 */
159static void inline unmask_timerx_irq(struct irq_data *d)
160{
161 unsigned int bit;
162 bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
163 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
164}
165
166static struct irq_chip h7202_timerx_chip = {
167 .irq_ack = mask_timerx_irq,
168 .irq_mask = mask_timerx_irq,
169 .irq_unmask = unmask_timerx_irq,
170};
171
172static struct irqaction h7202_timer_irq = {
173 .name = "h7202 Timer Tick",
174 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
175 .handler = h7202_timer_interrupt,
176};
177
178/*
179 * Setup TIMER0 as system timer
180 */
181void __init h7202_timer_init(void)
182{
183 arch_gettimeoffset = h720x_gettimeoffset;
184
185 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
186 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
187 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
188 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
189
190 setup_irq(IRQ_TIMER0, &h7202_timer_irq);
191}
192
193void __init h7202_init_irq (void)
194{
195 int irq;
196
197 CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
198
199 for (irq = IRQ_TIMER1;
200 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
201 __mask_timerx_irq(irq);
202 irq_set_chip_and_handler(irq, &h7202_timerx_chip,
203 handle_edge_irq);
204 set_irq_flags(irq, IRQF_VALID );
205 }
206 irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
207
208 h720x_init_irq();
209}
210
211void __init init_hw_h7202(void)
212{
213 /* Enable clocks */
214 CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
215
216 CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
217 CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
218#ifdef CONFIG_H7202_SERIAL23
219 CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
220 CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
221 CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 |
222 AMULSEL_USIN3 | AMULSEL_USOUT3;
223#endif
224 (void) platform_add_devices(devices, ARRAY_SIZE(devices));
225}
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
deleted file mode 100644
index 4fdeb686c0a9..000000000000
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * linux/arch/arm/mach-h720x/h7201-eval.c
3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * Architecture specific stuff for Hynix GMS30C7201 development board
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/string.h>
20#include <linux/device.h>
21
22#include <asm/setup.h>
23#include <asm/types.h>
24#include <asm/mach-types.h>
25#include <asm/page.h>
26#include <asm/mach/arch.h>
27#include <mach/hardware.h>
28#include "common.h"
29
30MACHINE_START(H7201, "Hynix GMS30C7201")
31 /* Maintainer: Robert Schwebel, Pengutronix */
32 .atag_offset = 0x1000,
33 .map_io = h720x_map_io,
34 .init_irq = h720x_init_irq,
35 .init_time = h7201_timer_init,
36 .dma_zone_size = SZ_256M,
37 .restart = h720x_restart,
38MACHINE_END
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
deleted file mode 100644
index f68e967a2062..000000000000
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * linux/arch/arm/mach-h720x/h7202-eval.c
3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * Architecture specific stuff for Hynix HMS30C7202 development board
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/string.h>
20#include <linux/platform_device.h>
21
22#include <asm/setup.h>
23#include <asm/types.h>
24#include <asm/mach-types.h>
25#include <asm/page.h>
26#include <asm/mach/arch.h>
27#include <mach/irqs.h>
28#include <mach/hardware.h>
29#include "common.h"
30
31static struct resource cirrus_resources[] = {
32 [0] = {
33 .start = ETH0_PHYS + 0x300,
34 .end = ETH0_PHYS + 0x300 + 0x10,
35 .flags = IORESOURCE_MEM,
36 },
37 [1] = {
38 .start = IRQ_CHAINED_GPIOB(8),
39 .end = IRQ_CHAINED_GPIOB(8),
40 .flags = IORESOURCE_IRQ,
41 },
42};
43
44static struct platform_device cirrus_device = {
45 .name = "cirrus-cs89x0",
46 .id = -1,
47 .num_resources = ARRAY_SIZE(cirrus_resources),
48 .resource = cirrus_resources,
49};
50
51static struct platform_device *devices[] __initdata = {
52 &cirrus_device,
53};
54
55/*
56 * Hardware init. This is called early in initcalls
57 * Place pin inits here. So you avoid adding ugly
58 * #ifdef stuff to common drivers.
59 * Use this only, if your bootloader is not able
60 * to initialize the pins proper.
61 */
62static void __init init_eval_h7202(void)
63{
64 init_hw_h7202();
65 (void) platform_add_devices(devices, ARRAY_SIZE(devices));
66
67 /* Enable interrupt on portb bit 8 (ethernet) */
68 CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8);
69 CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
70}
71
72MACHINE_START(H7202, "Hynix HMS30C7202")
73 /* Maintainer: Robert Schwebel, Pengutronix */
74 .atag_offset = 0x100,
75 .map_io = h720x_map_io,
76 .init_irq = h7202_init_irq,
77 .init_time = h7202_timer_init,
78 .init_machine = init_eval_h7202,
79 .dma_zone_size = SZ_256M,
80 .restart = h720x_restart,
81MACHINE_END
diff --git a/arch/arm/mach-h720x/include/mach/boards.h b/arch/arm/mach-h720x/include/mach/boards.h
deleted file mode 100644
index 38b8e0d61fbf..000000000000
--- a/arch/arm/mach-h720x/include/mach/boards.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/boards.h
3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 *
7 * This file contains the board specific defines for various devices
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
15#error Do not include this file directly. Include asm/hardware.h instead !
16#endif
17
18/* Hynix H7202 developer board specific device defines */
19#ifdef CONFIG_ARCH_H7202
20
21/* FLASH */
22#define H720X_FLASH_VIRT 0xd0000000
23#define H720X_FLASH_PHYS 0x00000000
24#define H720X_FLASH_SIZE 0x02000000
25
26/* onboard LAN controller */
27# define ETH0_PHYS 0x08000000
28
29/* Touch screen defines */
30/* GPIO Port */
31#define PEN_GPIO GPIO_B_VIRT
32/* Bitmask for pen down interrupt */
33#define PEN_INT_BIT (1<<7)
34/* Bitmask for pen up interrupt */
35#define PEN_ENA_BIT (1<<6)
36/* pen up interrupt */
37#define IRQ_PEN IRQ_MUX_GPIOB(7)
38
39#endif
40
41/* Hynix H7201 developer board specific device defines */
42#if defined (CONFIG_ARCH_H7201)
43/* ROM DISK SPACE */
44#define ROM_DISK_BASE 0xc1800000
45#define ROM_DISK_START 0x41800000
46#define ROM_DISK_SIZE 0x00700000
47
48/* SRAM DISK SPACE */
49#define SRAM_DISK_BASE 0xf1000000
50#define SRAM_DISK_START 0x04000000
51#define SRAM_DISK_SIZE 0x00400000
52#endif
53
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
deleted file mode 100644
index 8a46157b0582..000000000000
--- a/arch/arm/mach-h720x/include/mach/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
1/* arch/arm/mach-h720x/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <mach/hardware.h>
15
16 .equ io_virt, IO_VIRT
17 .equ io_phys, IO_PHYS
18
19 .macro addruart, rp, rv, tmp
20 mov \rp, #0x00020000 @ UART1
21 add \rv, \rp, #io_virt @ virtual address
22 add \rp, \rp, #io_phys @ physical base address
23 .endm
24
25 .macro senduart,rd,rx
26 str \rd, [\rx, #0x0] @ UARTDR
27
28 .endm
29
30 .macro waituart,rd,rx
311001: ldr \rd, [\rx, #0x18] @ UARTFLG
32 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
33 bne 1001b
34 .endm
35
36 .macro busyuart,rd,rx
371001: ldr \rd, [\rx, #0x18] @ UARTFLG
38 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
39 bne 1001b
40 .endm
diff --git a/arch/arm/mach-h720x/include/mach/entry-macro.S b/arch/arm/mach-h720x/include/mach/entry-macro.S
deleted file mode 100644
index 75267fad7012..000000000000
--- a/arch/arm/mach-h720x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Hynix HMS720x based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 .macro get_irqnr_preamble, base, tmp
12 .endm
13
14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
15#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
16 @ we could use the id register on H7202, but this is not
17 @ properly updated when we come back from asm_do_irq
18 @ without a previous return from interrupt
19 @ (see loops below in irq_svc, irq_usr)
20 @ We see unmasked pending ints only, as the masked pending ints
21 @ are not visible here
22
23 mov \base, #0xf0000000 @ base register
24 orr \base, \base, #0x24000 @ irqbase
25 ldr \irqstat, [\base, #0x04] @ get interrupt status
26#if defined (CONFIG_CPU_H7201)
27 ldr \tmp, =0x001fffff
28#else
29 mvn \tmp, #0xc0000000
30#endif
31 and \irqstat, \irqstat, \tmp @ mask out unused ints
32 mov \irqnr, #0
33
34 mov \tmp, #0xff00
35 orr \tmp, \tmp, #0xff
36 tst \irqstat, \tmp
37 addeq \irqnr, \irqnr, #16
38 moveq \irqstat, \irqstat, lsr #16
39 tst \irqstat, #255
40 addeq \irqnr, \irqnr, #8
41 moveq \irqstat, \irqstat, lsr #8
42 tst \irqstat, #15
43 addeq \irqnr, \irqnr, #4
44 moveq \irqstat, \irqstat, lsr #4
45 tst \irqstat, #3
46 addeq \irqnr, \irqnr, #2
47 moveq \irqstat, \irqstat, lsr #2
48 tst \irqstat, #1
49 addeq \irqnr, \irqnr, #1
50 moveq \irqstat, \irqstat, lsr #1
51 tst \irqstat, #1 @ bit 0 should be set
52 .endm
53
54#else
55#error hynix processor selection missmatch
56#endif
57
diff --git a/arch/arm/mach-h720x/include/mach/h7201-regs.h b/arch/arm/mach-h720x/include/mach/h7201-regs.h
deleted file mode 100644
index 611b4947ccfc..000000000000
--- a/arch/arm/mach-h720x/include/mach/h7201-regs.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/h7201-regs.h
3 *
4 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
5 * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
6 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
7 * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
8 *
9 * This file contains the hardware definitions of the h720x processors
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * Do not add implementations specific defines here. This files contains
16 * only defines of the onchip peripherals. Add those defines to boards.h,
17 * which is included by this file.
18 */
19
20#define SERIAL2_VIRT (IO_VIRT + 0x50100)
21#define SERIAL3_VIRT (IO_VIRT + 0x50200)
22
23/*
24 * PCMCIA
25 */
26#define PCMCIA0_ATT_BASE 0xe5000000
27#define PCMCIA0_ATT_SIZE 0x00200000
28#define PCMCIA0_ATT_START 0x20000000
29#define PCMCIA0_MEM_BASE 0xe5200000
30#define PCMCIA0_MEM_SIZE 0x00200000
31#define PCMCIA0_MEM_START 0x24000000
32#define PCMCIA0_IO_BASE 0xe5400000
33#define PCMCIA0_IO_SIZE 0x00200000
34#define PCMCIA0_IO_START 0x28000000
35
36#define PCMCIA1_ATT_BASE 0xe5600000
37#define PCMCIA1_ATT_SIZE 0x00200000
38#define PCMCIA1_ATT_START 0x30000000
39#define PCMCIA1_MEM_BASE 0xe5800000
40#define PCMCIA1_MEM_SIZE 0x00200000
41#define PCMCIA1_MEM_START 0x34000000
42#define PCMCIA1_IO_BASE 0xe5a00000
43#define PCMCIA1_IO_SIZE 0x00200000
44#define PCMCIA1_IO_START 0x38000000
45
46#define PRIME3C_BASE 0xf0050000
47#define PRIME3C_SIZE 0x00001000
48#define PRIME3C_START 0x10000000
49
50/* VGA Controller */
51#define VGA_RAMBASE 0x50
52#define VGA_TIMING0 0x60
53#define VGA_TIMING1 0x64
54#define VGA_TIMING2 0x68
55#define VGA_TIMING3 0x6c
56
57#define LCD_CTRL_VGA_ENABLE 0x00000100
58#define LCD_CTRL_VGA_BPP_MASK 0x00000600
59#define LCD_CTRL_VGA_4BPP 0x00000000
60#define LCD_CTRL_VGA_8BPP 0x00000200
61#define LCD_CTRL_VGA_16BPP 0x00000300
62#define LCD_CTRL_SHARE_DMA 0x00000800
63#define LCD_CTRL_VDE 0x00100000
64#define LCD_CTRL_LPE 0x00400000 /* LCD Power enable */
65#define LCD_CTRL_BLE 0x00800000 /* LCD backlight enable */
66
67#define VGA_PALETTE_BASE (IO_VIRT + 0x10800)
diff --git a/arch/arm/mach-h720x/include/mach/h7202-regs.h b/arch/arm/mach-h720x/include/mach/h7202-regs.h
deleted file mode 100644
index 17c12eb34995..000000000000
--- a/arch/arm/mach-h720x/include/mach/h7202-regs.h
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/h7202-regs.h
3 *
4 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
5 * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
6 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
7 * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
8 *
9 * This file contains the hardware definitions of the h720x processors
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * Do not add implementations specific defines here. This files contains
16 * only defines of the onchip peripherals. Add those defines to boards.h,
17 * which is included by this file.
18 */
19
20#define SERIAL2_OFS 0x2d000
21#define SERIAL2_BASE (IO_PHYS + SERIAL2_OFS)
22#define SERIAL2_VIRT (IO_VIRT + SERIAL2_OFS)
23#define SERIAL3_OFS 0x2e000
24#define SERIAL3_BASE (IO_PHYS + SERIAL3_OFS)
25#define SERIAL3_VIRT (IO_VIRT + SERIAL3_OFS)
26
27/* Matrix Keyboard Controller */
28#define KBD_VIRT (IO_VIRT + 0x22000)
29#define KBD_KBCR 0x00
30#define KBD_KBSC 0x04
31#define KBD_KBTR 0x08
32#define KBD_KBVR0 0x0C
33#define KBD_KBVR1 0x10
34#define KBD_KBSR 0x18
35
36#define KBD_KBCR_SCANENABLE (1 << 7)
37#define KBD_KBCR_NPOWERDOWN (1 << 2)
38#define KBD_KBCR_CLKSEL_MASK (3)
39#define KBD_KBCR_CLKSEL_PCLK2 0x0
40#define KBD_KBCR_CLKSEL_PCLK128 0x1
41#define KBD_KBCR_CLKSEL_PCLK256 0x2
42#define KBD_KBCR_CLKSEL_PCLK512 0x3
43
44#define KBD_KBSR_INTR (1 << 0)
45#define KBD_KBSR_WAKEUP (1 << 1)
46
47/* USB device controller */
48
49#define USBD_BASE (IO_VIRT + 0x12000)
50#define USBD_LENGTH 0x3C
51
52#define USBD_GCTRL 0x00
53#define USBD_EPCTRL 0x04
54#define USBD_INTMASK 0x08
55#define USBD_INTSTAT 0x0C
56#define USBD_PWR 0x10
57#define USBD_DMARXTX 0x14
58#define USBD_DEVID 0x18
59#define USBD_DEVCLASS 0x1C
60#define USBD_INTCLASS 0x20
61#define USBD_SETUP0 0x24
62#define USBD_SETUP1 0x28
63#define USBD_ENDP0RD 0x2C
64#define USBD_ENDP0WT 0x30
65#define USBD_ENDP1RD 0x34
66#define USBD_ENDP2WT 0x38
67
68/* PS/2 port */
69#define PSDATA 0x00
70#define PSSTAT 0x04
71#define PSSTAT_TXEMPTY (1<<0)
72#define PSSTAT_TXBUSY (1<<1)
73#define PSSTAT_RXFULL (1<<2)
74#define PSSTAT_RXBUSY (1<<3)
75#define PSSTAT_CLKIN (1<<4)
76#define PSSTAT_DATAIN (1<<5)
77#define PSSTAT_PARITY (1<<6)
78
79#define PSCONF 0x08
80#define PSCONF_ENABLE (1<<0)
81#define PSCONF_TXINTEN (1<<2)
82#define PSCONF_RXINTEN (1<<3)
83#define PSCONF_FORCECLKLOW (1<<4)
84#define PSCONF_FORCEDATLOW (1<<5)
85#define PSCONF_LCE (1<<6)
86
87#define PSINTR 0x0C
88#define PSINTR_TXINT (1<<0)
89#define PSINTR_RXINT (1<<1)
90#define PSINTR_PAR (1<<2)
91#define PSINTR_RXTO (1<<3)
92#define PSINTR_TXTO (1<<4)
93
94#define PSTDLO 0x10 /* clk low before start transmission */
95#define PSTPRI 0x14 /* PRI clock */
96#define PSTXMT 0x18 /* maximum transmission time */
97#define PSTREC 0x20 /* maximum receive time */
98#define PSPWDN 0x3c
99
100/* ADC converter */
101#define ADC_BASE (IO_VIRT + 0x29000)
102#define ADC_CR 0x00
103#define ADC_TSCTRL 0x04
104#define ADC_BT_CTRL 0x08
105#define ADC_MC_CTRL 0x0C
106#define ADC_STATUS 0x10
107
108/* ADC control register bits */
109#define ADC_CR_PW_CTRL 0x80
110#define ADC_CR_DIRECTC 0x04
111#define ADC_CR_CONTIME_NO 0x00
112#define ADC_CR_CONTIME_2 0x04
113#define ADC_CR_CONTIME_4 0x08
114#define ADC_CR_CONTIME_ADE 0x0c
115#define ADC_CR_LONGCALTIME 0x01
116
117/* ADC touch panel register bits */
118#define ADC_TSCTRL_ENABLE 0x80
119#define ADC_TSCTRL_INTR 0x40
120#define ADC_TSCTRL_SWBYPSS 0x20
121#define ADC_TSCTRL_SWINVT 0x10
122#define ADC_TSCTRL_S400 0x03
123#define ADC_TSCTRL_S200 0x02
124#define ADC_TSCTRL_S100 0x01
125#define ADC_TSCTRL_S50 0x00
126
127/* ADC Interrupt Status Register bits */
128#define ADC_STATUS_TS_BIT 0x80
129#define ADC_STATUS_MBT_BIT 0x40
130#define ADC_STATUS_BBT_BIT 0x20
131#define ADC_STATUS_MIC_BIT 0x10
132
133/* Touch data registers */
134#define ADC_TS_X0X1 0x30
135#define ADC_TS_X2X3 0x34
136#define ADC_TS_Y0Y1 0x38
137#define ADC_TS_Y2Y3 0x3c
138#define ADC_TS_X4X5 0x40
139#define ADC_TS_X6X7 0x44
140#define ADC_TS_Y4Y5 0x48
141#define ADC_TS_Y6Y7 0x50
142
143/* battery data */
144#define ADC_MB_DATA 0x54
145#define ADC_BB_DATA 0x58
146
147/* Sound data register */
148#define ADC_SD_DAT0 0x60
149#define ADC_SD_DAT1 0x64
150#define ADC_SD_DAT2 0x68
151#define ADC_SD_DAT3 0x6c
152#define ADC_SD_DAT4 0x70
153#define ADC_SD_DAT5 0x74
154#define ADC_SD_DAT6 0x78
155#define ADC_SD_DAT7 0x7c
diff --git a/arch/arm/mach-h720x/include/mach/hardware.h b/arch/arm/mach-h720x/include/mach/hardware.h
deleted file mode 100644
index c55a52c6541d..000000000000
--- a/arch/arm/mach-h720x/include/mach/hardware.h
+++ /dev/null
@@ -1,190 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/hardware.h
3 *
4 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
5 * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
6 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
7 *
8 * This file contains the hardware definitions of the h720x processors
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Do not add implementations specific defines here. This files contains
15 * only defines of the onchip peripherals. Add those defines to boards.h,
16 * which is included by this file.
17 */
18
19#ifndef __ASM_ARCH_HARDWARE_H
20#define __ASM_ARCH_HARDWARE_H
21
22#define IOCLK (3686400L)
23
24/* Onchip peripherals */
25
26#define IO_VIRT 0xf0000000 /* IO peripherals */
27#define IO_PHYS 0x80000000
28#define IO_SIZE 0x00050000
29
30#ifdef CONFIG_CPU_H7202
31#include "h7202-regs.h"
32#elif defined CONFIG_CPU_H7201
33#include "h7201-regs.h"
34#else
35#error machine definition mismatch
36#endif
37
38/* Macro to access the CPU IO */
39#define CPU_IO(x) (*(volatile u32*)(x))
40
41/* Macro to access general purpose regs (base, offset) */
42#define CPU_REG(x,y) CPU_IO(x+y)
43
44/* Macro to access irq related regs */
45#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
46
47/* CPU registers */
48/* general purpose I/O */
49#define GPIO_VIRT(x) (IO_VIRT + 0x23000 + ((x)<<5))
50#define GPIO_A_VIRT (GPIO_VIRT(0))
51#define GPIO_B_VIRT (GPIO_VIRT(1))
52#define GPIO_C_VIRT (GPIO_VIRT(2))
53#define GPIO_D_VIRT (GPIO_VIRT(3))
54#define GPIO_E_VIRT (GPIO_VIRT(4))
55#define GPIO_AMULSEL (GPIO_VIRT(0) + 0xA4)
56
57#define AMULSEL_USIN2 (1<<5)
58#define AMULSEL_USOUT2 (1<<6)
59#define AMULSEL_USIN3 (1<<13)
60#define AMULSEL_USOUT3 (1<<14)
61#define AMULSEL_IRDIN (1<<15)
62#define AMULSEL_IRDOUT (1<<7)
63
64/* Register offsets general purpose I/O */
65#define GPIO_DATA 0x00
66#define GPIO_DIR 0x04
67#define GPIO_MASK 0x08
68#define GPIO_STAT 0x0C
69#define GPIO_EDGE 0x10
70#define GPIO_CLR 0x14
71#define GPIO_POL 0x18
72#define GPIO_EN 0x1C
73
74/*interrupt controller */
75#define IRQC_VIRT (IO_VIRT + 0x24000)
76/* register offset interrupt controller */
77#define IRQC_IER 0x00
78#define IRQC_ISR 0x04
79
80/* timer unit */
81#define TIMER_VIRT (IO_VIRT + 0x25000)
82/* Register offsets timer unit */
83#define TM0_PERIOD 0x00
84#define TM0_COUNT 0x08
85#define TM0_CTRL 0x10
86#define TM1_PERIOD 0x20
87#define TM1_COUNT 0x28
88#define TM1_CTRL 0x30
89#define TM2_PERIOD 0x40
90#define TM2_COUNT 0x48
91#define TM2_CTRL 0x50
92#define TIMER_TOPCTRL 0x60
93#define TIMER_TOPSTAT 0x64
94#define T64_COUNTL 0x80
95#define T64_COUNTH 0x84
96#define T64_CTRL 0x88
97#define T64_BASEL 0x94
98#define T64_BASEH 0x98
99/* Bitmaks timer unit TOPSTAT reg */
100#define TSTAT_T0INT 0x1
101#define TSTAT_T1INT 0x2
102#define TSTAT_T2INT 0x4
103#define TSTAT_T3INT 0x8
104/* Bit description of TMx_CTRL register */
105#define TM_START 0x1
106#define TM_REPEAT 0x2
107#define TM_RESET 0x4
108/* Bit description of TIMER_CTRL register */
109#define ENABLE_TM0_INTR 0x1
110#define ENABLE_TM1_INTR 0x2
111#define ENABLE_TM2_INTR 0x4
112#define TIMER_ENABLE_BIT 0x8
113#define ENABLE_TIMER64 0x10
114#define ENABLE_TIMER64_INT 0x20
115
116/* PMU & PLL */
117#define PMU_BASE (IO_VIRT + 0x1000)
118#define PMU_MODE 0x00
119#define PMU_STAT 0x20
120#define PMU_PLL_CTRL 0x28
121
122/* PMU Mode bits */
123#define PMU_MODE_SLOW 0x00
124#define PMU_MODE_RUN 0x01
125#define PMU_MODE_IDLE 0x02
126#define PMU_MODE_SLEEP 0x03
127#define PMU_MODE_INIT 0x04
128#define PMU_MODE_DEEPSLEEP 0x07
129#define PMU_MODE_WAKEUP 0x08
130
131/* PMU ... */
132#define PLL_2_EN 0x8000
133#define PLL_1_EN 0x4000
134#define PLL_3_MUTE 0x0080
135
136/* Control bits for PMU/ PLL */
137#define PMU_WARMRESET 0x00010000
138#define PLL_CTRL_MASK23 0x000080ff
139
140/* LCD Controller */
141#define LCD_BASE (IO_VIRT + 0x10000)
142#define LCD_CTRL 0x00
143#define LCD_STATUS 0x04
144#define LCD_STATUS_M 0x08
145#define LCD_INTERRUPT 0x0C
146#define LCD_DBAR 0x10
147#define LCD_DCAR 0x14
148#define LCD_TIMING0 0x20
149#define LCD_TIMING1 0x24
150#define LCD_TIMING2 0x28
151#define LCD_TEST 0x40
152
153/* LCD Control Bits */
154#define LCD_CTRL_LCD_ENABLE 0x00000001
155/* Bits per pixel */
156#define LCD_CTRL_LCD_BPP_MASK 0x00000006
157#define LCD_CTRL_LCD_4BPP 0x00000000
158#define LCD_CTRL_LCD_8BPP 0x00000002
159#define LCD_CTRL_LCD_16BPP 0x00000004
160#define LCD_CTRL_LCD_BW 0x00000008
161#define LCD_CTRL_LCD_TFT 0x00000010
162#define LCD_CTRL_BGR 0x00001000
163#define LCD_CTRL_LCD_VCOMP 0x00080000
164#define LCD_CTRL_LCD_MONO8 0x00200000
165#define LCD_CTRL_LCD_PWR 0x00400000
166#define LCD_CTRL_LCD_BLE 0x00800000
167#define LCD_CTRL_LDBUSEN 0x01000000
168
169/* Palette */
170#define LCD_PALETTE_BASE (IO_VIRT + 0x10400)
171
172/* Serial ports */
173#define SERIAL0_OFS 0x20000
174#define SERIAL0_VIRT (IO_VIRT + SERIAL0_OFS)
175#define SERIAL0_BASE (IO_PHYS + SERIAL0_OFS)
176
177#define SERIAL1_OFS 0x21000
178#define SERIAL1_VIRT (IO_VIRT + SERIAL1_OFS)
179#define SERIAL1_BASE (IO_PHYS + SERIAL1_OFS)
180
181#define SERIAL_ENABLE 0x30
182#define SERIAL_ENABLE_EN (1<<0)
183
184/* General defines to pacify gcc */
185
186#define __ASM_ARCH_HARDWARE_INCMACH_H
187#include "boards.h"
188#undef __ASM_ARCH_HARDWARE_INCMACH_H
189
190#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-h720x/include/mach/irqs.h b/arch/arm/mach-h720x/include/mach/irqs.h
deleted file mode 100644
index 430a92b492f1..000000000000
--- a/arch/arm/mach-h720x/include/mach/irqs.h
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/irqs.h
3 *
4 * Copyright (C) 2000 Jungjun Kim
5 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
7 *
8 */
9
10#ifndef __ASM_ARCH_IRQS_H
11#define __ASM_ARCH_IRQS_H
12
13#if defined (CONFIG_CPU_H7201)
14
15#define IRQ_PMU 0 /* 0x000001 */
16#define IRQ_DMA 1 /* 0x000002 */
17#define IRQ_LCD 2 /* 0x000004 */
18#define IRQ_VGA 3 /* 0x000008 */
19#define IRQ_PCMCIA1 4 /* 0x000010 */
20#define IRQ_PCMCIA2 5 /* 0x000020 */
21#define IRQ_AFE 6 /* 0x000040 */
22#define IRQ_AIC 7 /* 0x000080 */
23#define IRQ_KEYBOARD 8 /* 0x000100 */
24#define IRQ_TIMER0 9 /* 0x000200 */
25#define IRQ_RTC 10 /* 0x000400 */
26#define IRQ_SOUND 11 /* 0x000800 */
27#define IRQ_USB 12 /* 0x001000 */
28#define IRQ_IrDA 13 /* 0x002000 */
29#define IRQ_UART0 14 /* 0x004000 */
30#define IRQ_UART1 15 /* 0x008000 */
31#define IRQ_SPI 16 /* 0x010000 */
32#define IRQ_GPIOA 17 /* 0x020000 */
33#define IRQ_GPIOB 18 /* 0x040000 */
34#define IRQ_GPIOC 19 /* 0x080000 */
35#define IRQ_GPIOD 20 /* 0x100000 */
36#define IRQ_CommRX 21 /* 0x200000 */
37#define IRQ_CommTX 22 /* 0x400000 */
38#define IRQ_Soft 23 /* 0x800000 */
39
40#define NR_GLBL_IRQS 24
41
42#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
43#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
44#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
45#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
46#define NR_IRQS IRQ_CHAINED_GPIOD(32)
47
48/* Enable mask for multiplexed interrupts */
49#define IRQ_ENA_MUX (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
50 | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
51
52
53#elif defined (CONFIG_CPU_H7202)
54
55#define IRQ_PMU 0 /* 0x00000001 */
56#define IRQ_DMA 1 /* 0x00000002 */
57#define IRQ_LCD 2 /* 0x00000004 */
58#define IRQ_SOUND 3 /* 0x00000008 */
59#define IRQ_I2S 4 /* 0x00000010 */
60#define IRQ_USB 5 /* 0x00000020 */
61#define IRQ_MMC 6 /* 0x00000040 */
62#define IRQ_RTC 7 /* 0x00000080 */
63#define IRQ_UART0 8 /* 0x00000100 */
64#define IRQ_UART1 9 /* 0x00000200 */
65#define IRQ_UART2 10 /* 0x00000400 */
66#define IRQ_UART3 11 /* 0x00000800 */
67#define IRQ_KBD 12 /* 0x00001000 */
68#define IRQ_PS2 13 /* 0x00002000 */
69#define IRQ_AIC 14 /* 0x00004000 */
70#define IRQ_TIMER0 15 /* 0x00008000 */
71#define IRQ_TIMERX 16 /* 0x00010000 */
72#define IRQ_WDT 17 /* 0x00020000 */
73#define IRQ_CAN0 18 /* 0x00040000 */
74#define IRQ_CAN1 19 /* 0x00080000 */
75#define IRQ_EXT0 20 /* 0x00100000 */
76#define IRQ_EXT1 21 /* 0x00200000 */
77#define IRQ_GPIOA 22 /* 0x00400000 */
78#define IRQ_GPIOB 23 /* 0x00800000 */
79#define IRQ_GPIOC 24 /* 0x01000000 */
80#define IRQ_GPIOD 25 /* 0x02000000 */
81#define IRQ_GPIOE 26 /* 0x04000000 */
82#define IRQ_COMMRX 27 /* 0x08000000 */
83#define IRQ_COMMTX 28 /* 0x10000000 */
84#define IRQ_SMC 29 /* 0x20000000 */
85#define IRQ_Soft 30 /* 0x40000000 */
86#define IRQ_RESERVED1 31 /* 0x80000000 */
87#define NR_GLBL_IRQS 32
88
89#define NR_TIMERX_IRQS 3
90
91#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
92#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
93#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
94#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
95#define IRQ_CHAINED_GPIOE(x) (IRQ_CHAINED_GPIOD(32) + x)
96#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
97#define IRQ_TIMER1 (IRQ_CHAINED_TIMERX(0))
98#define IRQ_TIMER2 (IRQ_CHAINED_TIMERX(1))
99#define IRQ_TIMER64B (IRQ_CHAINED_TIMERX(2))
100
101#define NR_IRQS (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
102
103/* Enable mask for multiplexed interrupts */
104#define IRQ_ENA_MUX (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
105 (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
106 (1<<IRQ_TIMERX)
107
108#else
109#error cpu definition mismatch
110#endif
111
112/* decode irq number to register number */
113#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
114#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
115
116#endif
diff --git a/arch/arm/mach-h720x/include/mach/isa-dma.h b/arch/arm/mach-h720x/include/mach/isa-dma.h
deleted file mode 100644
index 3eafb3f163c0..000000000000
--- a/arch/arm/mach-h720x/include/mach/isa-dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/isa-dma.h
3 *
4 * Architecture DMA routes
5 *
6 * Copyright (C) 1997.1998 Russell King
7 */
8#ifndef __ASM_ARCH_DMA_H
9#define __ASM_ARCH_DMA_H
10
11#if defined (CONFIG_CPU_H7201)
12#define MAX_DMA_CHANNELS 3
13#elif defined (CONFIG_CPU_H7202)
14#define MAX_DMA_CHANNELS 4
15#else
16#error processor definition missmatch
17#endif
18
19#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-h720x/include/mach/timex.h b/arch/arm/mach-h720x/include/mach/timex.h
deleted file mode 100644
index 3f2f447ff36b..000000000000
--- a/arch/arm/mach-h720x/include/mach/timex.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/timex.h
3 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef __ASM_ARCH_TIMEX
11#define __ASM_ARCH_TIMEX
12
13#define CLOCK_TICK_RATE 3686400
14
15#endif
diff --git a/arch/arm/mach-h720x/include/mach/uncompress.h b/arch/arm/mach-h720x/include/mach/uncompress.h
deleted file mode 100644
index 43e343c4b50a..000000000000
--- a/arch/arm/mach-h720x/include/mach/uncompress.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/uncompress.h
3 *
4 * Copyright (C) 2001-2002 Jungjun Kim
5 */
6
7#ifndef __ASM_ARCH_UNCOMPRESS_H
8#define __ASM_ARCH_UNCOMPRESS_H
9
10#include <mach/hardware.h>
11
12#define LSR 0x14
13#define TEMPTY 0x40
14
15static inline void putc(int c)
16{
17 volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
18
19 /* wait until transmit buffer is empty */
20 while((p[LSR] & TEMPTY) == 0x0)
21 barrier();
22
23 /* write next character */
24 *p = c;
25}
26
27static inline void flush(void)
28{
29}
30
31/*
32 * nothing to do
33 */
34#define arch_decomp_setup()
35
36#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 21:07:33 -0500