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-rw-r--r--arch/arm/mach-h720x/include/mach/boards.h53
-rw-r--r--arch/arm/mach-h720x/include/mach/debug-macro.S40
-rw-r--r--arch/arm/mach-h720x/include/mach/dma.h26
-rw-r--r--arch/arm/mach-h720x/include/mach/entry-macro.S66
-rw-r--r--arch/arm/mach-h720x/include/mach/h7201-regs.h67
-rw-r--r--arch/arm/mach-h720x/include/mach/h7202-regs.h155
-rw-r--r--arch/arm/mach-h720x/include/mach/hardware.h192
-rw-r--r--arch/arm/mach-h720x/include/mach/io.h24
-rw-r--r--arch/arm/mach-h720x/include/mach/irqs.h116
-rw-r--r--arch/arm/mach-h720x/include/mach/memory.h29
-rw-r--r--arch/arm/mach-h720x/include/mach/system.h33
-rw-r--r--arch/arm/mach-h720x/include/mach/timex.h15
-rw-r--r--arch/arm/mach-h720x/include/mach/uncompress.h37
-rw-r--r--arch/arm/mach-h720x/include/mach/vmalloc.h10
14 files changed, 863 insertions, 0 deletions
diff --git a/arch/arm/mach-h720x/include/mach/boards.h b/arch/arm/mach-h720x/include/mach/boards.h
new file mode 100644
index 000000000000..079b279e1242
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/boards.h
@@ -0,0 +1,53 @@
1/*
2 * arch/arm/mach-h720x/include/mach/boards.h
3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 *
7 * This file contains the board specific defines for various devices
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
15#error Do not include this file directly. Include asm/hardware.h instead !
16#endif
17
18/* Hynix H7202 developer board specific device defines */
19#ifdef CONFIG_ARCH_H7202
20
21/* FLASH */
22#define FLASH_VIRT 0xd0000000
23#define FLASH_PHYS 0x00000000
24#define FLASH_SIZE 0x02000000
25
26/* onboard LAN controller */
27# define ETH0_PHYS 0x08000000
28
29/* Touch screen defines */
30/* GPIO Port */
31#define PEN_GPIO GPIO_B_VIRT
32/* Bitmask for pen down interrupt */
33#define PEN_INT_BIT (1<<7)
34/* Bitmask for pen up interrupt */
35#define PEN_ENA_BIT (1<<6)
36/* pen up interrupt */
37#define IRQ_PEN IRQ_MUX_GPIOB(7)
38
39#endif
40
41/* Hynix H7201 developer board specific device defines */
42#if defined (CONFIG_ARCH_H7201)
43/* ROM DISK SPACE */
44#define ROM_DISK_BASE 0xc1800000
45#define ROM_DISK_START 0x41800000
46#define ROM_DISK_SIZE 0x00700000
47
48/* SRAM DISK SPACE */
49#define SRAM_DISK_BASE 0xf1000000
50#define SRAM_DISK_START 0x04000000
51#define SRAM_DISK_SIZE 0x00400000
52#endif
53
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
new file mode 100644
index 000000000000..6294a1344dda
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/debug-macro.S
@@ -0,0 +1,40 @@
1/* arch/arm/mach-h720x/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .equ io_virt, IO_BASE
15 .equ io_phys, IO_START
16
17 .macro addruart,rx
18 mrc p15, 0, \rx, c1, c0
19 tst \rx, #1 @ MMU enabled?
20 moveq \rx, #io_phys @ physical base address
21 movne \rx, #io_virt @ virtual address
22 add \rx, \rx, #0x00020000 @ UART1
23 .endm
24
25 .macro senduart,rd,rx
26 str \rd, [\rx, #0x0] @ UARTDR
27
28 .endm
29
30 .macro waituart,rd,rx
311001: ldr \rd, [\rx, #0x18] @ UARTFLG
32 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
33 bne 1001b
34 .endm
35
36 .macro busyuart,rd,rx
371001: ldr \rd, [\rx, #0x18] @ UARTFLG
38 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
39 bne 1001b
40 .endm
diff --git a/arch/arm/mach-h720x/include/mach/dma.h b/arch/arm/mach-h720x/include/mach/dma.h
new file mode 100644
index 000000000000..0a9d86ee84fe
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/dma.h
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-h720x/include/mach/dma.h
3 *
4 * Architecture DMA routes
5 *
6 * Copyright (C) 1997.1998 Russell King
7 */
8#ifndef __ASM_ARCH_DMA_H
9#define __ASM_ARCH_DMA_H
10
11/*
12 * This is the maximum DMA address that can be DMAd to.
13 * There should not be more than (0xd0000000 - 0xc0000000)
14 * bytes of RAM.
15 */
16#define MAX_DMA_ADDRESS 0xd0000000
17
18#if defined (CONFIG_CPU_H7201)
19#define MAX_DMA_CHANNELS 3
20#elif defined (CONFIG_CPU_H7202)
21#define MAX_DMA_CHANNELS 4
22#else
23#error processor definition missmatch
24#endif
25
26#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-h720x/include/mach/entry-macro.S b/arch/arm/mach-h720x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..6d3b917c4a18
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/entry-macro.S
@@ -0,0 +1,66 @@
1/*
2 * arch/arm/mach-h720x/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Hynix HMS720x based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 .macro disable_fiq
12 .endm
13
14 .macro get_irqnr_preamble, base, tmp
15 .endm
16
17 .macro arch_ret_to_user, tmp1, tmp2
18 .endm
19
20 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
21#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
22 @ we could use the id register on H7202, but this is not
23 @ properly updated when we come back from asm_do_irq
24 @ without a previous return from interrupt
25 @ (see loops below in irq_svc, irq_usr)
26 @ We see unmasked pending ints only, as the masked pending ints
27 @ are not visible here
28
29 mov \base, #0xf0000000 @ base register
30 orr \base, \base, #0x24000 @ irqbase
31 ldr \irqstat, [\base, #0x04] @ get interrupt status
32#if defined (CONFIG_CPU_H7201)
33 ldr \tmp, =0x001fffff
34#else
35 mvn \tmp, #0xc0000000
36#endif
37 and \irqstat, \irqstat, \tmp @ mask out unused ints
38 mov \irqnr, #0
39
40 mov \tmp, #0xff00
41 orr \tmp, \tmp, #0xff
42 tst \irqstat, \tmp
43 addeq \irqnr, \irqnr, #16
44 moveq \irqstat, \irqstat, lsr #16
45 tst \irqstat, #255
46 addeq \irqnr, \irqnr, #8
47 moveq \irqstat, \irqstat, lsr #8
48 tst \irqstat, #15
49 addeq \irqnr, \irqnr, #4
50 moveq \irqstat, \irqstat, lsr #4
51 tst \irqstat, #3
52 addeq \irqnr, \irqnr, #2
53 moveq \irqstat, \irqstat, lsr #2
54 tst \irqstat, #1
55 addeq \irqnr, \irqnr, #1
56 moveq \irqstat, \irqstat, lsr #1
57 tst \irqstat, #1 @ bit 0 should be set
58 .endm
59
60 .macro irq_prio_table
61 .endm
62
63#else
64#error hynix processor selection missmatch
65#endif
66
diff --git a/arch/arm/mach-h720x/include/mach/h7201-regs.h b/arch/arm/mach-h720x/include/mach/h7201-regs.h
new file mode 100644
index 000000000000..611b4947ccfc
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/h7201-regs.h
@@ -0,0 +1,67 @@
1/*
2 * arch/arm/mach-h720x/include/mach/h7201-regs.h
3 *
4 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
5 * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
6 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
7 * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
8 *
9 * This file contains the hardware definitions of the h720x processors
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * Do not add implementations specific defines here. This files contains
16 * only defines of the onchip peripherals. Add those defines to boards.h,
17 * which is included by this file.
18 */
19
20#define SERIAL2_VIRT (IO_VIRT + 0x50100)
21#define SERIAL3_VIRT (IO_VIRT + 0x50200)
22
23/*
24 * PCMCIA
25 */
26#define PCMCIA0_ATT_BASE 0xe5000000
27#define PCMCIA0_ATT_SIZE 0x00200000
28#define PCMCIA0_ATT_START 0x20000000
29#define PCMCIA0_MEM_BASE 0xe5200000
30#define PCMCIA0_MEM_SIZE 0x00200000
31#define PCMCIA0_MEM_START 0x24000000
32#define PCMCIA0_IO_BASE 0xe5400000
33#define PCMCIA0_IO_SIZE 0x00200000
34#define PCMCIA0_IO_START 0x28000000
35
36#define PCMCIA1_ATT_BASE 0xe5600000
37#define PCMCIA1_ATT_SIZE 0x00200000
38#define PCMCIA1_ATT_START 0x30000000
39#define PCMCIA1_MEM_BASE 0xe5800000
40#define PCMCIA1_MEM_SIZE 0x00200000
41#define PCMCIA1_MEM_START 0x34000000
42#define PCMCIA1_IO_BASE 0xe5a00000
43#define PCMCIA1_IO_SIZE 0x00200000
44#define PCMCIA1_IO_START 0x38000000
45
46#define PRIME3C_BASE 0xf0050000
47#define PRIME3C_SIZE 0x00001000
48#define PRIME3C_START 0x10000000
49
50/* VGA Controller */
51#define VGA_RAMBASE 0x50
52#define VGA_TIMING0 0x60
53#define VGA_TIMING1 0x64
54#define VGA_TIMING2 0x68
55#define VGA_TIMING3 0x6c
56
57#define LCD_CTRL_VGA_ENABLE 0x00000100
58#define LCD_CTRL_VGA_BPP_MASK 0x00000600
59#define LCD_CTRL_VGA_4BPP 0x00000000
60#define LCD_CTRL_VGA_8BPP 0x00000200
61#define LCD_CTRL_VGA_16BPP 0x00000300
62#define LCD_CTRL_SHARE_DMA 0x00000800
63#define LCD_CTRL_VDE 0x00100000
64#define LCD_CTRL_LPE 0x00400000 /* LCD Power enable */
65#define LCD_CTRL_BLE 0x00800000 /* LCD backlight enable */
66
67#define VGA_PALETTE_BASE (IO_VIRT + 0x10800)
diff --git a/arch/arm/mach-h720x/include/mach/h7202-regs.h b/arch/arm/mach-h720x/include/mach/h7202-regs.h
new file mode 100644
index 000000000000..17c12eb34995
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/h7202-regs.h
@@ -0,0 +1,155 @@
1/*
2 * arch/arm/mach-h720x/include/mach/h7202-regs.h
3 *
4 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
5 * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
6 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
7 * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
8 *
9 * This file contains the hardware definitions of the h720x processors
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * Do not add implementations specific defines here. This files contains
16 * only defines of the onchip peripherals. Add those defines to boards.h,
17 * which is included by this file.
18 */
19
20#define SERIAL2_OFS 0x2d000
21#define SERIAL2_BASE (IO_PHYS + SERIAL2_OFS)
22#define SERIAL2_VIRT (IO_VIRT + SERIAL2_OFS)
23#define SERIAL3_OFS 0x2e000
24#define SERIAL3_BASE (IO_PHYS + SERIAL3_OFS)
25#define SERIAL3_VIRT (IO_VIRT + SERIAL3_OFS)
26
27/* Matrix Keyboard Controller */
28#define KBD_VIRT (IO_VIRT + 0x22000)
29#define KBD_KBCR 0x00
30#define KBD_KBSC 0x04
31#define KBD_KBTR 0x08
32#define KBD_KBVR0 0x0C
33#define KBD_KBVR1 0x10
34#define KBD_KBSR 0x18
35
36#define KBD_KBCR_SCANENABLE (1 << 7)
37#define KBD_KBCR_NPOWERDOWN (1 << 2)
38#define KBD_KBCR_CLKSEL_MASK (3)
39#define KBD_KBCR_CLKSEL_PCLK2 0x0
40#define KBD_KBCR_CLKSEL_PCLK128 0x1
41#define KBD_KBCR_CLKSEL_PCLK256 0x2
42#define KBD_KBCR_CLKSEL_PCLK512 0x3
43
44#define KBD_KBSR_INTR (1 << 0)
45#define KBD_KBSR_WAKEUP (1 << 1)
46
47/* USB device controller */
48
49#define USBD_BASE (IO_VIRT + 0x12000)
50#define USBD_LENGTH 0x3C
51
52#define USBD_GCTRL 0x00
53#define USBD_EPCTRL 0x04
54#define USBD_INTMASK 0x08
55#define USBD_INTSTAT 0x0C
56#define USBD_PWR 0x10
57#define USBD_DMARXTX 0x14
58#define USBD_DEVID 0x18
59#define USBD_DEVCLASS 0x1C
60#define USBD_INTCLASS 0x20
61#define USBD_SETUP0 0x24
62#define USBD_SETUP1 0x28
63#define USBD_ENDP0RD 0x2C
64#define USBD_ENDP0WT 0x30
65#define USBD_ENDP1RD 0x34
66#define USBD_ENDP2WT 0x38
67
68/* PS/2 port */
69#define PSDATA 0x00
70#define PSSTAT 0x04
71#define PSSTAT_TXEMPTY (1<<0)
72#define PSSTAT_TXBUSY (1<<1)
73#define PSSTAT_RXFULL (1<<2)
74#define PSSTAT_RXBUSY (1<<3)
75#define PSSTAT_CLKIN (1<<4)
76#define PSSTAT_DATAIN (1<<5)
77#define PSSTAT_PARITY (1<<6)
78
79#define PSCONF 0x08
80#define PSCONF_ENABLE (1<<0)
81#define PSCONF_TXINTEN (1<<2)
82#define PSCONF_RXINTEN (1<<3)
83#define PSCONF_FORCECLKLOW (1<<4)
84#define PSCONF_FORCEDATLOW (1<<5)
85#define PSCONF_LCE (1<<6)
86
87#define PSINTR 0x0C
88#define PSINTR_TXINT (1<<0)
89#define PSINTR_RXINT (1<<1)
90#define PSINTR_PAR (1<<2)
91#define PSINTR_RXTO (1<<3)
92#define PSINTR_TXTO (1<<4)
93
94#define PSTDLO 0x10 /* clk low before start transmission */
95#define PSTPRI 0x14 /* PRI clock */
96#define PSTXMT 0x18 /* maximum transmission time */
97#define PSTREC 0x20 /* maximum receive time */
98#define PSPWDN 0x3c
99
100/* ADC converter */
101#define ADC_BASE (IO_VIRT + 0x29000)
102#define ADC_CR 0x00
103#define ADC_TSCTRL 0x04
104#define ADC_BT_CTRL 0x08
105#define ADC_MC_CTRL 0x0C
106#define ADC_STATUS 0x10
107
108/* ADC control register bits */
109#define ADC_CR_PW_CTRL 0x80
110#define ADC_CR_DIRECTC 0x04
111#define ADC_CR_CONTIME_NO 0x00
112#define ADC_CR_CONTIME_2 0x04
113#define ADC_CR_CONTIME_4 0x08
114#define ADC_CR_CONTIME_ADE 0x0c
115#define ADC_CR_LONGCALTIME 0x01
116
117/* ADC touch panel register bits */
118#define ADC_TSCTRL_ENABLE 0x80
119#define ADC_TSCTRL_INTR 0x40
120#define ADC_TSCTRL_SWBYPSS 0x20
121#define ADC_TSCTRL_SWINVT 0x10
122#define ADC_TSCTRL_S400 0x03
123#define ADC_TSCTRL_S200 0x02
124#define ADC_TSCTRL_S100 0x01
125#define ADC_TSCTRL_S50 0x00
126
127/* ADC Interrupt Status Register bits */
128#define ADC_STATUS_TS_BIT 0x80
129#define ADC_STATUS_MBT_BIT 0x40
130#define ADC_STATUS_BBT_BIT 0x20
131#define ADC_STATUS_MIC_BIT 0x10
132
133/* Touch data registers */
134#define ADC_TS_X0X1 0x30
135#define ADC_TS_X2X3 0x34
136#define ADC_TS_Y0Y1 0x38
137#define ADC_TS_Y2Y3 0x3c
138#define ADC_TS_X4X5 0x40
139#define ADC_TS_X6X7 0x44
140#define ADC_TS_Y4Y5 0x48
141#define ADC_TS_Y6Y7 0x50
142
143/* battery data */
144#define ADC_MB_DATA 0x54
145#define ADC_BB_DATA 0x58
146
147/* Sound data register */
148#define ADC_SD_DAT0 0x60
149#define ADC_SD_DAT1 0x64
150#define ADC_SD_DAT2 0x68
151#define ADC_SD_DAT3 0x6c
152#define ADC_SD_DAT4 0x70
153#define ADC_SD_DAT5 0x74
154#define ADC_SD_DAT6 0x78
155#define ADC_SD_DAT7 0x7c
diff --git a/arch/arm/mach-h720x/include/mach/hardware.h b/arch/arm/mach-h720x/include/mach/hardware.h
new file mode 100644
index 000000000000..6c19156e2a42
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/hardware.h
@@ -0,0 +1,192 @@
1/*
2 * arch/arm/mach-h720x/include/mach/hardware.h
3 *
4 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
5 * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
6 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
7 *
8 * This file contains the hardware definitions of the h720x processors
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Do not add implementations specific defines here. This files contains
15 * only defines of the onchip peripherals. Add those defines to boards.h,
16 * which is included by this file.
17 */
18
19#ifndef __ASM_ARCH_HARDWARE_H
20#define __ASM_ARCH_HARDWARE_H
21
22#define IOCLK (3686400L)
23
24/* Onchip peripherals */
25
26#define IO_VIRT 0xf0000000 /* IO peripherals */
27#define IO_PHYS 0x80000000
28#define IO_SIZE 0x00050000
29
30#ifdef CONFIG_CPU_H7202
31#include "h7202-regs.h"
32#elif defined CONFIG_CPU_H7201
33#include "h7201-regs.h"
34#else
35#error machine definition mismatch
36#endif
37
38/* Macro to access the CPU IO */
39#define CPU_IO(x) (*(volatile u32*)(x))
40
41/* Macro to access general purpose regs (base, offset) */
42#define CPU_REG(x,y) CPU_IO(x+y)
43
44/* Macro to access irq related regs */
45#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
46
47/* CPU registers */
48/* general purpose I/O */
49#define GPIO_VIRT(x) (IO_VIRT + 0x23000 + ((x)<<5))
50#define GPIO_A_VIRT (GPIO_VIRT(0))
51#define GPIO_B_VIRT (GPIO_VIRT(1))
52#define GPIO_C_VIRT (GPIO_VIRT(2))
53#define GPIO_D_VIRT (GPIO_VIRT(3))
54#define GPIO_E_VIRT (GPIO_VIRT(4))
55#define GPIO_AMULSEL (GPIO_VIRT(0) + 0xA4)
56
57#define AMULSEL_USIN2 (1<<5)
58#define AMULSEL_USOUT2 (1<<6)
59#define AMULSEL_USIN3 (1<<13)
60#define AMULSEL_USOUT3 (1<<14)
61#define AMULSEL_IRDIN (1<<15)
62#define AMULSEL_IRDOUT (1<<7)
63
64/* Register offsets general purpose I/O */
65#define GPIO_DATA 0x00
66#define GPIO_DIR 0x04
67#define GPIO_MASK 0x08
68#define GPIO_STAT 0x0C
69#define GPIO_EDGE 0x10
70#define GPIO_CLR 0x14
71#define GPIO_POL 0x18
72#define GPIO_EN 0x1C
73
74/*interrupt controller */
75#define IRQC_VIRT (IO_VIRT + 0x24000)
76/* register offset interrupt controller */
77#define IRQC_IER 0x00
78#define IRQC_ISR 0x04
79
80/* timer unit */
81#define TIMER_VIRT (IO_VIRT + 0x25000)
82/* Register offsets timer unit */
83#define TM0_PERIOD 0x00
84#define TM0_COUNT 0x08
85#define TM0_CTRL 0x10
86#define TM1_PERIOD 0x20
87#define TM1_COUNT 0x28
88#define TM1_CTRL 0x30
89#define TM2_PERIOD 0x40
90#define TM2_COUNT 0x48
91#define TM2_CTRL 0x50
92#define TIMER_TOPCTRL 0x60
93#define TIMER_TOPSTAT 0x64
94#define T64_COUNTL 0x80
95#define T64_COUNTH 0x84
96#define T64_CTRL 0x88
97#define T64_BASEL 0x94
98#define T64_BASEH 0x98
99/* Bitmaks timer unit TOPSTAT reg */
100#define TSTAT_T0INT 0x1
101#define TSTAT_T1INT 0x2
102#define TSTAT_T2INT 0x4
103#define TSTAT_T3INT 0x8
104/* Bit description of TMx_CTRL register */
105#define TM_START 0x1
106#define TM_REPEAT 0x2
107#define TM_RESET 0x4
108/* Bit description of TIMER_CTRL register */
109#define ENABLE_TM0_INTR 0x1
110#define ENABLE_TM1_INTR 0x2
111#define ENABLE_TM2_INTR 0x4
112#define TIMER_ENABLE_BIT 0x8
113#define ENABLE_TIMER64 0x10
114#define ENABLE_TIMER64_INT 0x20
115
116/* PMU & PLL */
117#define PMU_BASE (IO_VIRT + 0x1000)
118#define PMU_MODE 0x00
119#define PMU_STAT 0x20
120#define PMU_PLL_CTRL 0x28
121
122/* PMU Mode bits */
123#define PMU_MODE_SLOW 0x00
124#define PMU_MODE_RUN 0x01
125#define PMU_MODE_IDLE 0x02
126#define PMU_MODE_SLEEP 0x03
127#define PMU_MODE_INIT 0x04
128#define PMU_MODE_DEEPSLEEP 0x07
129#define PMU_MODE_WAKEUP 0x08
130
131/* PMU ... */
132#define PLL_2_EN 0x8000
133#define PLL_1_EN 0x4000
134#define PLL_3_MUTE 0x0080
135
136/* Control bits for PMU/ PLL */
137#define PMU_WARMRESET 0x00010000
138#define PLL_CTRL_MASK23 0x000080ff
139
140/* LCD Controller */
141#define LCD_BASE (IO_VIRT + 0x10000)
142#define LCD_CTRL 0x00
143#define LCD_STATUS 0x04
144#define LCD_STATUS_M 0x08
145#define LCD_INTERRUPT 0x0C
146#define LCD_DBAR 0x10
147#define LCD_DCAR 0x14
148#define LCD_TIMING0 0x20
149#define LCD_TIMING1 0x24
150#define LCD_TIMING2 0x28
151#define LCD_TEST 0x40
152
153/* LCD Control Bits */
154#define LCD_CTRL_LCD_ENABLE 0x00000001
155/* Bits per pixel */
156#define LCD_CTRL_LCD_BPP_MASK 0x00000006
157#define LCD_CTRL_LCD_4BPP 0x00000000
158#define LCD_CTRL_LCD_8BPP 0x00000002
159#define LCD_CTRL_LCD_16BPP 0x00000004
160#define LCD_CTRL_LCD_BW 0x00000008
161#define LCD_CTRL_LCD_TFT 0x00000010
162#define LCD_CTRL_BGR 0x00001000
163#define LCD_CTRL_LCD_VCOMP 0x00080000
164#define LCD_CTRL_LCD_MONO8 0x00200000
165#define LCD_CTRL_LCD_PWR 0x00400000
166#define LCD_CTRL_LCD_BLE 0x00800000
167#define LCD_CTRL_LDBUSEN 0x01000000
168
169/* Palette */
170#define LCD_PALETTE_BASE (IO_VIRT + 0x10400)
171
172/* Serial ports */
173#define SERIAL0_OFS 0x20000
174#define SERIAL0_VIRT (IO_VIRT + SERIAL0_OFS)
175#define SERIAL0_BASE (IO_PHYS + SERIAL0_OFS)
176
177#define SERIAL1_OFS 0x21000
178#define SERIAL1_VIRT (IO_VIRT + SERIAL1_OFS)
179#define SERIAL1_BASE (IO_PHYS + SERIAL1_OFS)
180
181#define SERIAL_ENABLE 0x30
182#define SERIAL_ENABLE_EN (1<<0)
183
184/* General defines to pacify gcc */
185#define PCIO_BASE (0) /* for inb, outb and friends */
186#define PCIO_VIRT PCIO_BASE
187
188#define __ASM_ARCH_HARDWARE_INCMACH_H
189#include "boards.h"
190#undef __ASM_ARCH_HARDWARE_INCMACH_H
191
192#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-h720x/include/mach/io.h b/arch/arm/mach-h720x/include/mach/io.h
new file mode 100644
index 000000000000..1dab74ce88c6
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/io.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/mach-h720x/include/mach/io.h
3 *
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 *
6 * Changelog:
7 *
8 * 09-19-2001 JJKIM
9 * Created from arch/arm/mach-l7200/include/mach/io.h
10 *
11 * 03-27-2003 Robert Schwebel <r.schwebel@pengutronix.de>:
12 * re-unified header files for h720x
13 */
14#ifndef __ASM_ARM_ARCH_IO_H
15#define __ASM_ARM_ARCH_IO_H
16
17#include <mach/hardware.h>
18
19#define IO_SPACE_LIMIT 0xffffffff
20
21#define __io(a) ((void __iomem *)(a))
22#define __mem_pci(a) (a)
23
24#endif
diff --git a/arch/arm/mach-h720x/include/mach/irqs.h b/arch/arm/mach-h720x/include/mach/irqs.h
new file mode 100644
index 000000000000..430a92b492f1
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/irqs.h
@@ -0,0 +1,116 @@
1/*
2 * arch/arm/mach-h720x/include/mach/irqs.h
3 *
4 * Copyright (C) 2000 Jungjun Kim
5 * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * (C) 2003 Thomas Gleixner <tglx@linutronix.de>
7 *
8 */
9
10#ifndef __ASM_ARCH_IRQS_H
11#define __ASM_ARCH_IRQS_H
12
13#if defined (CONFIG_CPU_H7201)
14
15#define IRQ_PMU 0 /* 0x000001 */
16#define IRQ_DMA 1 /* 0x000002 */
17#define IRQ_LCD 2 /* 0x000004 */
18#define IRQ_VGA 3 /* 0x000008 */
19#define IRQ_PCMCIA1 4 /* 0x000010 */
20#define IRQ_PCMCIA2 5 /* 0x000020 */
21#define IRQ_AFE 6 /* 0x000040 */
22#define IRQ_AIC 7 /* 0x000080 */
23#define IRQ_KEYBOARD 8 /* 0x000100 */
24#define IRQ_TIMER0 9 /* 0x000200 */
25#define IRQ_RTC 10 /* 0x000400 */
26#define IRQ_SOUND 11 /* 0x000800 */
27#define IRQ_USB 12 /* 0x001000 */
28#define IRQ_IrDA 13 /* 0x002000 */
29#define IRQ_UART0 14 /* 0x004000 */
30#define IRQ_UART1 15 /* 0x008000 */
31#define IRQ_SPI 16 /* 0x010000 */
32#define IRQ_GPIOA 17 /* 0x020000 */
33#define IRQ_GPIOB 18 /* 0x040000 */
34#define IRQ_GPIOC 19 /* 0x080000 */
35#define IRQ_GPIOD 20 /* 0x100000 */
36#define IRQ_CommRX 21 /* 0x200000 */
37#define IRQ_CommTX 22 /* 0x400000 */
38#define IRQ_Soft 23 /* 0x800000 */
39
40#define NR_GLBL_IRQS 24
41
42#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
43#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
44#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
45#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
46#define NR_IRQS IRQ_CHAINED_GPIOD(32)
47
48/* Enable mask for multiplexed interrupts */
49#define IRQ_ENA_MUX (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
50 | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
51
52
53#elif defined (CONFIG_CPU_H7202)
54
55#define IRQ_PMU 0 /* 0x00000001 */
56#define IRQ_DMA 1 /* 0x00000002 */
57#define IRQ_LCD 2 /* 0x00000004 */
58#define IRQ_SOUND 3 /* 0x00000008 */
59#define IRQ_I2S 4 /* 0x00000010 */
60#define IRQ_USB 5 /* 0x00000020 */
61#define IRQ_MMC 6 /* 0x00000040 */
62#define IRQ_RTC 7 /* 0x00000080 */
63#define IRQ_UART0 8 /* 0x00000100 */
64#define IRQ_UART1 9 /* 0x00000200 */
65#define IRQ_UART2 10 /* 0x00000400 */
66#define IRQ_UART3 11 /* 0x00000800 */
67#define IRQ_KBD 12 /* 0x00001000 */
68#define IRQ_PS2 13 /* 0x00002000 */
69#define IRQ_AIC 14 /* 0x00004000 */
70#define IRQ_TIMER0 15 /* 0x00008000 */
71#define IRQ_TIMERX 16 /* 0x00010000 */
72#define IRQ_WDT 17 /* 0x00020000 */
73#define IRQ_CAN0 18 /* 0x00040000 */
74#define IRQ_CAN1 19 /* 0x00080000 */
75#define IRQ_EXT0 20 /* 0x00100000 */
76#define IRQ_EXT1 21 /* 0x00200000 */
77#define IRQ_GPIOA 22 /* 0x00400000 */
78#define IRQ_GPIOB 23 /* 0x00800000 */
79#define IRQ_GPIOC 24 /* 0x01000000 */
80#define IRQ_GPIOD 25 /* 0x02000000 */
81#define IRQ_GPIOE 26 /* 0x04000000 */
82#define IRQ_COMMRX 27 /* 0x08000000 */
83#define IRQ_COMMTX 28 /* 0x10000000 */
84#define IRQ_SMC 29 /* 0x20000000 */
85#define IRQ_Soft 30 /* 0x40000000 */
86#define IRQ_RESERVED1 31 /* 0x80000000 */
87#define NR_GLBL_IRQS 32
88
89#define NR_TIMERX_IRQS 3
90
91#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
92#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
93#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
94#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
95#define IRQ_CHAINED_GPIOE(x) (IRQ_CHAINED_GPIOD(32) + x)
96#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
97#define IRQ_TIMER1 (IRQ_CHAINED_TIMERX(0))
98#define IRQ_TIMER2 (IRQ_CHAINED_TIMERX(1))
99#define IRQ_TIMER64B (IRQ_CHAINED_TIMERX(2))
100
101#define NR_IRQS (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
102
103/* Enable mask for multiplexed interrupts */
104#define IRQ_ENA_MUX (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
105 (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
106 (1<<IRQ_TIMERX)
107
108#else
109#error cpu definition mismatch
110#endif
111
112/* decode irq number to register number */
113#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
114#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
115
116#endif
diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h
new file mode 100644
index 000000000000..cb26f49cc4e1
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/memory.h
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-h720x/include/mach/memory.h
3 *
4 * Copyright (c) 2000 Jungjun Kim
5 *
6 */
7#ifndef __ASM_ARCH_MEMORY_H
8#define __ASM_ARCH_MEMORY_H
9
10/*
11 * Page offset:
12 * ( 0xc0000000UL )
13 */
14#define PHYS_OFFSET UL(0x40000000)
15
16/*
17 * Virtual view <-> DMA view memory address translations
18 * virt_to_bus: Used to translate the virtual address to an
19 * address suitable to be passed to set_dma_addr
20 * bus_to_virt: Used to convert an address for DMA operations
21 * to an address that the kernel can use.
22 *
23 * There is something to do here later !, Mar 2000, Jungjun Kim
24 */
25
26#define __virt_to_bus(x) __virt_to_phys(x)
27#define __bus_to_virt(x) __phys_to_virt(x)
28
29#endif
diff --git a/arch/arm/mach-h720x/include/mach/system.h b/arch/arm/mach-h720x/include/mach/system.h
new file mode 100644
index 000000000000..e4a7c760d52a
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/system.h
@@ -0,0 +1,33 @@
1/*
2 * arch/arm/mach-h720x/include/mach/system.h
3 *
4 * Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 * arch/arm/mach-h720x/include/mach/system.h
10 *
11 */
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H
15#include <mach/hardware.h>
16
17static void arch_idle(void)
18{
19 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
20 nop();
21 nop();
22 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
23 nop();
24 nop();
25}
26
27
28static __inline__ void arch_reset(char mode)
29{
30 CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
31}
32
33#endif
diff --git a/arch/arm/mach-h720x/include/mach/timex.h b/arch/arm/mach-h720x/include/mach/timex.h
new file mode 100644
index 000000000000..3f2f447ff36b
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/timex.h
@@ -0,0 +1,15 @@
1/*
2 * arch/arm/mach-h720x/include/mach/timex.h
3 * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef __ASM_ARCH_TIMEX
11#define __ASM_ARCH_TIMEX
12
13#define CLOCK_TICK_RATE 3686400
14
15#endif
diff --git a/arch/arm/mach-h720x/include/mach/uncompress.h b/arch/arm/mach-h720x/include/mach/uncompress.h
new file mode 100644
index 000000000000..d6623234f61e
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/uncompress.h
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/mach-h720x/include/mach/uncompress.h
3 *
4 * Copyright (C) 2001-2002 Jungjun Kim
5 */
6
7#ifndef __ASM_ARCH_UNCOMPRESS_H
8#define __ASM_ARCH_UNCOMPRESS_H
9
10#include <mach/hardware.h>
11
12#define LSR 0x14
13#define TEMPTY 0x40
14
15static inline void putc(int c)
16{
17 volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
18
19 /* wait until transmit buffer is empty */
20 while((p[LSR] & TEMPTY) == 0x0)
21 barrier();
22
23 /* write next character */
24 *p = c;
25}
26
27static inline void flush(void)
28{
29}
30
31/*
32 * nothing to do
33 */
34#define arch_decomp_setup()
35#define arch_decomp_wdog()
36
37#endif
diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..ff1460d6841b
--- /dev/null
+++ b/arch/arm/mach-h720x/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
1/*
2 * arch/arm/mach-h720x/include/mach/vmalloc.h
3 */
4
5#ifndef __ARCH_ARM_VMALLOC_H
6#define __ARCH_ARM_VMALLOC_H
7
8#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
9
10#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 21:06:25 -0500