diff options
Diffstat (limited to 'arch/arm/mach-h720x/common.c')
-rw-r--r-- | arch/arm/mach-h720x/common.c | 29 |
1 files changed, 12 insertions, 17 deletions
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index c096b4569308..4719229a1a78 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c | |||
@@ -101,14 +101,14 @@ static void inline unmask_gpio_irq(u32 irq) | |||
101 | 101 | ||
102 | static void | 102 | static void |
103 | h720x_gpio_handler(unsigned int mask, unsigned int irq, | 103 | h720x_gpio_handler(unsigned int mask, unsigned int irq, |
104 | struct irqdesc *desc, struct pt_regs *regs) | 104 | struct irqdesc *desc) |
105 | { | 105 | { |
106 | IRQDBG("%s irq: %d\n",__FUNCTION__,irq); | 106 | IRQDBG("%s irq: %d\n",__FUNCTION__,irq); |
107 | desc = irq_desc + irq; | 107 | desc = irq_desc + irq; |
108 | while (mask) { | 108 | while (mask) { |
109 | if (mask & 1) { | 109 | if (mask & 1) { |
110 | IRQDBG("handling irq %d\n", irq); | 110 | IRQDBG("handling irq %d\n", irq); |
111 | desc_handle_irq(irq, desc, regs); | 111 | desc_handle_irq(irq, desc); |
112 | } | 112 | } |
113 | irq++; | 113 | irq++; |
114 | desc++; | 114 | desc++; |
@@ -117,63 +117,58 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq, | |||
117 | } | 117 | } |
118 | 118 | ||
119 | static void | 119 | static void |
120 | h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc, | 120 | h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc) |
121 | struct pt_regs *regs) | ||
122 | { | 121 | { |
123 | unsigned int mask, irq; | 122 | unsigned int mask, irq; |
124 | 123 | ||
125 | mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT); | 124 | mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT); |
126 | irq = IRQ_CHAINED_GPIOA(0); | 125 | irq = IRQ_CHAINED_GPIOA(0); |
127 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); | 126 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); |
128 | h720x_gpio_handler(mask, irq, desc, regs); | 127 | h720x_gpio_handler(mask, irq, desc); |
129 | } | 128 | } |
130 | 129 | ||
131 | static void | 130 | static void |
132 | h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc, | 131 | h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc) |
133 | struct pt_regs *regs) | ||
134 | { | 132 | { |
135 | unsigned int mask, irq; | 133 | unsigned int mask, irq; |
136 | mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); | 134 | mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); |
137 | irq = IRQ_CHAINED_GPIOB(0); | 135 | irq = IRQ_CHAINED_GPIOB(0); |
138 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); | 136 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); |
139 | h720x_gpio_handler(mask, irq, desc, regs); | 137 | h720x_gpio_handler(mask, irq, desc); |
140 | } | 138 | } |
141 | 139 | ||
142 | static void | 140 | static void |
143 | h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc, | 141 | h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc) |
144 | struct pt_regs *regs) | ||
145 | { | 142 | { |
146 | unsigned int mask, irq; | 143 | unsigned int mask, irq; |
147 | 144 | ||
148 | mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT); | 145 | mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT); |
149 | irq = IRQ_CHAINED_GPIOC(0); | 146 | irq = IRQ_CHAINED_GPIOC(0); |
150 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); | 147 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); |
151 | h720x_gpio_handler(mask, irq, desc, regs); | 148 | h720x_gpio_handler(mask, irq, desc); |
152 | } | 149 | } |
153 | 150 | ||
154 | static void | 151 | static void |
155 | h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc, | 152 | h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc) |
156 | struct pt_regs *regs) | ||
157 | { | 153 | { |
158 | unsigned int mask, irq; | 154 | unsigned int mask, irq; |
159 | 155 | ||
160 | mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT); | 156 | mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT); |
161 | irq = IRQ_CHAINED_GPIOD(0); | 157 | irq = IRQ_CHAINED_GPIOD(0); |
162 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); | 158 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); |
163 | h720x_gpio_handler(mask, irq, desc, regs); | 159 | h720x_gpio_handler(mask, irq, desc); |
164 | } | 160 | } |
165 | 161 | ||
166 | #ifdef CONFIG_CPU_H7202 | 162 | #ifdef CONFIG_CPU_H7202 |
167 | static void | 163 | static void |
168 | h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc, | 164 | h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc) |
169 | struct pt_regs *regs) | ||
170 | { | 165 | { |
171 | unsigned int mask, irq; | 166 | unsigned int mask, irq; |
172 | 167 | ||
173 | mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT); | 168 | mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT); |
174 | irq = IRQ_CHAINED_GPIOE(0); | 169 | irq = IRQ_CHAINED_GPIOE(0); |
175 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); | 170 | IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); |
176 | h720x_gpio_handler(mask, irq, desc, regs); | 171 | h720x_gpio_handler(mask, irq, desc); |
177 | } | 172 | } |
178 | #endif | 173 | #endif |
179 | 174 | ||