diff options
Diffstat (limited to 'arch/arm/mach-footbridge/isa-timer.c')
-rw-r--r-- | arch/arm/mach-footbridge/isa-timer.c | 129 |
1 files changed, 85 insertions, 44 deletions
diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c index f488fa2082d7..441c6ce0d555 100644 --- a/arch/arm/mach-footbridge/isa-timer.c +++ b/arch/arm/mach-footbridge/isa-timer.c | |||
@@ -4,10 +4,13 @@ | |||
4 | * Copyright (C) 1998 Russell King. | 4 | * Copyright (C) 1998 Russell King. |
5 | * Copyright (C) 1998 Phil Blundell | 5 | * Copyright (C) 1998 Phil Blundell |
6 | */ | 6 | */ |
7 | #include <linux/clockchips.h> | ||
8 | #include <linux/clocksource.h> | ||
7 | #include <linux/init.h> | 9 | #include <linux/init.h> |
8 | #include <linux/interrupt.h> | 10 | #include <linux/interrupt.h> |
9 | #include <linux/irq.h> | 11 | #include <linux/irq.h> |
10 | #include <linux/io.h> | 12 | #include <linux/io.h> |
13 | #include <linux/timex.h> | ||
11 | 14 | ||
12 | #include <asm/irq.h> | 15 | #include <asm/irq.h> |
13 | 16 | ||
@@ -15,77 +18,115 @@ | |||
15 | 18 | ||
16 | #include "common.h" | 19 | #include "common.h" |
17 | 20 | ||
18 | /* | 21 | #define PIT_MODE 0x43 |
19 | * ISA timer tick support | 22 | #define PIT_CH0 0x40 |
20 | */ | 23 | |
21 | #define mSEC_10_from_14 ((14318180 + 100) / 200) | 24 | #define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ) |
22 | 25 | ||
23 | static unsigned long isa_gettimeoffset(void) | 26 | static cycle_t pit_read(struct clocksource *cs) |
24 | { | 27 | { |
28 | unsigned long flags; | ||
29 | static int old_count; | ||
30 | static u32 old_jifs; | ||
25 | int count; | 31 | int count; |
32 | u32 jifs; | ||
26 | 33 | ||
27 | static int count_p = (mSEC_10_from_14/6); /* for the first call after boot */ | 34 | raw_local_irq_save(flags); |
28 | static unsigned long jiffies_p = 0; | ||
29 | 35 | ||
30 | /* | 36 | jifs = jiffies; |
31 | * cache volatile jiffies temporarily; we have IRQs turned off. | 37 | outb_p(0x00, PIT_MODE); /* latch the count */ |
32 | */ | 38 | count = inb_p(PIT_CH0); /* read the latched count */ |
33 | unsigned long jiffies_t; | 39 | count |= inb_p(PIT_CH0) << 8; |
34 | 40 | ||
35 | /* timer count may underflow right here */ | 41 | if (count > old_count && jifs == old_jifs) |
36 | outb_p(0x00, 0x43); /* latch the count ASAP */ | 42 | count = old_count; |
37 | 43 | ||
38 | count = inb_p(0x40); /* read the latched count */ | 44 | old_count = count; |
45 | old_jifs = jifs; | ||
39 | 46 | ||
40 | /* | 47 | raw_local_irq_restore(flags); |
41 | * We do this guaranteed double memory access instead of a _p | ||
42 | * postfix in the previous port access. Wheee, hackady hack | ||
43 | */ | ||
44 | jiffies_t = jiffies; | ||
45 | 48 | ||
46 | count |= inb_p(0x40) << 8; | 49 | count = (PIT_LATCH - 1) - count; |
47 | 50 | ||
48 | /* Detect timer underflows. If we haven't had a timer tick since | 51 | return (cycle_t)(jifs * PIT_LATCH) + count; |
49 | the last time we were called, and time is apparently going | 52 | } |
50 | backwards, the counter must have wrapped during this routine. */ | ||
51 | if ((jiffies_t == jiffies_p) && (count > count_p)) | ||
52 | count -= (mSEC_10_from_14/6); | ||
53 | else | ||
54 | jiffies_p = jiffies_t; | ||
55 | 53 | ||
56 | count_p = count; | 54 | static struct clocksource pit_cs = { |
55 | .name = "pit", | ||
56 | .rating = 110, | ||
57 | .read = pit_read, | ||
58 | .mask = CLOCKSOURCE_MASK(32), | ||
59 | }; | ||
57 | 60 | ||
58 | count = (((mSEC_10_from_14/6)-1) - count) * (tick_nsec / 1000); | 61 | static void pit_set_mode(enum clock_event_mode mode, |
59 | count = (count + (mSEC_10_from_14/6)/2) / (mSEC_10_from_14/6); | 62 | struct clock_event_device *evt) |
63 | { | ||
64 | unsigned long flags; | ||
65 | |||
66 | raw_local_irq_save(flags); | ||
67 | |||
68 | switch (mode) { | ||
69 | case CLOCK_EVT_MODE_PERIODIC: | ||
70 | outb_p(0x34, PIT_MODE); | ||
71 | outb_p(PIT_LATCH & 0xff, PIT_CH0); | ||
72 | outb_p(PIT_LATCH >> 8, PIT_CH0); | ||
73 | break; | ||
74 | |||
75 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
76 | case CLOCK_EVT_MODE_UNUSED: | ||
77 | outb_p(0x30, PIT_MODE); | ||
78 | outb_p(0, PIT_CH0); | ||
79 | outb_p(0, PIT_CH0); | ||
80 | break; | ||
81 | |||
82 | case CLOCK_EVT_MODE_ONESHOT: | ||
83 | case CLOCK_EVT_MODE_RESUME: | ||
84 | break; | ||
85 | } | ||
86 | local_irq_restore(flags); | ||
87 | } | ||
60 | 88 | ||
61 | return count; | 89 | static int pit_set_next_event(unsigned long delta, |
90 | struct clock_event_device *evt) | ||
91 | { | ||
92 | return 0; | ||
62 | } | 93 | } |
63 | 94 | ||
64 | static irqreturn_t | 95 | static struct clock_event_device pit_ce = { |
65 | isa_timer_interrupt(int irq, void *dev_id) | 96 | .name = "pit", |
97 | .features = CLOCK_EVT_FEAT_PERIODIC, | ||
98 | .set_mode = pit_set_mode, | ||
99 | .set_next_event = pit_set_next_event, | ||
100 | .shift = 32, | ||
101 | }; | ||
102 | |||
103 | static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) | ||
66 | { | 104 | { |
67 | timer_tick(); | 105 | struct clock_event_device *ce = dev_id; |
106 | ce->event_handler(ce); | ||
68 | return IRQ_HANDLED; | 107 | return IRQ_HANDLED; |
69 | } | 108 | } |
70 | 109 | ||
71 | static struct irqaction isa_timer_irq = { | 110 | static struct irqaction pit_timer_irq = { |
72 | .name = "ISA timer tick", | 111 | .name = "pit", |
73 | .handler = isa_timer_interrupt, | 112 | .handler = pit_timer_interrupt, |
74 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 113 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
114 | .dev_id = &pit_ce, | ||
75 | }; | 115 | }; |
76 | 116 | ||
77 | static void __init isa_timer_init(void) | 117 | static void __init isa_timer_init(void) |
78 | { | 118 | { |
79 | /* enable PIT timer */ | 119 | pit_ce.cpumask = cpumask_of(smp_processor_id()); |
80 | /* set for periodic (4) and LSB/MSB write (0x30) */ | 120 | pit_ce.mult = div_sc(PIT_TICK_RATE, NSEC_PER_SEC, pit_ce.shift); |
81 | outb(0x34, 0x43); | 121 | pit_ce.max_delta_ns = clockevent_delta2ns(0x7fff, &pit_ce); |
82 | outb((mSEC_10_from_14/6) & 0xFF, 0x40); | 122 | pit_ce.min_delta_ns = clockevent_delta2ns(0x000f, &pit_ce); |
83 | outb((mSEC_10_from_14/6) >> 8, 0x40); | 123 | |
124 | clocksource_register_hz(&pit_cs, PIT_TICK_RATE); | ||
84 | 125 | ||
85 | setup_irq(IRQ_ISA_TIMER, &isa_timer_irq); | 126 | setup_irq(pit_ce.irq, &pit_timer_irq); |
127 | clockevents_register_device(&pit_ce); | ||
86 | } | 128 | } |
87 | 129 | ||
88 | struct sys_timer isa_timer = { | 130 | struct sys_timer isa_timer = { |
89 | .init = isa_timer_init, | 131 | .init = isa_timer_init, |
90 | .offset = isa_gettimeoffset, | ||
91 | }; | 132 | }; |