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-rw-r--r--arch/arm/mach-exynos/Kconfig5
-rw-r--r--arch/arm/mach-exynos/Makefile1
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c41
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c9
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c23
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c62
-rw-r--r--arch/arm/mach-exynos/dev-sysmmu.c274
-rw-r--r--arch/arm/mach-exynos/include/mach/sysmmu.h66
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c34
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c30
10 files changed, 137 insertions, 408 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 85afb031b676..70f94c87479d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -105,11 +105,6 @@ config EXYNOS4_SETUP_FIMD0
105 help 105 help
106 Common setup code for FIMD0. 106 Common setup code for FIMD0.
107 107
108config EXYNOS_DEV_SYSMMU
109 bool
110 help
111 Common setup code for SYSTEM MMU in EXYNOS platforms
112
113config EXYNOS4_DEV_USB_OHCI 108config EXYNOS4_DEV_USB_OHCI
114 bool 109 bool
115 help 110 help
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index b189881657ec..435757e57bb4 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
53obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o 53obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
54obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 54obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
55obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
56 55
57obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o 56obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
58obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 57obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index bbcb3dea0d40..8a8468d83c8c 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -24,7 +24,6 @@
24 24
25#include <mach/map.h> 25#include <mach/map.h>
26#include <mach/regs-clock.h> 26#include <mach/regs-clock.h>
27#include <mach/sysmmu.h>
28 27
29#include "common.h" 28#include "common.h"
30#include "clock-exynos4.h" 29#include "clock-exynos4.h"
@@ -709,53 +708,53 @@ static struct clk exynos4_init_clocks_off[] = {
709 .enable = exynos4_clk_ip_peril_ctrl, 708 .enable = exynos4_clk_ip_peril_ctrl,
710 .ctrlbit = (1 << 14), 709 .ctrlbit = (1 << 14),
711 }, { 710 }, {
712 .name = SYSMMU_CLOCK_NAME, 711 .name = "sysmmu",
713 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), 712 .devname = "exynos-sysmmu.0",
714 .enable = exynos4_clk_ip_mfc_ctrl, 713 .enable = exynos4_clk_ip_mfc_ctrl,
715 .ctrlbit = (1 << 1), 714 .ctrlbit = (1 << 1),
716 }, { 715 }, {
717 .name = SYSMMU_CLOCK_NAME, 716 .name = "sysmmu",
718 .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1), 717 .devname = "exynos-sysmmu.1",
719 .enable = exynos4_clk_ip_mfc_ctrl, 718 .enable = exynos4_clk_ip_mfc_ctrl,
720 .ctrlbit = (1 << 2), 719 .ctrlbit = (1 << 2),
721 }, { 720 }, {
722 .name = SYSMMU_CLOCK_NAME, 721 .name = "sysmmu",
723 .devname = SYSMMU_CLOCK_DEVNAME(tv, 2), 722 .devname = "exynos-sysmmu.2",
724 .enable = exynos4_clk_ip_tv_ctrl, 723 .enable = exynos4_clk_ip_tv_ctrl,
725 .ctrlbit = (1 << 4), 724 .ctrlbit = (1 << 4),
726 }, { 725 }, {
727 .name = SYSMMU_CLOCK_NAME, 726 .name = "sysmmu",
728 .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3), 727 .devname = "exynos-sysmmu.3",
729 .enable = exynos4_clk_ip_cam_ctrl, 728 .enable = exynos4_clk_ip_cam_ctrl,
730 .ctrlbit = (1 << 11), 729 .ctrlbit = (1 << 11),
731 }, { 730 }, {
732 .name = SYSMMU_CLOCK_NAME, 731 .name = "sysmmu",
733 .devname = SYSMMU_CLOCK_DEVNAME(rot, 4), 732 .devname = "exynos-sysmmu.4",
734 .enable = exynos4_clk_ip_image_ctrl, 733 .enable = exynos4_clk_ip_image_ctrl,
735 .ctrlbit = (1 << 4), 734 .ctrlbit = (1 << 4),
736 }, { 735 }, {
737 .name = SYSMMU_CLOCK_NAME, 736 .name = "sysmmu",
738 .devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5), 737 .devname = "exynos-sysmmu.5",
739 .enable = exynos4_clk_ip_cam_ctrl, 738 .enable = exynos4_clk_ip_cam_ctrl,
740 .ctrlbit = (1 << 7), 739 .ctrlbit = (1 << 7),
741 }, { 740 }, {
742 .name = SYSMMU_CLOCK_NAME, 741 .name = "sysmmu",
743 .devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6), 742 .devname = "exynos-sysmmu.6",
744 .enable = exynos4_clk_ip_cam_ctrl, 743 .enable = exynos4_clk_ip_cam_ctrl,
745 .ctrlbit = (1 << 8), 744 .ctrlbit = (1 << 8),
746 }, { 745 }, {
747 .name = SYSMMU_CLOCK_NAME, 746 .name = "sysmmu",
748 .devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7), 747 .devname = "exynos-sysmmu.7",
749 .enable = exynos4_clk_ip_cam_ctrl, 748 .enable = exynos4_clk_ip_cam_ctrl,
750 .ctrlbit = (1 << 9), 749 .ctrlbit = (1 << 9),
751 }, { 750 }, {
752 .name = SYSMMU_CLOCK_NAME, 751 .name = "sysmmu",
753 .devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8), 752 .devname = "exynos-sysmmu.8",
754 .enable = exynos4_clk_ip_cam_ctrl, 753 .enable = exynos4_clk_ip_cam_ctrl,
755 .ctrlbit = (1 << 10), 754 .ctrlbit = (1 << 10),
756 }, { 755 }, {
757 .name = SYSMMU_CLOCK_NAME, 756 .name = "sysmmu",
758 .devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10), 757 .devname = "exynos-sysmmu.10",
759 .enable = exynos4_clk_ip_lcd0_ctrl, 758 .enable = exynos4_clk_ip_lcd0_ctrl,
760 .ctrlbit = (1 << 4), 759 .ctrlbit = (1 << 4),
761 } 760 }
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index fed4c26e9dad..19af9f783c56 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -26,7 +26,6 @@
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/map.h> 27#include <mach/map.h>
28#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
29#include <mach/sysmmu.h>
30 29
31#include "common.h" 30#include "common.h"
32#include "clock-exynos4.h" 31#include "clock-exynos4.h"
@@ -129,13 +128,13 @@ static struct clk init_clocks_off[] = {
129 .enable = exynos4_clk_ip_lcd1_ctrl, 128 .enable = exynos4_clk_ip_lcd1_ctrl,
130 .ctrlbit = (1 << 0), 129 .ctrlbit = (1 << 0),
131 }, { 130 }, {
132 .name = SYSMMU_CLOCK_NAME, 131 .name = "sysmmu",
133 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14), 132 .devname = "exynos-sysmmu.9",
134 .enable = exynos4_clk_ip_image_ctrl, 133 .enable = exynos4_clk_ip_image_ctrl,
135 .ctrlbit = (1 << 3), 134 .ctrlbit = (1 << 3),
136 }, { 135 }, {
137 .name = SYSMMU_CLOCK_NAME, 136 .name = "sysmmu",
138 .devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11), 137 .devname = "exynos-sysmmu.11",
139 .enable = exynos4_clk_ip_lcd1_ctrl, 138 .enable = exynos4_clk_ip_lcd1_ctrl,
140 .ctrlbit = (1 << 4), 139 .ctrlbit = (1 << 4),
141 }, { 140 }, {
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 8fba0b5fb8ab..529476f8ec71 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -26,7 +26,6 @@
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/map.h> 27#include <mach/map.h>
28#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
29#include <mach/sysmmu.h>
30 29
31#include "common.h" 30#include "common.h"
32#include "clock-exynos4.h" 31#include "clock-exynos4.h"
@@ -111,21 +110,31 @@ static struct clksrc_clk clksrcs[] = {
111 110
112static struct clk init_clocks_off[] = { 111static struct clk init_clocks_off[] = {
113 { 112 {
114 .name = SYSMMU_CLOCK_NAME, 113 .name = "sysmmu",
115 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14), 114 .devname = "exynos-sysmmu.9",
116 .enable = exynos4_clk_ip_dmc_ctrl, 115 .enable = exynos4_clk_ip_dmc_ctrl,
117 .ctrlbit = (1 << 24), 116 .ctrlbit = (1 << 24),
118 }, { 117 }, {
119 .name = SYSMMU_CLOCK_NAME, 118 .name = "sysmmu",
120 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), 119 .devname = "exynos-sysmmu.12",
121 .enable = exynos4212_clk_ip_isp0_ctrl, 120 .enable = exynos4212_clk_ip_isp0_ctrl,
122 .ctrlbit = (7 << 8), 121 .ctrlbit = (7 << 8),
123 }, { 122 }, {
124 .name = SYSMMU_CLOCK_NAME2, 123 .name = "sysmmu",
125 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), 124 .devname = "exynos-sysmmu.13",
126 .enable = exynos4212_clk_ip_isp1_ctrl, 125 .enable = exynos4212_clk_ip_isp1_ctrl,
127 .ctrlbit = (1 << 4), 126 .ctrlbit = (1 << 4),
128 }, { 127 }, {
128 .name = "sysmmu",
129 .devname = "exynos-sysmmu.14",
130 .enable = exynos4212_clk_ip_isp0_ctrl,
131 .ctrlbit = (1 << 11),
132 }, {
133 .name = "sysmmu",
134 .devname = "exynos-sysmmu.15",
135 .enable = exynos4212_clk_ip_isp0_ctrl,
136 .ctrlbit = (1 << 12),
137 }, {
129 .name = "flite", 138 .name = "flite",
130 .devname = "exynos-fimc-lite.0", 139 .devname = "exynos-fimc-lite.0",
131 .enable = exynos4212_clk_ip_isp0_ctrl, 140 .enable = exynos4212_clk_ip_isp0_ctrl,
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index e9d7b80bae49..b0ea31fc9fb8 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -24,7 +24,6 @@
24 24
25#include <mach/map.h> 25#include <mach/map.h>
26#include <mach/regs-clock.h> 26#include <mach/regs-clock.h>
27#include <mach/sysmmu.h>
28 27
29#include "common.h" 28#include "common.h"
30 29
@@ -859,73 +858,78 @@ static struct clk exynos5_init_clocks_off[] = {
859 .enable = exynos5_clk_ip_gscl_ctrl, 858 .enable = exynos5_clk_ip_gscl_ctrl,
860 .ctrlbit = (1 << 3), 859 .ctrlbit = (1 << 3),
861 }, { 860 }, {
862 .name = SYSMMU_CLOCK_NAME, 861 .name = "sysmmu",
863 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), 862 .devname = "exynos-sysmmu.1",
864 .enable = &exynos5_clk_ip_mfc_ctrl, 863 .enable = &exynos5_clk_ip_mfc_ctrl,
865 .ctrlbit = (1 << 1), 864 .ctrlbit = (1 << 1),
866 }, { 865 }, {
867 .name = SYSMMU_CLOCK_NAME, 866 .name = "sysmmu",
868 .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1), 867 .devname = "exynos-sysmmu.0",
869 .enable = &exynos5_clk_ip_mfc_ctrl, 868 .enable = &exynos5_clk_ip_mfc_ctrl,
870 .ctrlbit = (1 << 2), 869 .ctrlbit = (1 << 2),
871 }, { 870 }, {
872 .name = SYSMMU_CLOCK_NAME, 871 .name = "sysmmu",
873 .devname = SYSMMU_CLOCK_DEVNAME(tv, 2), 872 .devname = "exynos-sysmmu.2",
874 .enable = &exynos5_clk_ip_disp1_ctrl, 873 .enable = &exynos5_clk_ip_disp1_ctrl,
875 .ctrlbit = (1 << 9) 874 .ctrlbit = (1 << 9)
876 }, { 875 }, {
877 .name = SYSMMU_CLOCK_NAME, 876 .name = "sysmmu",
878 .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3), 877 .devname = "exynos-sysmmu.3",
879 .enable = &exynos5_clk_ip_gen_ctrl, 878 .enable = &exynos5_clk_ip_gen_ctrl,
880 .ctrlbit = (1 << 7), 879 .ctrlbit = (1 << 7),
881 }, { 880 }, {
882 .name = SYSMMU_CLOCK_NAME, 881 .name = "sysmmu",
883 .devname = SYSMMU_CLOCK_DEVNAME(rot, 4), 882 .devname = "exynos-sysmmu.4",
884 .enable = &exynos5_clk_ip_gen_ctrl, 883 .enable = &exynos5_clk_ip_gen_ctrl,
885 .ctrlbit = (1 << 6) 884 .ctrlbit = (1 << 6)
886 }, { 885 }, {
887 .name = SYSMMU_CLOCK_NAME, 886 .name = "sysmmu",
888 .devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5), 887 .devname = "exynos-sysmmu.5",
889 .enable = &exynos5_clk_ip_gscl_ctrl, 888 .enable = &exynos5_clk_ip_gscl_ctrl,
890 .ctrlbit = (1 << 7), 889 .ctrlbit = (1 << 7),
891 }, { 890 }, {
892 .name = SYSMMU_CLOCK_NAME, 891 .name = "sysmmu",
893 .devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6), 892 .devname = "exynos-sysmmu.6",
894 .enable = &exynos5_clk_ip_gscl_ctrl, 893 .enable = &exynos5_clk_ip_gscl_ctrl,
895 .ctrlbit = (1 << 8), 894 .ctrlbit = (1 << 8),
896 }, { 895 }, {
897 .name = SYSMMU_CLOCK_NAME, 896 .name = "sysmmu",
898 .devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7), 897 .devname = "exynos-sysmmu.7",
899 .enable = &exynos5_clk_ip_gscl_ctrl, 898 .enable = &exynos5_clk_ip_gscl_ctrl,
900 .ctrlbit = (1 << 9), 899 .ctrlbit = (1 << 9),
901 }, { 900 }, {
902 .name = SYSMMU_CLOCK_NAME, 901 .name = "sysmmu",
903 .devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8), 902 .devname = "exynos-sysmmu.8",
904 .enable = &exynos5_clk_ip_gscl_ctrl, 903 .enable = &exynos5_clk_ip_gscl_ctrl,
905 .ctrlbit = (1 << 10), 904 .ctrlbit = (1 << 10),
906 }, { 905 }, {
907 .name = SYSMMU_CLOCK_NAME, 906 .name = "sysmmu",
908 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), 907 .devname = "exynos-sysmmu.9",
909 .enable = &exynos5_clk_ip_isp0_ctrl, 908 .enable = &exynos5_clk_ip_isp0_ctrl,
910 .ctrlbit = (0x3F << 8), 909 .ctrlbit = (0x3F << 8),
911 }, { 910 }, {
912 .name = SYSMMU_CLOCK_NAME2, 911 .name = "sysmmu",
913 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), 912 .devname = "exynos-sysmmu.10",
914 .enable = &exynos5_clk_ip_isp1_ctrl, 913 .enable = &exynos5_clk_ip_isp1_ctrl,
915 .ctrlbit = (0xF << 4), 914 .ctrlbit = (0xF << 4),
916 }, { 915 }, {
917 .name = SYSMMU_CLOCK_NAME, 916 .name = "sysmmu",
918 .devname = SYSMMU_CLOCK_DEVNAME(camif0, 12), 917 .devname = "exynos-sysmmu.11",
918 .enable = &exynos5_clk_ip_disp1_ctrl,
919 .ctrlbit = (1 << 8)
920 }, {
921 .name = "sysmmu",
922 .devname = "exynos-sysmmu.12",
919 .enable = &exynos5_clk_ip_gscl_ctrl, 923 .enable = &exynos5_clk_ip_gscl_ctrl,
920 .ctrlbit = (1 << 11), 924 .ctrlbit = (1 << 11),
921 }, { 925 }, {
922 .name = SYSMMU_CLOCK_NAME, 926 .name = "sysmmu",
923 .devname = SYSMMU_CLOCK_DEVNAME(camif1, 13), 927 .devname = "exynos-sysmmu.13",
924 .enable = &exynos5_clk_ip_gscl_ctrl, 928 .enable = &exynos5_clk_ip_gscl_ctrl,
925 .ctrlbit = (1 << 12), 929 .ctrlbit = (1 << 12),
926 }, { 930 }, {
927 .name = SYSMMU_CLOCK_NAME, 931 .name = "sysmmu",
928 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14), 932 .devname = "exynos-sysmmu.14",
929 .enable = &exynos5_clk_ip_acp_ctrl, 933 .enable = &exynos5_clk_ip_acp_ctrl,
930 .ctrlbit = (1 << 7) 934 .ctrlbit = (1 << 7)
931 } 935 }
diff --git a/arch/arm/mach-exynos/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
deleted file mode 100644
index c5b1ea301df0..000000000000
--- a/arch/arm/mach-exynos/dev-sysmmu.c
+++ /dev/null
@@ -1,274 +0,0 @@
1/* linux/arch/arm/mach-exynos/dev-sysmmu.c
2 *
3 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS - System MMU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15
16#include <plat/cpu.h>
17
18#include <mach/map.h>
19#include <mach/irqs.h>
20#include <mach/sysmmu.h>
21
22static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
23
24#define SYSMMU_PLATFORM_DEVICE(ipname, devid) \
25static struct sysmmu_platform_data platdata_##ipname = { \
26 .dbgname = #ipname, \
27}; \
28struct platform_device SYSMMU_PLATDEV(ipname) = \
29{ \
30 .name = SYSMMU_DEVNAME_BASE, \
31 .id = devid, \
32 .dev = { \
33 .dma_mask = &exynos_sysmmu_dma_mask, \
34 .coherent_dma_mask = DMA_BIT_MASK(32), \
35 .platform_data = &platdata_##ipname, \
36 }, \
37}
38
39SYSMMU_PLATFORM_DEVICE(mfc_l, 0);
40SYSMMU_PLATFORM_DEVICE(mfc_r, 1);
41SYSMMU_PLATFORM_DEVICE(tv, 2);
42SYSMMU_PLATFORM_DEVICE(jpeg, 3);
43SYSMMU_PLATFORM_DEVICE(rot, 4);
44SYSMMU_PLATFORM_DEVICE(fimc0, 5); /* fimc* and gsc* exist exclusively */
45SYSMMU_PLATFORM_DEVICE(fimc1, 6);
46SYSMMU_PLATFORM_DEVICE(fimc2, 7);
47SYSMMU_PLATFORM_DEVICE(fimc3, 8);
48SYSMMU_PLATFORM_DEVICE(gsc0, 5);
49SYSMMU_PLATFORM_DEVICE(gsc1, 6);
50SYSMMU_PLATFORM_DEVICE(gsc2, 7);
51SYSMMU_PLATFORM_DEVICE(gsc3, 8);
52SYSMMU_PLATFORM_DEVICE(isp, 9);
53SYSMMU_PLATFORM_DEVICE(fimd0, 10);
54SYSMMU_PLATFORM_DEVICE(fimd1, 11);
55SYSMMU_PLATFORM_DEVICE(camif0, 12);
56SYSMMU_PLATFORM_DEVICE(camif1, 13);
57SYSMMU_PLATFORM_DEVICE(2d, 14);
58
59#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
60
61#define SYSMMU_RESOURCE(core, ipname) \
62 static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
63
64#define DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
65 DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem), \
66 DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
67
68#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq) \
69 SYSMMU_RESOURCE(core, ipname) { \
70 DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
71 }
72
73struct sysmmu_resource_map {
74 struct platform_device *pdev;
75 struct resource *res;
76 u32 rnum;
77 struct device *pdd;
78 char *clocknames;
79};
80
81#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) { \
82 .pdev = &SYSMMU_PLATDEV(ipname), \
83 .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
84 .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
85 .clocknames = SYSMMU_CLOCK_NAME, \
86}
87
88#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) { \
89 .pdev = &SYSMMU_PLATDEV(ipname), \
90 .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
91 .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
92 .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
93}
94
95#ifdef CONFIG_EXYNOS_DEV_PD
96#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) { \
97 .pdev = &SYSMMU_PLATDEV(ipname), \
98 .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
99 .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
100 .clocknames = SYSMMU_CLOCK_NAME, \
101 .pdd = &exynos##core##_device_pd[pd].dev, \
102}
103
104#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
105 .pdev = &SYSMMU_PLATDEV(ipname), \
106 .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
107 .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
108 .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
109 .pdd = &exynos##core##_device_pd[pd].dev, \
110}
111#else
112#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) \
113 SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
114#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) \
115 SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
116
117#endif /* CONFIG_EXYNOS_DEV_PD */
118
119#ifdef CONFIG_ARCH_EXYNOS4
120SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0, FIMC0, FIMC0);
121SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1, FIMC1, FIMC1);
122SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2, FIMC2, FIMC2);
123SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3, FIMC3, FIMC3);
124SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg, JPEG, JPEG);
125SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d, G2D, 2D);
126SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv, TV, TV_M0);
127SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp, 2D_ACP, 2D);
128SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot, ROTATOR, ROTATOR);
129SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0, FIMD0, LCD0_M0);
130SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1, FIMD1, LCD1_M1);
131SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0, FIMC_LITE0, FIMC_LITE0);
132SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1, FIMC_LITE1, FIMC_LITE1);
133SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r, MFC_R, MFC_M0);
134SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l, MFC_L, MFC_M1);
135SYSMMU_RESOURCE(EXYNOS4, isp) {
136 DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
137 DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
138 DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
139 DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
140};
141
142static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
143 SYSMMU_RESOURCE_MAPPING_PD(4, fimc0, fimc0, PD_CAM),
144 SYSMMU_RESOURCE_MAPPING_PD(4, fimc1, fimc1, PD_CAM),
145 SYSMMU_RESOURCE_MAPPING_PD(4, fimc2, fimc2, PD_CAM),
146 SYSMMU_RESOURCE_MAPPING_PD(4, fimc3, fimc3, PD_CAM),
147 SYSMMU_RESOURCE_MAPPING_PD(4, tv, tv, PD_TV),
148 SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r, mfc_r, PD_MFC),
149 SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l, mfc_l, PD_MFC),
150 SYSMMU_RESOURCE_MAPPING_PD(4, rot, rot, PD_LCD0),
151 SYSMMU_RESOURCE_MAPPING_PD(4, jpeg, jpeg, PD_CAM),
152 SYSMMU_RESOURCE_MAPPING_PD(4, fimd0, fimd0, PD_LCD0),
153};
154
155static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
156 SYSMMU_RESOURCE_MAPPING_PD(4, 2d, 2d, PD_LCD0),
157 SYSMMU_RESOURCE_MAPPING_PD(4, fimd1, fimd1, PD_LCD1),
158};
159
160static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
161 SYSMMU_RESOURCE_MAPPING(4, 2d, 2d_acp),
162 SYSMMU_RESOURCE_MAPPING_PD(4, camif0, flite0, PD_ISP),
163 SYSMMU_RESOURCE_MAPPING_PD(4, camif1, flite1, PD_ISP),
164 SYSMMU_RESOURCE_MAPPING_PD(4, isp, isp, PD_ISP),
165};
166#endif /* CONFIG_ARCH_EXYNOS4 */
167
168#ifdef CONFIG_ARCH_EXYNOS5
169SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg, JPEG, JPEG);
170SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1, FIMD1, FIMD1);
171SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d, 2D, 2D);
172SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot, ROTATOR, ROTATOR);
173SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv, TV, TV);
174SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0, LITE0, LITE0);
175SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1, LITE1, LITE1);
176SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0, GSC0, GSC0);
177SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1, GSC1, GSC1);
178SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2, GSC2, GSC2);
179SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3, GSC3, GSC3);
180SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r, MFC_R, MFC_R);
181SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l, MFC_L, MFC_L);
182SYSMMU_RESOURCE(EXYNOS5, isp) {
183 DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
184 DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
185 DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
186 DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
187 DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
188 DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
189 DEFINE_SYSMMU_RESOURCE(EXYNOS5, ODC, ODC),
190 DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
191 DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
192 DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
193};
194
195static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
196 SYSMMU_RESOURCE_MAPPING(5, jpeg, jpeg),
197 SYSMMU_RESOURCE_MAPPING(5, fimd1, fimd1),
198 SYSMMU_RESOURCE_MAPPING(5, 2d, 2d),
199 SYSMMU_RESOURCE_MAPPING(5, rot, rot),
200 SYSMMU_RESOURCE_MAPPING_PD(5, tv, tv, PD_DISP1),
201 SYSMMU_RESOURCE_MAPPING_PD(5, camif0, flite0, PD_GSCL),
202 SYSMMU_RESOURCE_MAPPING_PD(5, camif1, flite1, PD_GSCL),
203 SYSMMU_RESOURCE_MAPPING_PD(5, gsc0, gsc0, PD_GSCL),
204 SYSMMU_RESOURCE_MAPPING_PD(5, gsc1, gsc1, PD_GSCL),
205 SYSMMU_RESOURCE_MAPPING_PD(5, gsc2, gsc2, PD_GSCL),
206 SYSMMU_RESOURCE_MAPPING_PD(5, gsc3, gsc3, PD_GSCL),
207 SYSMMU_RESOURCE_MAPPING_PD(5, mfc_r, mfc_r, PD_MFC),
208 SYSMMU_RESOURCE_MAPPING_PD(5, mfc_l, mfc_l, PD_MFC),
209 SYSMMU_RESOURCE_MAPPING_MCPD(5, isp, isp, PD_ISP, mc_platdata),
210};
211#endif /* CONFIG_ARCH_EXYNOS5 */
212
213static int __init init_sysmmu_platform_device(void)
214{
215 int i, j;
216 struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
217 int nmap[2] = {0, 0};
218
219#ifdef CONFIG_ARCH_EXYNOS5
220 if (soc_is_exynos5250()) {
221 resmap[0] = sysmmu_resmap5;
222 nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
223 nmap[1] = 0;
224 }
225#endif
226
227#ifdef CONFIG_ARCH_EXYNOS4
228 if (resmap[0] == NULL) {
229 resmap[0] = sysmmu_resmap4;
230 nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
231 }
232
233 if (soc_is_exynos4210()) {
234 resmap[1] = sysmmu_resmap4210;
235 nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
236 }
237
238 if (soc_is_exynos4412() || soc_is_exynos4212()) {
239 resmap[1] = sysmmu_resmap4212;
240 nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
241 }
242#endif
243
244 for (j = 0; j < 2; j++) {
245 for (i = 0; i < nmap[j]; i++) {
246 struct sysmmu_resource_map *map;
247 struct sysmmu_platform_data *platdata;
248
249 map = &resmap[j][i];
250
251 map->pdev->dev.parent = map->pdd;
252
253 platdata = map->pdev->dev.platform_data;
254 platdata->clockname = map->clocknames;
255
256 if (platform_device_add_resources(map->pdev, map->res,
257 map->rnum)) {
258 pr_err("%s: Failed to add device resources for "
259 "%s.%d\n", __func__,
260 map->pdev->name, map->pdev->id);
261 continue;
262 }
263
264 if (platform_device_register(map->pdev)) {
265 pr_err("%s: Failed to register %s.%d\n",
266 __func__, map->pdev->name,
267 map->pdev->id);
268 }
269 }
270 }
271
272 return 0;
273}
274arch_initcall(init_sysmmu_platform_device);
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
deleted file mode 100644
index 88a4543b0001..000000000000
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - System MMU support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
13#define _ARM_MACH_EXYNOS_SYSMMU_H_
14
15struct sysmmu_platform_data {
16 char *dbgname;
17 /* comma(,) separated list of clock names for clock gating */
18 char *clockname;
19};
20
21#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
22
23#define SYSMMU_CLOCK_NAME "sysmmu"
24#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
25
26#ifdef CONFIG_EXYNOS_DEV_SYSMMU
27#include <linux/device.h>
28struct platform_device;
29
30#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
31
32extern struct platform_device SYSMMU_PLATDEV(mfc_l);
33extern struct platform_device SYSMMU_PLATDEV(mfc_r);
34extern struct platform_device SYSMMU_PLATDEV(tv);
35extern struct platform_device SYSMMU_PLATDEV(jpeg);
36extern struct platform_device SYSMMU_PLATDEV(rot);
37extern struct platform_device SYSMMU_PLATDEV(fimc0);
38extern struct platform_device SYSMMU_PLATDEV(fimc1);
39extern struct platform_device SYSMMU_PLATDEV(fimc2);
40extern struct platform_device SYSMMU_PLATDEV(fimc3);
41extern struct platform_device SYSMMU_PLATDEV(gsc0);
42extern struct platform_device SYSMMU_PLATDEV(gsc1);
43extern struct platform_device SYSMMU_PLATDEV(gsc2);
44extern struct platform_device SYSMMU_PLATDEV(gsc3);
45extern struct platform_device SYSMMU_PLATDEV(isp);
46extern struct platform_device SYSMMU_PLATDEV(fimd0);
47extern struct platform_device SYSMMU_PLATDEV(fimd1);
48extern struct platform_device SYSMMU_PLATDEV(camif0);
49extern struct platform_device SYSMMU_PLATDEV(camif1);
50extern struct platform_device SYSMMU_PLATDEV(2d);
51
52#ifdef CONFIG_IOMMU_API
53static inline void platform_set_sysmmu(
54 struct device *sysmmu, struct device *dev)
55{
56 dev->archdata.iommu = sysmmu;
57}
58#endif
59
60#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
61#define platform_set_sysmmu(sysmmu, dev) do { } while (0)
62#endif
63
64#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
65
66#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 92757ff817ae..ac09af860b38 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -80,6 +80,40 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
80 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL), 80 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
81 OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU, 81 OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
82 "exynos-tmu", NULL), 82 "exynos-tmu", NULL),
83 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
84 "exynos-sysmmu.0", NULL), /* MFC_L */
85 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
86 "exynos-sysmmu.1", NULL), /* MFC_R */
87 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
88 "exynos-sysmmu.2", NULL), /* TV */
89 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
90 "exynos-sysmmu.3", NULL), /* JPEG */
91 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
92 "exynos-sysmmu.4", NULL), /* ROTATOR */
93 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
94 "exynos-sysmmu.5", NULL), /* FIMC0 */
95 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
96 "exynos-sysmmu.6", NULL), /* FIMC1 */
97 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
98 "exynos-sysmmu.7", NULL), /* FIMC2 */
99 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
100 "exynos-sysmmu.8", NULL), /* FIMC3 */
101 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
102 "exynos-sysmmu.9", NULL), /* G2D(4210) */
103 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
104 "exynos-sysmmu.9", NULL), /* G2D(4x12) */
105 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
106 "exynos-sysmmu.10", NULL), /* FIMD0 */
107 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
108 "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
109 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
110 "exynos-sysmmu.12", NULL), /* IS0(4x12) */
111 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
112 "exynos-sysmmu.13", NULL), /* IS1(4x12) */
113 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
114 "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
115 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
116 "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
83 {}, 117 {},
84}; 118};
85 119
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index e99d3d8f2bcf..26710758c385 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -104,6 +104,36 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
104 OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL), 104 OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
105 OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000, 105 OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
106 "exynos-tmu", NULL), 106 "exynos-tmu", NULL),
107 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
108 "exynos-sysmmu.0", "mfc"), /* MFC_L */
109 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
110 "exynos-sysmmu.1", "mfc"), /* MFC_R */
111 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
112 "exynos-sysmmu.2", NULL), /* TV */
113 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
114 "exynos-sysmmu.3", "jpeg"), /* JPEG */
115 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
116 "exynos-sysmmu.4", NULL), /* ROTATOR */
117 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
118 "exynos-sysmmu.5", "gscl"), /* GSCL0 */
119 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
120 "exynos-sysmmu.6", "gscl"), /* GSCL1 */
121 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
122 "exynos-sysmmu.7", "gscl"), /* GSCL2 */
123 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
124 "exynos-sysmmu.8", "gscl"), /* GSCL3 */
125 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
126 "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
127 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
128 "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
129 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
130 "exynos-sysmmu.11", NULL), /* FIMD1 */
131 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
132 "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
133 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
134 "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
135 OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
136 "exynos-sysmmu.14", NULL), /* G2D */
107 {}, 137 {},
108}; 138};
109 139
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 19:18:13 -0500