18 files changed, 423 insertions, 133 deletions

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e3cfd5fd7dd5..43ebe9094411 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select SAMSUNG_DMADEV
         help
           Enable EXYNOS5250 SoC support
 
@@ -70,7 +71,7 @@ config EXYNOS4_MCT
         help
           Use MCT (Multi Core Timer) as kernel timers
 
-config EXYNOS4_DEV_DMA
+config EXYNOS_DEV_DMA
         bool
         help
           Compile in amba device definitions for DMA controller
@@ -80,6 +81,11 @@ config EXYNOS4_DEV_AHCI
         help
           Compile in platform device definitions for AHCI
 
+config EXYNOS_DEV_DRM
+        bool
+        help
+          Compile in platform device definitions for core DRM device
+
 config EXYNOS4_SETUP_FIMD0
         bool
         help
@@ -161,7 +167,7 @@ config EXYNOS4_SETUP_USB_PHY
         help
           Common setup code for USB PHY controller
 
-config EXYNOS4_SETUP_SPI
+config EXYNOS_SETUP_SPI
         bool
         help
           Common setup code for SPI GPIO configurations.
@@ -224,7 +230,7 @@ config MACH_ARMLEX4210
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
         select EXYNOS4_DEV_AHCI
-        select EXYNOS4_DEV_DMA
+        select EXYNOS_DEV_DMA
         select EXYNOS4_SETUP_SDHCI
         help
           Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -362,7 +368,7 @@ config MACH_SMDK4212
         select SAMSUNG_DEV_KEYPAD
         select SAMSUNG_DEV_PWM
         select EXYNOS_DEV_SYSMMU
-        select EXYNOS4_DEV_DMA
+        select EXYNOS_DEV_DMA
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C7
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 272625231c73..440a637c76f1 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -50,10 +50,11 @@ obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 obj-y                                   += dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)              += dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
-obj-$(CONFIG_EXYNOS_DEV_SYSMMU)         += dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)         += dev-dwmci.o
-obj-$(CONFIG_EXYNOS4_DEV_DMA)           += dma.o
+obj-$(CONFIG_EXYNOS_DEV_DMA)            += dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
+obj-$(CONFIG_EXYNOS_DEV_DRM)            += dev-drm.o
+obj-$(CONFIG_EXYNOS_DEV_SYSMMU)         += dev-sysmmu.o
 
 obj-$(CONFIG_ARCH_EXYNOS)               += setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
@@ -68,4 +69,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7)	+= setup-i2c7.o
 obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)      += setup-keypad.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
 obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)     += setup-usb-phy.o
-obj-$(CONFIG_EXYNOS4_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_EXYNOS_SETUP_SPI)          += setup-spi.o
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
index b9862e22bf10..31bd181b0514 100644
--- a/arch/arm/mach-exynos/Makefile.boot
+++ b/arch/arm/mach-exynos/Makefile.boot
@@ -1,2 +1,5 @@
    zreladdr-y   += 0x40008000
 params_phys-y   := 0x40000100
+
+dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
+dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 98823120570e..da397d21bbcf 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -92,6 +92,16 @@ static struct clk init_clocks_off[] = {
                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
                 .enable         = exynos4212_clk_ip_isp1_ctrl,
                 .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "flite",
+                .devname        = "exynos-fimc-lite.0",
+                .enable         = exynos4212_clk_ip_isp0_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "flite",
+                .devname        = "exynos-fimc-lite.1",
+                .enable         = exynos4212_clk_ip_isp0_ctrl,
+                .ctrlbit        = (1 << 3),
         }
 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 9f87a07b0bf8..5aa460b01fdf 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+        .clk    = {
+                .name           = "mout_bpll_fout",
+        },
+        .sources = &clk_src_bpll_fout,
+        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_list[] = {
+        [0] = &clk_fin_bpll,
+        [1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll = {
+        .sources        = exynos5_clk_src_bpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
+};
+
 static struct clksrc_clk exynos5_clk_mout_bpll = {
         .clk    = {
                 .name           = "mout_bpll",
         },
-        .sources = &clk_src_bpll,
+        .sources = &exynos5_clk_src_bpll,
         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 };
 
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+        .clk    = {
+                .name           = "mout_mpll_fout",
+        },
+        .sources = &clk_src_mpll_fout,
+        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll = {
+        .sources        = exynos5_clk_src_mpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
 struct clksrc_clk exynos5_clk_mout_mpll = {
         .clk = {
                 .name           = "mout_mpll",
         },
-        .sources = &clk_src_mpll,
+        .sources = &exynos5_clk_src_mpll,
         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 };
 
@@ -474,6 +510,11 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_peris_ctrl,
                 .ctrlbit        = (1 << 20),
         }, {
+                .name           = "watchdog",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peris_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
                 .name           = "hsmmc",
                 .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos5_clk_aclk_200.clk,
@@ -1031,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
         &exynos5_clk_mout_apll,
         &exynos5_clk_sclk_apll,
         &exynos5_clk_mout_bpll,
+        &exynos5_clk_mout_bpll_fout,
         &exynos5_clk_mout_bpll_user,
         &exynos5_clk_mout_cpll,
         &exynos5_clk_mout_epll,
         &exynos5_clk_mout_mpll,
+        &exynos5_clk_mout_mpll_fout,
         &exynos5_clk_mout_mpll_user,
         &exynos5_clk_vpllsrc,
         &exynos5_clk_sclk_vpll,
@@ -1098,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = {
         &exynos5_clk_sclk_hdmi27m,
         &exynos5_clk_sclk_hdmiphy,
         &clk_fout_bpll,
+        &clk_fout_bpll_div2,
         &clk_fout_cpll,
+        &clk_fout_mpll_div2,
         &exynos5_clk_armclk,
 };
 
@@ -1263,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
 
         clk_fout_apll.ops = &exynos5_fout_apll_ops;
         clk_fout_bpll.rate = bpll;
+        clk_fout_bpll_div2.rate = bpll >> 1;
         clk_fout_cpll.rate = cpll;
         clk_fout_mpll.rate = mpll;
+        clk_fout_mpll_div2.rate = mpll >> 1;
         clk_fout_epll.rate = epll;
         clk_fout_vpll.rate = vpll;
 
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 5ccd6e80a607..49134711f4c6 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -19,6 +19,9 @@
 #include <linux/serial_core.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/export.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
@@ -265,12 +268,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
         }, {
                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
-                .length         = SZ_64K,
+                .length         = SZ_8K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
-                .length         = SZ_64K,
+                .length         = SZ_4K,
                 .type           = MT_DEVICE,
         },
 };
@@ -399,6 +402,7 @@ struct combiner_chip_data {
         void __iomem *base;
 };
 
+static struct irq_domain *combiner_irq_domain;
 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 
 static inline void __iomem *combiner_base(struct irq_data *data)
@@ -411,14 +415,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
 
 static void combiner_mask_irq(struct irq_data *data)
 {
-        u32 mask = 1 << (data->irq % 32);
+        u32 mask = 1 << (data->hwirq % 32);
 
         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 }
 
 static void combiner_unmask_irq(struct irq_data *data)
 {
-        u32 mask = 1 << (data->irq % 32);
+        u32 mask = 1 << (data->hwirq % 32);
 
         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 }
@@ -474,49 +478,131 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 }
 
-static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
-                          unsigned int irq_start)
+static void __init combiner_init_one(unsigned int combiner_nr,
+                                     void __iomem *base)
 {
-        unsigned int i;
-        unsigned int max_nr;
-
-        if (soc_is_exynos5250())
-                max_nr = EXYNOS5_MAX_COMBINER_NR;
-        else
-                max_nr = EXYNOS4_MAX_COMBINER_NR;
-
-        if (combiner_nr >= max_nr)
-                BUG();
-
         combiner_data[combiner_nr].base = base;
-        combiner_data[combiner_nr].irq_offset = irq_start;
+        combiner_data[combiner_nr].irq_offset = irq_find_mapping(
+                combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 
         /* Disable all interrupts */
-
         __raw_writel(combiner_data[combiner_nr].irq_mask,
                      base + COMBINER_ENABLE_CLEAR);
+}
+
+#ifdef CONFIG_OF
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+                                     struct device_node *controller,
+                                     const u32 *intspec, unsigned int intsize,
+                                     unsigned long *out_hwirq,
+                                     unsigned int *out_type)
+{
+        if (d->of_node != controller)
+                return -EINVAL;
+
+        if (intsize < 2)
+                return -EINVAL;
+
+        *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
+        *out_type = 0;
+
+        return 0;
+}
+#else
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+                                     struct device_node *controller,
+                                     const u32 *intspec, unsigned int intsize,
+                                     unsigned long *out_hwirq,
+                                     unsigned int *out_type)
+{
+        return -EINVAL;
+}
+#endif
+
+static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                                   irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
+        irq_set_chip_data(irq, &combiner_data[hw >> 3]);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 
-        /* Setup the Linux IRQ subsystem */
+        return 0;
+}
+
+static struct irq_domain_ops combiner_irq_domain_ops = {
+        .xlate  = combiner_irq_domain_xlate,
+        .map    = combiner_irq_domain_map,
+};
 
-        for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
-                                + MAX_IRQ_IN_COMBINER; i++) {
-                irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
-                irq_set_chip_data(i, &combiner_data[combiner_nr]);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
+{
+        int i, irq, irq_base;
+        unsigned int max_nr, nr_irq;
+
+        if (np) {
+                if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
+                        pr_warning("%s: number of combiners not specified, "
+                                "setting default as %d.\n",
+                                __func__, EXYNOS4_MAX_COMBINER_NR);
+                        max_nr = EXYNOS4_MAX_COMBINER_NR;
+                }
+        } else {
+                max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+                                                EXYNOS4_MAX_COMBINER_NR;
+        }
+        nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
+
+        irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
+        if (IS_ERR_VALUE(irq_base)) {
+                irq_base = COMBINER_IRQ(0, 0);
+                pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
+        }
+
+        combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
+                                &combiner_irq_domain_ops, &combiner_data);
+        if (WARN_ON(!combiner_irq_domain)) {
+                pr_warning("%s: irq domain init failed\n", __func__);
+                return;
+        }
+
+        for (i = 0; i < max_nr; i++) {
+                combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
+                irq = IRQ_SPI(i);
+#ifdef CONFIG_OF
+                if (np)
+                        irq = irq_of_parse_and_map(np, i);
+#endif
+                combiner_cascade_irq(i, irq);
         }
 }
 
 #ifdef CONFIG_OF
+int __init combiner_of_init(struct device_node *np, struct device_node *parent)
+{
+        void __iomem *combiner_base;
+
+        combiner_base = of_iomap(np, 0);
+        if (!combiner_base) {
+                pr_err("%s: failed to map combiner registers\n", __func__);
+                return -ENXIO;
+        }
+
+        combiner_init(combiner_base, np);
+
+        return 0;
+}
+
 static const struct of_device_id exynos4_dt_irq_match[] = {
         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { .compatible = "samsung,exynos4210-combiner",
+                        .data = combiner_of_init, },
         {},
 };
 #endif
 
 void __init exynos4_init_irq(void)
 {
-        int irq;
         unsigned int gic_bank_offset;
 
         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@@ -528,12 +614,8 @@ void __init exynos4_init_irq(void)
                 of_irq_init(exynos4_dt_irq_match);
 #endif
 
-        for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
-
-                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-                                COMBINER_IRQ(irq, 0));
-                combiner_cascade_irq(irq, IRQ_SPI(irq));
-        }
+        if (!of_have_populated_dt())
+                combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
         /*
          * The parameters of s5p_init_irq() are for VIC init.
@@ -545,18 +627,9 @@ void __init exynos4_init_irq(void)
 
 void __init exynos5_init_irq(void)
 {
-        int irq;
-
 #ifdef CONFIG_OF
         of_irq_init(exynos4_dt_irq_match);
 #endif
-
-        for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
-                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-                                COMBINER_IRQ(irq, 0));
-                combiner_cascade_irq(irq, IRQ_SPI(irq));
-        }
-
         /*
          * The parameters of s5p_init_irq() are for VIC init.
          * Theses parameters should be NULL and 0 because EXYNOS4
@@ -565,30 +638,18 @@ void __init exynos5_init_irq(void)
         s5p_init_irq(NULL, 0);
 }
 
-struct bus_type exynos4_subsys = {
-        .name           = "exynos4-core",
-        .dev_name       = "exynos4-core",
-};
-
-struct bus_type exynos5_subsys = {
-        .name           = "exynos5-core",
-        .dev_name       = "exynos5-core",
+struct bus_type exynos_subsys = {
+        .name           = "exynos-core",
+        .dev_name       = "exynos-core",
 };
 
 static struct device exynos4_dev = {
-        .bus    = &exynos4_subsys,
-};
-
-static struct device exynos5_dev = {
-        .bus    = &exynos5_subsys,
+        .bus    = &exynos_subsys,
 };
 
 static int __init exynos_core_init(void)
 {
-        if (soc_is_exynos5250())
-                return subsys_system_register(&exynos5_subsys, NULL);
-        else
-                return subsys_system_register(&exynos4_subsys, NULL);
+        return subsys_system_register(&exynos_subsys, NULL);
 }
 core_initcall(exynos_core_init);
 
@@ -675,10 +736,7 @@ static int __init exynos_init(void)
 {
         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
-        if (soc_is_exynos5250())
-                return device_register(&exynos5_dev);
-        else
-                return device_register(&exynos4_dev);
+        return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c
new file mode 100644
index 000000000000..17c9c6ecc2e0
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-drm.c
@@ -0,0 +1,29 @@
+/*
+ * linux/arch/arm/mach-exynos/dev-drm.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - core DRM device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <plat/devs.h>
+
+static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_drm = {
+        .name   = "exynos-drm",
+        .dev    = {
+                .dma_mask               = &exynos_drm_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 69aaa4503205..f60b66dbcf84 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -103,10 +103,45 @@ static u8 exynos4212_pdma0_peri[] = {
         DMACH_MIPI_HSI5,
 };
 
-struct dma_pl330_platdata exynos4_pdma0_pdata;
+static u8 exynos5250_pdma0_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM2_RX,
+        DMACH_PCM2_TX,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI2_RX,
+        DMACH_SPI2_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S2_RX,
+        DMACH_I2S2_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART4_RX,
+        DMACH_UART4_TX,
+        DMACH_SLIMBUS0_RX,
+        DMACH_SLIMBUS0_TX,
+        DMACH_SLIMBUS2_RX,
+        DMACH_SLIMBUS2_TX,
+        DMACH_SLIMBUS4_RX,
+        DMACH_SLIMBUS4_TX,
+        DMACH_AC97_MICIN,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_PCMOUT,
+        DMACH_MIPI_HSI0,
+        DMACH_MIPI_HSI2,
+        DMACH_MIPI_HSI4,
+        DMACH_MIPI_HSI6,
+};
+
+static struct dma_pl330_platdata exynos_pdma0_pdata;
 
-static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
-        EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
+static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
+        EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
 
 static u8 exynos4210_pdma1_peri[] = {
         DMACH_PCM0_RX,
@@ -169,10 +204,45 @@ static u8 exynos4212_pdma1_peri[] = {
         DMACH_MIPI_HSI7,
 };
 
-static struct dma_pl330_platdata exynos4_pdma1_pdata;
+static u8 exynos5250_pdma1_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM1_RX,
+        DMACH_PCM1_TX,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_PWM,
+        DMACH_SPDIF,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_SLIMBUS1_RX,
+        DMACH_SLIMBUS1_TX,
+        DMACH_SLIMBUS3_RX,
+        DMACH_SLIMBUS3_TX,
+        DMACH_SLIMBUS5_RX,
+        DMACH_SLIMBUS5_TX,
+        DMACH_SLIMBUS0AUX_RX,
+        DMACH_SLIMBUS0AUX_TX,
+        DMACH_DISP1,
+        DMACH_MIPI_HSI1,
+        DMACH_MIPI_HSI3,
+        DMACH_MIPI_HSI5,
+        DMACH_MIPI_HSI7,
+};
 
-static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
-        EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
+static struct dma_pl330_platdata exynos_pdma1_pdata;
+
+static AMBA_AHB_DEVICE(exynos_pdma1,  "dma-pl330.1", 0x00041330,
+        EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
 
 static u8 mdma_peri[] = {
         DMACH_MTOM_0,
@@ -185,46 +255,63 @@ static u8 mdma_peri[] = {
         DMACH_MTOM_7,
 };
 
-static struct dma_pl330_platdata exynos4_mdma1_pdata = {
+static struct dma_pl330_platdata exynos_mdma1_pdata = {
         .nr_valid_peri = ARRAY_SIZE(mdma_peri),
         .peri_id = mdma_peri,
 };
 
-static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,
-        EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
+static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,
+        EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
 
-static int __init exynos4_dma_init(void)
+static int __init exynos_dma_init(void)
 {
         if (of_have_populated_dt())
                 return 0;
 
         if (soc_is_exynos4210()) {
-                exynos4_pdma0_pdata.nr_valid_peri =
+                exynos_pdma0_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4210_pdma0_peri);
-                exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
-                exynos4_pdma1_pdata.nr_valid_peri =
+                exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
+                exynos_pdma1_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4210_pdma1_peri);
-                exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+                exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                exynos4_pdma0_pdata.nr_valid_peri =
+                exynos_pdma0_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4212_pdma0_peri);
-                exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
-                exynos4_pdma1_pdata.nr_valid_peri =
+                exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
+                exynos_pdma1_pdata.nr_valid_peri =
                         ARRAY_SIZE(exynos4212_pdma1_peri);
-                exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+                exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+        } else if (soc_is_exynos5250()) {
+                exynos_pdma0_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos5250_pdma0_peri);
+                exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
+                exynos_pdma1_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos5250_pdma1_peri);
+                exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
+
+                exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
+                exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
+                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
+                exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
+                exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
+                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
+                exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
+                exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
+                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
         }
 
-        dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
-        amba_device_register(&exynos4_pdma0_device, &iomem_resource);
+        dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
+        amba_device_register(&exynos_pdma0_device, &iomem_resource);
 
-        dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
-        amba_device_register(&exynos4_pdma1_device, &iomem_resource);
+        dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
+        amba_device_register(&exynos_pdma1_device, &iomem_resource);
 
-        dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
-        amba_device_register(&exynos4_mdma1_device, &iomem_resource);
+        dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
+        amba_device_register(&exynos_mdma1_device, &iomem_resource);
 
         return 0;
 }
-arch_initcall(exynos4_dma_init);
+arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index d7498afe036a..eb24f1eb8e3b 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
 #define EXYNOS5_GPIO_B2_NR      (4)
 #define EXYNOS5_GPIO_B3_NR      (4)
 #define EXYNOS5_GPIO_C0_NR      (7)
-#define EXYNOS5_GPIO_C1_NR      (7)
+#define EXYNOS5_GPIO_C1_NR      (4)
 #define EXYNOS5_GPIO_C2_NR      (7)
 #define EXYNOS5_GPIO_C3_NR      (7)
-#define EXYNOS5_GPIO_D0_NR      (8)
+#define EXYNOS5_GPIO_C4_NR      (7)
+#define EXYNOS5_GPIO_D0_NR      (4)
 #define EXYNOS5_GPIO_D1_NR      (8)
 #define EXYNOS5_GPIO_Y0_NR      (6)
 #define EXYNOS5_GPIO_Y1_NR      (4)
@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
         EXYNOS5_GPIO_C1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
         EXYNOS5_GPIO_C2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
         EXYNOS5_GPIO_C3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+        EXYNOS5_GPIO_C4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
         EXYNOS5_GPIO_D1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
         EXYNOS5_GPIO_Y0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
         EXYNOS5_GPIO_Y1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
 #define EXYNOS5_GPC1(_nr)       (EXYNOS5_GPIO_C1_START + (_nr))
 #define EXYNOS5_GPC2(_nr)       (EXYNOS5_GPIO_C2_START + (_nr))
 #define EXYNOS5_GPC3(_nr)       (EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr)       (EXYNOS5_GPIO_C4_START + (_nr))
 #define EXYNOS5_GPD0(_nr)       (EXYNOS5_GPIO_D0_START + (_nr))
 #define EXYNOS5_GPD1(_nr)       (EXYNOS5_GPIO_D1_START + (_nr))
 #define EXYNOS5_GPY0(_nr)       (EXYNOS5_GPIO_Y0_START + (_nr))
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index ddde8f3a24d4..7a4b4789eb72 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -287,6 +287,7 @@
 #define EXYNOS5_IRQ_MIPICSI1            IRQ_SPI(80)
 #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT   IRQ_SPI(81)
 #define EXYNOS5_IRQ_MIPIDSI0            IRQ_SPI(82)
+#define EXYNOS5_IRQ_WDT_IOP             IRQ_SPI(83)
 #define EXYNOS5_IRQ_ROTATOR             IRQ_SPI(84)
 #define EXYNOS5_IRQ_GSC0                IRQ_SPI(85)
 #define EXYNOS5_IRQ_GSC1                IRQ_SPI(86)
@@ -295,8 +296,8 @@
 #define EXYNOS5_IRQ_JPEG                IRQ_SPI(89)
 #define EXYNOS5_IRQ_EFNFCON_DMA         IRQ_SPI(90)
 #define EXYNOS5_IRQ_2D                  IRQ_SPI(91)
-#define EXYNOS5_IRQ_SFMC0               IRQ_SPI(92)
-#define EXYNOS5_IRQ_SFMC1               IRQ_SPI(93)
+#define EXYNOS5_IRQ_EFNFCON_0           IRQ_SPI(92)
+#define EXYNOS5_IRQ_EFNFCON_1           IRQ_SPI(93)
 #define EXYNOS5_IRQ_MIXER               IRQ_SPI(94)
 #define EXYNOS5_IRQ_HDMI                IRQ_SPI(95)
 #define EXYNOS5_IRQ_MFC                 IRQ_SPI(96)
@@ -310,7 +311,7 @@
 #define EXYNOS5_IRQ_PCM2                IRQ_SPI(104)
 #define EXYNOS5_IRQ_SPDIF               IRQ_SPI(105)
 #define EXYNOS5_IRQ_ADC0                IRQ_SPI(106)
-
+#define EXYNOS5_IRQ_ADC1                IRQ_SPI(107)
 #define EXYNOS5_IRQ_SATA_PHY            IRQ_SPI(108)
 #define EXYNOS5_IRQ_SATA_PMEMREQ        IRQ_SPI(109)
 #define EXYNOS5_IRQ_CAM_C               IRQ_SPI(110)
@@ -319,8 +320,9 @@
 #define EXYNOS5_IRQ_DP1_INTP1           IRQ_SPI(113)
 #define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
-#define EXYNOS5_IRQ_NFCON               IRQ_SPI(116)
 
+#define EXYNOS5_IRQ_MCT_L0              IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1              IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
@@ -328,7 +330,6 @@
 #define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
 
 #define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
-#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(1, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
 #define EXYNOS5_IRQ_SYSMMU_GSC0_1       COMBINER_IRQ(2, 1)
@@ -339,6 +340,8 @@
 #define EXYNOS5_IRQ_SYSMMU_GSC3_0       COMBINER_IRQ(2, 6)
 #define EXYNOS5_IRQ_SYSMMU_GSC3_1       COMBINER_IRQ(2, 7)
 
+#define EXYNOS5_IRQ_SYSMMU_LITE2_0      COMBINER_IRQ(3, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE2_1      COMBINER_IRQ(3, 1)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_0      COMBINER_IRQ(3, 2)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_1      COMBINER_IRQ(3, 3)
 #define EXYNOS5_IRQ_SYSMMU_LITE0_0      COMBINER_IRQ(3, 4)
@@ -362,8 +365,8 @@
 
 #define EXYNOS5_IRQ_SYSMMU_ARM_0        COMBINER_IRQ(6, 0)
 #define EXYNOS5_IRQ_SYSMMU_ARM_1        COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(6, 3)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_0       COMBINER_IRQ(6, 4)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_1       COMBINER_IRQ(6, 5)
 #define EXYNOS5_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(6, 6)
@@ -375,11 +378,9 @@
 #define EXYNOS5_IRQ_SYSMMU_MDMA1_1      COMBINER_IRQ(7, 3)
 #define EXYNOS5_IRQ_SYSMMU_TV_0         COMBINER_IRQ(7, 4)
 #define EXYNOS5_IRQ_SYSMMU_TV_1         COMBINER_IRQ(7, 5)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_0       COMBINER_IRQ(7, 6)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_1       COMBINER_IRQ(7, 7)
 
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(8, 6)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(8, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_DIS1_0       COMBINER_IRQ(9, 4)
 #define EXYNOS5_IRQ_SYSMMU_DIS1_1       COMBINER_IRQ(9, 5)
@@ -395,17 +396,24 @@
 #define EXYNOS5_IRQ_SYSMMU_DRC_0        COMBINER_IRQ(11, 6)
 #define EXYNOS5_IRQ_SYSMMU_DRC_1        COMBINER_IRQ(11, 7)
 
+#define EXYNOS5_IRQ_MDMA1_ABORT         COMBINER_IRQ(13, 1)
+
+#define EXYNOS5_IRQ_MDMA0_ABORT         COMBINER_IRQ(15, 3)
+
 #define EXYNOS5_IRQ_FIMD1_FIFO          COMBINER_IRQ(18, 4)
 #define EXYNOS5_IRQ_FIMD1_VSYNC         COMBINER_IRQ(18, 5)
 #define EXYNOS5_IRQ_FIMD1_SYSTEM        COMBINER_IRQ(18, 6)
 
+#define EXYNOS5_IRQ_ARMIOP_GIC          COMBINER_IRQ(19, 0)
+#define EXYNOS5_IRQ_ARMISP_GIC          COMBINER_IRQ(19, 1)
+#define EXYNOS5_IRQ_IOP_GIC             COMBINER_IRQ(19, 3)
+#define EXYNOS5_IRQ_ISP_GIC             COMBINER_IRQ(19, 4)
+
+#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
+
 #define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_L0              COMBINER_IRQ(23, 1)
-#define EXYNOS5_IRQ_MCT_L1              COMBINER_IRQ(23, 2)
 #define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
 #define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
-#define EXYNOS5_IRQ_MCT_G2              COMBINER_IRQ(23, 5)
-#define EXYNOS5_IRQ_MCT_G3              COMBINER_IRQ(23, 6)
 
 #define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
@@ -436,7 +444,7 @@
 
 #define EXYNOS5_MAX_COMBINER_NR         32
 
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     13
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     14
 #define EXYNOS5_IRQ_GPIO2_NR_GROUPS     9
 #define EXYNOS5_IRQ_GPIO3_NR_GROUPS     5
 #define EXYNOS5_IRQ_GPIO4_NR_GROUPS     1
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 2196af2d8218..ca4aa89aa46b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -34,6 +34,9 @@
 
 #define EXYNOS4_PA_JPEG                 0x11840000
 
+/* x = 0...1 */
+#define EXYNOS4_PA_FIMC_LITE(x)         (0x12390000 + ((x) * 0x10000))
+
 #define EXYNOS4_PA_G2D                  0x12800000
 
 #define EXYNOS4_PA_I2S0                 0x03830000
@@ -78,8 +81,8 @@
 
 #define EXYNOS4_PA_GIC_CPU              0x10480000
 #define EXYNOS4_PA_GIC_DIST             0x10490000
-#define EXYNOS5_PA_GIC_CPU              0x10480000
-#define EXYNOS5_PA_GIC_DIST             0x10490000
+#define EXYNOS5_PA_GIC_CPU              0x10482000
+#define EXYNOS5_PA_GIC_DIST             0x10481000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
 #define EXYNOS4_PA_TWD                  0x10500600
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index dba83e91f0fd..b78b5f3ad9c0 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -322,6 +322,8 @@
 #define EXYNOS5_CLKSRC_CDREX                    EXYNOS_CLKREG(0x20200)
 #define EXYNOS5_CLKDIV_CDREX                    EXYNOS_CLKREG(0x20500)
 
+#define EXYNOS5_PLL_DIV2_SEL                    EXYNOS_CLKREG(0x20A24)
+
 #define EXYNOS5_EPLL_LOCK                       EXYNOS_CLKREG(0x10030)
 
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d457d052a420..4dbb8629b200 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -180,7 +180,7 @@
 
 #define S5P_PMU_LCD1_CONF               S5P_PMUREG(0x3CA0)
 
-/* Only for EXYNOS4212 */
+/* Only for EXYNOS4x12 */
 #define S5P_ISP_ARM_LOWPWR                      S5P_PMUREG(0x1050)
 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR        S5P_PMUREG(0x1054)
 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR      S5P_PMUREG(0x1058)
@@ -221,4 +221,12 @@
 #define S5P_SECSS_MEM_OPTION                    S5P_PMUREG(0x2EC8)
 #define S5P_ROTATOR_MEM_OPTION                  S5P_PMUREG(0x2F48)
 
+/* Only for EXYNOS4412 */
+#define S5P_ARM_CORE2_LOWPWR                    S5P_PMUREG(0x1020)
+#define S5P_DIS_IRQ_CORE2                       S5P_PMUREG(0x1024)
+#define S5P_DIS_IRQ_CENTRAL2                    S5P_PMUREG(0x1028)
+#define S5P_ARM_CORE3_LOWPWR                    S5P_PMUREG(0x1030)
+#define S5P_DIS_IRQ_CORE3                       S5P_PMUREG(0x1034)
+#define S5P_DIS_IRQ_CENTRAL3                    S5P_PMUREG(0x1038)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
index 576efdf6d091..c71a5fba6a84 100644
--- a/arch/arm/mach-exynos/include/mach/spi-clocks.h
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -11,6 +11,6 @@
 #define __ASM_ARCH_SPI_CLKS_H __FILE__
 
 /* Must source from SCLK_SPI */
-#define EXYNOS4_SPI_SRCCLK_SCLK         0
+#define EXYNOS_SPI_SRCCLK_SCLK          0
 
 #endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 4711c8920e37..cf5d2228e998 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -43,6 +43,10 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                 "exynos4210-uart.2", NULL),
         OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
                                 "exynos4210-uart.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
+                                "s3c2440-i2c.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
+                                "s3c2440-i2c.1", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 897d9a9cf226..b601fb8a408b 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt;
         unsigned int cpu = smp_processor_id();
+        int mct_lx_irq;
 
         mevt = this_cpu_ptr(&percpu_mct_tick);
         mevt->evt = evt;
@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 
         if (mct_int_type == MCT_INT_SPI) {
                 if (cpu == 0) {
+                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
+                                                EXYNOS5_IRQ_MCT_L0;
                         mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = EXYNOS4_IRQ_MCT_L0;
-                        setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
+                        evt->irq = mct_lx_irq;
+                        setup_irq(mct_lx_irq, &mct_tick0_event_irq);
                 } else {
+                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
+                                                EXYNOS5_IRQ_MCT_L1;
                         mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = EXYNOS4_IRQ_MCT_L1;
-                        setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
-                        irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
+                        evt->irq = mct_lx_irq;
+                        setup_irq(mct_lx_irq, &mct_tick1_event_irq);
+                        irq_set_affinity(mct_lx_irq, cpumask_of(1));
                 }
         } else {
                 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
 
 static void __init exynos4_timer_init(void)
 {
-        if (soc_is_exynos4210())
+        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
                 mct_int_type = MCT_INT_SPI;
         else
                 mct_int_type = MCT_INT_PPI;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 428cfeb57724..563dea9a6dbb 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -275,7 +275,7 @@ static void exynos4_restore_pll(void)
 
 static struct subsys_interface exynos4_pm_interface = {
         .name           = "exynos4_pm",
-        .subsys         = &exynos4_subsys,
+        .subsys         = &exynos_subsys,
         .add_dev        = exynos4_pm_add,
 };
 
@@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void)
         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
-        if (soc_is_exynos4212()) {
+        if (soc_is_exynos4212() || soc_is_exynos4412()) {
                 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
                 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
                          S5P_USE_STANDBYWFE_ISP_ARM);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index bba48f5c3e8f..77c6815eebee 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
+static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
         { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
         { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
         { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
@@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
+static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
+        { S5P_ARM_CORE2_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+        { S5P_DIS_IRQ_CORE2,                    { 0x0, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_CENTRAL2,                 { 0x0, 0x0, 0x0 } },
+        { S5P_ARM_CORE3_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+        { S5P_DIS_IRQ_CORE3,                    { 0x0, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_CENTRAL3,                 { 0x0, 0x0, 0x0 } },
+        { PMU_TABLE_END,},
+};
+
 void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
 {
         unsigned int i;
@@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
         for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
                 __raw_writel(exynos4_pmu_config[i].val[mode],
                                 exynos4_pmu_config[i].reg);
+
+        if (soc_is_exynos4412()) {
+                for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
+                        __raw_writel(exynos4412_pmu_config[i].val[mode],
+                                exynos4412_pmu_config[i].reg);
+        }
 }
 
 static int __init exynos4_pmu_init(void)
@@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void)
         if (soc_is_exynos4210()) {
                 exynos4_pmu_config = exynos4210_pmu_config;
                 pr_info("EXYNOS4210 PMU Initialize\n");
-        } else if (soc_is_exynos4212()) {
-                exynos4_pmu_config = exynos4212_pmu_config;
-                pr_info("EXYNOS4212 PMU Initialize\n");
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                exynos4_pmu_config = exynos4x12_pmu_config;
+                pr_info("EXYNOS4x12 PMU Initialize\n");
         } else {
                 pr_info("EXYNOS4: PMU not supported\n");
         }