diff options
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r-- | arch/arm/mach-exynos/clock-exynos4.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-exynos/clock-exynos5.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-exynos/common.c | 14 | ||||
-rw-r--r-- | arch/arm/mach-exynos/dev-dwmci.c | 13 | ||||
-rw-r--r-- | arch/arm/mach-exynos/mach-nuri.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-exynos/mach-universal_c210.c | 1 |
6 files changed, 42 insertions, 35 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index df54c2a92225..6efd1e5919fd 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c | |||
@@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = { | |||
497 | .ctrlbit = (1 << 3), | 497 | .ctrlbit = (1 << 3), |
498 | }, { | 498 | }, { |
499 | .name = "hsmmc", | 499 | .name = "hsmmc", |
500 | .devname = "s3c-sdhci.0", | 500 | .devname = "exynos4-sdhci.0", |
501 | .parent = &exynos4_clk_aclk_133.clk, | 501 | .parent = &exynos4_clk_aclk_133.clk, |
502 | .enable = exynos4_clk_ip_fsys_ctrl, | 502 | .enable = exynos4_clk_ip_fsys_ctrl, |
503 | .ctrlbit = (1 << 5), | 503 | .ctrlbit = (1 << 5), |
504 | }, { | 504 | }, { |
505 | .name = "hsmmc", | 505 | .name = "hsmmc", |
506 | .devname = "s3c-sdhci.1", | 506 | .devname = "exynos4-sdhci.1", |
507 | .parent = &exynos4_clk_aclk_133.clk, | 507 | .parent = &exynos4_clk_aclk_133.clk, |
508 | .enable = exynos4_clk_ip_fsys_ctrl, | 508 | .enable = exynos4_clk_ip_fsys_ctrl, |
509 | .ctrlbit = (1 << 6), | 509 | .ctrlbit = (1 << 6), |
510 | }, { | 510 | }, { |
511 | .name = "hsmmc", | 511 | .name = "hsmmc", |
512 | .devname = "s3c-sdhci.2", | 512 | .devname = "exynos4-sdhci.2", |
513 | .parent = &exynos4_clk_aclk_133.clk, | 513 | .parent = &exynos4_clk_aclk_133.clk, |
514 | .enable = exynos4_clk_ip_fsys_ctrl, | 514 | .enable = exynos4_clk_ip_fsys_ctrl, |
515 | .ctrlbit = (1 << 7), | 515 | .ctrlbit = (1 << 7), |
516 | }, { | 516 | }, { |
517 | .name = "hsmmc", | 517 | .name = "hsmmc", |
518 | .devname = "s3c-sdhci.3", | 518 | .devname = "exynos4-sdhci.3", |
519 | .parent = &exynos4_clk_aclk_133.clk, | 519 | .parent = &exynos4_clk_aclk_133.clk, |
520 | .enable = exynos4_clk_ip_fsys_ctrl, | 520 | .enable = exynos4_clk_ip_fsys_ctrl, |
521 | .ctrlbit = (1 << 8), | 521 | .ctrlbit = (1 << 8), |
@@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = { | |||
1202 | static struct clksrc_clk exynos4_clk_sclk_mmc0 = { | 1202 | static struct clksrc_clk exynos4_clk_sclk_mmc0 = { |
1203 | .clk = { | 1203 | .clk = { |
1204 | .name = "sclk_mmc", | 1204 | .name = "sclk_mmc", |
1205 | .devname = "s3c-sdhci.0", | 1205 | .devname = "exynos4-sdhci.0", |
1206 | .parent = &exynos4_clk_dout_mmc0.clk, | 1206 | .parent = &exynos4_clk_dout_mmc0.clk, |
1207 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1207 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1208 | .ctrlbit = (1 << 0), | 1208 | .ctrlbit = (1 << 0), |
@@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = { | |||
1213 | static struct clksrc_clk exynos4_clk_sclk_mmc1 = { | 1213 | static struct clksrc_clk exynos4_clk_sclk_mmc1 = { |
1214 | .clk = { | 1214 | .clk = { |
1215 | .name = "sclk_mmc", | 1215 | .name = "sclk_mmc", |
1216 | .devname = "s3c-sdhci.1", | 1216 | .devname = "exynos4-sdhci.1", |
1217 | .parent = &exynos4_clk_dout_mmc1.clk, | 1217 | .parent = &exynos4_clk_dout_mmc1.clk, |
1218 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1218 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1219 | .ctrlbit = (1 << 4), | 1219 | .ctrlbit = (1 << 4), |
@@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = { | |||
1224 | static struct clksrc_clk exynos4_clk_sclk_mmc2 = { | 1224 | static struct clksrc_clk exynos4_clk_sclk_mmc2 = { |
1225 | .clk = { | 1225 | .clk = { |
1226 | .name = "sclk_mmc", | 1226 | .name = "sclk_mmc", |
1227 | .devname = "s3c-sdhci.2", | 1227 | .devname = "exynos4-sdhci.2", |
1228 | .parent = &exynos4_clk_dout_mmc2.clk, | 1228 | .parent = &exynos4_clk_dout_mmc2.clk, |
1229 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1229 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1230 | .ctrlbit = (1 << 8), | 1230 | .ctrlbit = (1 << 8), |
@@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = { | |||
1235 | static struct clksrc_clk exynos4_clk_sclk_mmc3 = { | 1235 | static struct clksrc_clk exynos4_clk_sclk_mmc3 = { |
1236 | .clk = { | 1236 | .clk = { |
1237 | .name = "sclk_mmc", | 1237 | .name = "sclk_mmc", |
1238 | .devname = "s3c-sdhci.3", | 1238 | .devname = "exynos4-sdhci.3", |
1239 | .parent = &exynos4_clk_dout_mmc3.clk, | 1239 | .parent = &exynos4_clk_dout_mmc3.clk, |
1240 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1240 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1241 | .ctrlbit = (1 << 12), | 1241 | .ctrlbit = (1 << 12), |
@@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { | |||
1340 | CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), | 1340 | CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), |
1341 | CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), | 1341 | CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), |
1342 | CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), | 1342 | CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), |
1343 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), | 1343 | CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), |
1344 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), | 1344 | CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), |
1345 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), | 1345 | CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), |
1346 | CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), | 1346 | CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), |
1347 | CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), | 1347 | CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), |
1348 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), | 1348 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), |
1349 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), | 1349 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), |
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index d013982d0f8e..5cd7a8b8868c 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c | |||
@@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = { | |||
455 | .ctrlbit = (1 << 20), | 455 | .ctrlbit = (1 << 20), |
456 | }, { | 456 | }, { |
457 | .name = "hsmmc", | 457 | .name = "hsmmc", |
458 | .devname = "s3c-sdhci.0", | 458 | .devname = "exynos4-sdhci.0", |
459 | .parent = &exynos5_clk_aclk_200.clk, | 459 | .parent = &exynos5_clk_aclk_200.clk, |
460 | .enable = exynos5_clk_ip_fsys_ctrl, | 460 | .enable = exynos5_clk_ip_fsys_ctrl, |
461 | .ctrlbit = (1 << 12), | 461 | .ctrlbit = (1 << 12), |
462 | }, { | 462 | }, { |
463 | .name = "hsmmc", | 463 | .name = "hsmmc", |
464 | .devname = "s3c-sdhci.1", | 464 | .devname = "exynos4-sdhci.1", |
465 | .parent = &exynos5_clk_aclk_200.clk, | 465 | .parent = &exynos5_clk_aclk_200.clk, |
466 | .enable = exynos5_clk_ip_fsys_ctrl, | 466 | .enable = exynos5_clk_ip_fsys_ctrl, |
467 | .ctrlbit = (1 << 13), | 467 | .ctrlbit = (1 << 13), |
468 | }, { | 468 | }, { |
469 | .name = "hsmmc", | 469 | .name = "hsmmc", |
470 | .devname = "s3c-sdhci.2", | 470 | .devname = "exynos4-sdhci.2", |
471 | .parent = &exynos5_clk_aclk_200.clk, | 471 | .parent = &exynos5_clk_aclk_200.clk, |
472 | .enable = exynos5_clk_ip_fsys_ctrl, | 472 | .enable = exynos5_clk_ip_fsys_ctrl, |
473 | .ctrlbit = (1 << 14), | 473 | .ctrlbit = (1 << 14), |
474 | }, { | 474 | }, { |
475 | .name = "hsmmc", | 475 | .name = "hsmmc", |
476 | .devname = "s3c-sdhci.3", | 476 | .devname = "exynos4-sdhci.3", |
477 | .parent = &exynos5_clk_aclk_200.clk, | 477 | .parent = &exynos5_clk_aclk_200.clk, |
478 | .enable = exynos5_clk_ip_fsys_ctrl, | 478 | .enable = exynos5_clk_ip_fsys_ctrl, |
479 | .ctrlbit = (1 << 15), | 479 | .ctrlbit = (1 << 15), |
@@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { | |||
813 | static struct clksrc_clk exynos5_clk_sclk_mmc0 = { | 813 | static struct clksrc_clk exynos5_clk_sclk_mmc0 = { |
814 | .clk = { | 814 | .clk = { |
815 | .name = "sclk_mmc", | 815 | .name = "sclk_mmc", |
816 | .devname = "s3c-sdhci.0", | 816 | .devname = "exynos4-sdhci.0", |
817 | .parent = &exynos5_clk_dout_mmc0.clk, | 817 | .parent = &exynos5_clk_dout_mmc0.clk, |
818 | .enable = exynos5_clksrc_mask_fsys_ctrl, | 818 | .enable = exynos5_clksrc_mask_fsys_ctrl, |
819 | .ctrlbit = (1 << 0), | 819 | .ctrlbit = (1 << 0), |
@@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { | |||
824 | static struct clksrc_clk exynos5_clk_sclk_mmc1 = { | 824 | static struct clksrc_clk exynos5_clk_sclk_mmc1 = { |
825 | .clk = { | 825 | .clk = { |
826 | .name = "sclk_mmc", | 826 | .name = "sclk_mmc", |
827 | .devname = "s3c-sdhci.1", | 827 | .devname = "exynos4-sdhci.1", |
828 | .parent = &exynos5_clk_dout_mmc1.clk, | 828 | .parent = &exynos5_clk_dout_mmc1.clk, |
829 | .enable = exynos5_clksrc_mask_fsys_ctrl, | 829 | .enable = exynos5_clksrc_mask_fsys_ctrl, |
830 | .ctrlbit = (1 << 4), | 830 | .ctrlbit = (1 << 4), |
@@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { | |||
835 | static struct clksrc_clk exynos5_clk_sclk_mmc2 = { | 835 | static struct clksrc_clk exynos5_clk_sclk_mmc2 = { |
836 | .clk = { | 836 | .clk = { |
837 | .name = "sclk_mmc", | 837 | .name = "sclk_mmc", |
838 | .devname = "s3c-sdhci.2", | 838 | .devname = "exynos4-sdhci.2", |
839 | .parent = &exynos5_clk_dout_mmc2.clk, | 839 | .parent = &exynos5_clk_dout_mmc2.clk, |
840 | .enable = exynos5_clksrc_mask_fsys_ctrl, | 840 | .enable = exynos5_clksrc_mask_fsys_ctrl, |
841 | .ctrlbit = (1 << 8), | 841 | .ctrlbit = (1 << 8), |
@@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { | |||
846 | static struct clksrc_clk exynos5_clk_sclk_mmc3 = { | 846 | static struct clksrc_clk exynos5_clk_sclk_mmc3 = { |
847 | .clk = { | 847 | .clk = { |
848 | .name = "sclk_mmc", | 848 | .name = "sclk_mmc", |
849 | .devname = "s3c-sdhci.3", | 849 | .devname = "exynos4-sdhci.3", |
850 | .parent = &exynos5_clk_dout_mmc3.clk, | 850 | .parent = &exynos5_clk_dout_mmc3.clk, |
851 | .enable = exynos5_clksrc_mask_fsys_ctrl, | 851 | .enable = exynos5_clksrc_mask_fsys_ctrl, |
852 | .ctrlbit = (1 << 12), | 852 | .ctrlbit = (1 << 12), |
@@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = { | |||
990 | CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk), | 990 | CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk), |
991 | CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk), | 991 | CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk), |
992 | CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk), | 992 | CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk), |
993 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), | 993 | CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), |
994 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), | 994 | CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), |
995 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), | 995 | CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), |
996 | CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), | 996 | CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), |
997 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), | 997 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), |
998 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), | 998 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), |
999 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), | 999 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), |
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 8614aab47cc0..5ccd6e80a607 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -326,6 +326,11 @@ static void __init exynos4_map_io(void) | |||
326 | s3c_fimc_setname(2, "exynos4-fimc"); | 326 | s3c_fimc_setname(2, "exynos4-fimc"); |
327 | s3c_fimc_setname(3, "exynos4-fimc"); | 327 | s3c_fimc_setname(3, "exynos4-fimc"); |
328 | 328 | ||
329 | s3c_sdhci_setname(0, "exynos4-sdhci"); | ||
330 | s3c_sdhci_setname(1, "exynos4-sdhci"); | ||
331 | s3c_sdhci_setname(2, "exynos4-sdhci"); | ||
332 | s3c_sdhci_setname(3, "exynos4-sdhci"); | ||
333 | |||
329 | /* The I2C bus controllers are directly compatible with s3c2440 */ | 334 | /* The I2C bus controllers are directly compatible with s3c2440 */ |
330 | s3c_i2c0_setname("s3c2440-i2c"); | 335 | s3c_i2c0_setname("s3c2440-i2c"); |
331 | s3c_i2c1_setname("s3c2440-i2c"); | 336 | s3c_i2c1_setname("s3c2440-i2c"); |
@@ -344,6 +349,11 @@ static void __init exynos5_map_io(void) | |||
344 | s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC; | 349 | s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC; |
345 | s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC; | 350 | s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC; |
346 | 351 | ||
352 | s3c_sdhci_setname(0, "exynos4-sdhci"); | ||
353 | s3c_sdhci_setname(1, "exynos4-sdhci"); | ||
354 | s3c_sdhci_setname(2, "exynos4-sdhci"); | ||
355 | s3c_sdhci_setname(3, "exynos4-sdhci"); | ||
356 | |||
347 | /* The I2C bus controllers are directly compatible with s3c2440 */ | 357 | /* The I2C bus controllers are directly compatible with s3c2440 */ |
348 | s3c_i2c0_setname("s3c2440-i2c"); | 358 | s3c_i2c0_setname("s3c2440-i2c"); |
349 | s3c_i2c1_setname("s3c2440-i2c"); | 359 | s3c_i2c1_setname("s3c2440-i2c"); |
@@ -537,7 +547,9 @@ void __init exynos5_init_irq(void) | |||
537 | { | 547 | { |
538 | int irq; | 548 | int irq; |
539 | 549 | ||
540 | gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); | 550 | #ifdef CONFIG_OF |
551 | of_irq_init(exynos4_dt_irq_match); | ||
552 | #endif | ||
541 | 553 | ||
542 | for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) { | 554 | for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) { |
543 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), | 555 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), |
diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c index b025db4bf602..79035018fb74 100644 --- a/arch/arm/mach-exynos/dev-dwmci.c +++ b/arch/arm/mach-exynos/dev-dwmci.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/dma-mapping.h> | 16 | #include <linux/dma-mapping.h> |
17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
18 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
19 | #include <linux/ioport.h> | ||
19 | #include <linux/mmc/dw_mmc.h> | 20 | #include <linux/mmc/dw_mmc.h> |
20 | 21 | ||
21 | #include <plat/devs.h> | 22 | #include <plat/devs.h> |
@@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data) | |||
33 | } | 34 | } |
34 | 35 | ||
35 | static struct resource exynos4_dwmci_resource[] = { | 36 | static struct resource exynos4_dwmci_resource[] = { |
36 | [0] = { | 37 | [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K), |
37 | .start = EXYNOS4_PA_DWMCI, | 38 | [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI), |
38 | .end = EXYNOS4_PA_DWMCI + SZ_4K - 1, | ||
39 | .flags = IORESOURCE_MEM, | ||
40 | }, | ||
41 | [1] = { | ||
42 | .start = IRQ_DWMCI, | ||
43 | .end = IRQ_DWMCI, | ||
44 | .flags = IORESOURCE_IRQ, | ||
45 | } | ||
46 | }; | 39 | }; |
47 | 40 | ||
48 | static struct dw_mci_board exynos4_dwci_pdata = { | 41 | static struct dw_mci_board exynos4_dwci_pdata = { |
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index e284b0e4ca2e..9c97d7ca389c 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c | |||
@@ -113,6 +113,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = { | |||
113 | .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | | 113 | .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | |
114 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | | 114 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
115 | MMC_CAP_ERASE), | 115 | MMC_CAP_ERASE), |
116 | .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, | ||
116 | .cd_type = S3C_SDHCI_CD_PERMANENT, | 117 | .cd_type = S3C_SDHCI_CD_PERMANENT, |
117 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | 118 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, |
118 | }; | 119 | }; |
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index ad15d0fda3c1..62f159a6583c 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c | |||
@@ -748,6 +748,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { | |||
748 | .max_width = 8, | 748 | .max_width = 8, |
749 | .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | | 749 | .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | |
750 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), | 750 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), |
751 | .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, | ||
751 | .cd_type = S3C_SDHCI_CD_PERMANENT, | 752 | .cd_type = S3C_SDHCI_CD_PERMANENT, |
752 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | 753 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, |
753 | }; | 754 | }; |