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-rw-r--r--arch/arm/mach-exynos/Kconfig36
-rw-r--r--arch/arm/mach-exynos/Makefile8
-rw-r--r--arch/arm/mach-exynos/clock.c302
-rw-r--r--arch/arm/mach-exynos/common.c53
-rw-r--r--arch/arm/mach-exynos/dev-ohci.c52
-rw-r--r--arch/arm/mach-exynos/dma.c229
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h11
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h8
-rw-r--r--arch/arm/mach-exynos/include/mach/ohci.h21
-rw-r--r--arch/arm/mach-exynos/include/mach/spi-clocks.h16
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c85
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c9
-rw-r--r--arch/arm/mach-exynos/mach-origen.c13
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c17
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c10
-rw-r--r--arch/arm/mach-exynos/pm.c24
-rw-r--r--arch/arm/mach-exynos/setup-sdhci.c22
-rw-r--r--arch/arm/mach-exynos/setup-spi.c72
-rw-r--r--arch/arm/mach-exynos/setup-usb-phy.c15
19 files changed, 626 insertions, 377 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e1efbca2a539..5d602f68a0e8 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -59,6 +59,11 @@ config EXYNOS4_MCT
59 help 59 help
60 Use MCT (Multi Core Timer) as kernel timers 60 Use MCT (Multi Core Timer) as kernel timers
61 61
62config EXYNOS4_DEV_DMA
63 bool
64 help
65 Compile in amba device definitions for DMA controller
66
62config EXYNOS4_DEV_AHCI 67config EXYNOS4_DEV_AHCI
63 bool 68 bool
64 help 69 help
@@ -84,6 +89,11 @@ config EXYNOS4_DEV_DWMCI
84 help 89 help
85 Compile in platform device definitions for DWMCI 90 Compile in platform device definitions for DWMCI
86 91
92config EXYNOS4_DEV_USB_OHCI
93 bool
94 help
95 Compile in platform device definition for USB OHCI
96
87config EXYNOS4_SETUP_I2C1 97config EXYNOS4_SETUP_I2C1
88 bool 98 bool
89 help 99 help
@@ -145,6 +155,11 @@ config EXYNOS4_SETUP_USB_PHY
145 help 155 help
146 Common setup code for USB PHY controller 156 Common setup code for USB PHY controller
147 157
158config EXYNOS4_SETUP_SPI
159 bool
160 help
161 Common setup code for SPI GPIO configurations.
162
148# machine support 163# machine support
149 164
150if ARCH_EXYNOS4 165if ARCH_EXYNOS4
@@ -179,8 +194,10 @@ config MACH_SMDKV310
179 select SAMSUNG_DEV_BACKLIGHT 194 select SAMSUNG_DEV_BACKLIGHT
180 select EXYNOS4_DEV_AHCI 195 select EXYNOS4_DEV_AHCI
181 select SAMSUNG_DEV_KEYPAD 196 select SAMSUNG_DEV_KEYPAD
197 select EXYNOS4_DEV_DMA
182 select EXYNOS4_DEV_PD 198 select EXYNOS4_DEV_PD
183 select SAMSUNG_DEV_PWM 199 select SAMSUNG_DEV_PWM
200 select EXYNOS4_DEV_USB_OHCI
184 select EXYNOS4_DEV_SYSMMU 201 select EXYNOS4_DEV_SYSMMU
185 select EXYNOS4_SETUP_FIMD0 202 select EXYNOS4_SETUP_FIMD0
186 select EXYNOS4_SETUP_I2C1 203 select EXYNOS4_SETUP_I2C1
@@ -199,6 +216,7 @@ config MACH_ARMLEX4210
199 select S3C_DEV_HSMMC2 216 select S3C_DEV_HSMMC2
200 select S3C_DEV_HSMMC3 217 select S3C_DEV_HSMMC3
201 select EXYNOS4_DEV_AHCI 218 select EXYNOS4_DEV_AHCI
219 select EXYNOS4_DEV_DMA
202 select EXYNOS4_DEV_SYSMMU 220 select EXYNOS4_DEV_SYSMMU
203 select EXYNOS4_SETUP_SDHCI 221 select EXYNOS4_SETUP_SDHCI
204 help 222 help
@@ -224,6 +242,7 @@ config MACH_UNIVERSAL_C210
224 select S5P_DEV_MFC 242 select S5P_DEV_MFC
225 select S5P_DEV_ONENAND 243 select S5P_DEV_ONENAND
226 select S5P_DEV_TV 244 select S5P_DEV_TV
245 select EXYNOS4_DEV_DMA
227 select EXYNOS4_DEV_PD 246 select EXYNOS4_DEV_PD
228 select EXYNOS4_SETUP_FIMD0 247 select EXYNOS4_SETUP_FIMD0
229 select EXYNOS4_SETUP_I2C1 248 select EXYNOS4_SETUP_I2C1
@@ -257,6 +276,7 @@ config MACH_NURI
257 select S5P_DEV_MFC 276 select S5P_DEV_MFC
258 select S5P_DEV_USB_EHCI 277 select S5P_DEV_USB_EHCI
259 select S5P_SETUP_MIPIPHY 278 select S5P_SETUP_MIPIPHY
279 select EXYNOS4_DEV_DMA
260 select EXYNOS4_DEV_PD 280 select EXYNOS4_DEV_PD
261 select EXYNOS4_SETUP_FIMC 281 select EXYNOS4_SETUP_FIMC
262 select EXYNOS4_SETUP_FIMD0 282 select EXYNOS4_SETUP_FIMD0
@@ -289,7 +309,9 @@ config MACH_ORIGEN
289 select S5P_DEV_USB_EHCI 309 select S5P_DEV_USB_EHCI
290 select SAMSUNG_DEV_BACKLIGHT 310 select SAMSUNG_DEV_BACKLIGHT
291 select SAMSUNG_DEV_PWM 311 select SAMSUNG_DEV_PWM
312 select EXYNOS4_DEV_DMA
292 select EXYNOS4_DEV_PD 313 select EXYNOS4_DEV_PD
314 select EXYNOS4_DEV_USB_OHCI
293 select EXYNOS4_SETUP_FIMD0 315 select EXYNOS4_SETUP_FIMD0
294 select EXYNOS4_SETUP_SDHCI 316 select EXYNOS4_SETUP_SDHCI
295 select EXYNOS4_SETUP_USB_PHY 317 select EXYNOS4_SETUP_USB_PHY
@@ -329,6 +351,20 @@ config MACH_SMDK4412
329 Machine support for Samsung SMDK4412 351 Machine support for Samsung SMDK4412
330endif 352endif
331 353
354comment "Flattened Device Tree based board for Exynos4 based SoC"
355
356config MACH_EXYNOS4_DT
357 bool "Samsung Exynos4 Machine using device tree"
358 select CPU_EXYNOS4210
359 select USE_OF
360 select ARM_AMBA
361 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
362 help
363 Machine support for Samsung Exynos4 machine with device tree enabled.
364 Select this if a fdt blob is available for the Exynos4 SoC based board.
365 Note: This is under development and not all peripherals can be supported
366 with this machine file.
367
332if ARCH_EXYNOS4 368if ARCH_EXYNOS4
333 369
334comment "Configuration for HSMMC 8-bit bus width" 370comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index bcb9efc576e9..5fc202cdfdb6 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
19obj-$(CONFIG_PM) += pm.o 19obj-$(CONFIG_PM) += pm.o
20obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
21 21
22obj-$(CONFIG_ARCH_EXYNOS4) += dma.o pmu.o 22obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o
23 23
24obj-$(CONFIG_SMP) += platsmp.o headsmp.o 24obj-$(CONFIG_SMP) += platsmp.o headsmp.o
25 25
@@ -39,6 +39,8 @@ obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
39obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o 39obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
40obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o 40obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
41 41
42obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
43
42# device support 44# device support
43 45
44obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 46obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
@@ -46,6 +48,8 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
46obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o 48obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
47obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 49obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
48obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o 50obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
51obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
52obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
49 53
50obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o 54obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o
51obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 55obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
@@ -58,6 +62,6 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
58obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o 62obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
59obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o 63obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
60obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 64obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
61obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
62obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 65obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
63obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o 66obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
67obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 83616a039b15..5a8c42e90005 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -554,16 +554,6 @@ static struct clk init_clocks_off[] = {
554 .enable = exynos4_clk_dac_ctrl, 554 .enable = exynos4_clk_dac_ctrl,
555 .ctrlbit = (1 << 0), 555 .ctrlbit = (1 << 0),
556 }, { 556 }, {
557 .name = "dma",
558 .devname = "dma-pl330.0",
559 .enable = exynos4_clk_ip_fsys_ctrl,
560 .ctrlbit = (1 << 0),
561 }, {
562 .name = "dma",
563 .devname = "dma-pl330.1",
564 .enable = exynos4_clk_ip_fsys_ctrl,
565 .ctrlbit = (1 << 1),
566 }, {
567 .name = "adc", 557 .name = "adc",
568 .enable = exynos4_clk_ip_peril_ctrl, 558 .enable = exynos4_clk_ip_peril_ctrl,
569 .ctrlbit = (1 << 15), 559 .ctrlbit = (1 << 15),
@@ -779,6 +769,20 @@ static struct clk init_clocks[] = {
779 } 769 }
780}; 770};
781 771
772static struct clk clk_pdma0 = {
773 .name = "dma",
774 .devname = "dma-pl330.0",
775 .enable = exynos4_clk_ip_fsys_ctrl,
776 .ctrlbit = (1 << 0),
777};
778
779static struct clk clk_pdma1 = {
780 .name = "dma",
781 .devname = "dma-pl330.1",
782 .enable = exynos4_clk_ip_fsys_ctrl,
783 .ctrlbit = (1 << 1),
784};
785
782struct clk *clkset_group_list[] = { 786struct clk *clkset_group_list[] = {
783 [0] = &clk_ext_xtal_mux, 787 [0] = &clk_ext_xtal_mux,
784 [1] = &clk_xusbxti, 788 [1] = &clk_xusbxti,
@@ -1010,46 +1014,6 @@ static struct clksrc_clk clk_dout_mmc4 = {
1010 1014
1011static struct clksrc_clk clksrcs[] = { 1015static struct clksrc_clk clksrcs[] = {
1012 { 1016 {
1013 .clk = {
1014 .name = "uclk1",
1015 .devname = "s5pv210-uart.0",
1016 .enable = exynos4_clksrc_mask_peril0_ctrl,
1017 .ctrlbit = (1 << 0),
1018 },
1019 .sources = &clkset_group,
1020 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1021 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1022 }, {
1023 .clk = {
1024 .name = "uclk1",
1025 .devname = "s5pv210-uart.1",
1026 .enable = exynos4_clksrc_mask_peril0_ctrl,
1027 .ctrlbit = (1 << 4),
1028 },
1029 .sources = &clkset_group,
1030 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1031 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1032 }, {
1033 .clk = {
1034 .name = "uclk1",
1035 .devname = "s5pv210-uart.2",
1036 .enable = exynos4_clksrc_mask_peril0_ctrl,
1037 .ctrlbit = (1 << 8),
1038 },
1039 .sources = &clkset_group,
1040 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1041 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1042 }, {
1043 .clk = {
1044 .name = "uclk1",
1045 .devname = "s5pv210-uart.3",
1046 .enable = exynos4_clksrc_mask_peril0_ctrl,
1047 .ctrlbit = (1 << 12),
1048 },
1049 .sources = &clkset_group,
1050 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1051 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1052 }, {
1053 .clk = { 1017 .clk = {
1054 .name = "sclk_pwm", 1018 .name = "sclk_pwm",
1055 .enable = exynos4_clksrc_mask_peril0_ctrl, 1019 .enable = exynos4_clksrc_mask_peril0_ctrl,
@@ -1148,36 +1112,6 @@ static struct clksrc_clk clksrcs[] = {
1148 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, 1112 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1149 }, { 1113 }, {
1150 .clk = { 1114 .clk = {
1151 .name = "sclk_spi",
1152 .devname = "s3c64xx-spi.0",
1153 .enable = exynos4_clksrc_mask_peril1_ctrl,
1154 .ctrlbit = (1 << 16),
1155 },
1156 .sources = &clkset_group,
1157 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1158 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1159 }, {
1160 .clk = {
1161 .name = "sclk_spi",
1162 .devname = "s3c64xx-spi.1",
1163 .enable = exynos4_clksrc_mask_peril1_ctrl,
1164 .ctrlbit = (1 << 20),
1165 },
1166 .sources = &clkset_group,
1167 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1168 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1169 }, {
1170 .clk = {
1171 .name = "sclk_spi",
1172 .devname = "s3c64xx-spi.2",
1173 .enable = exynos4_clksrc_mask_peril1_ctrl,
1174 .ctrlbit = (1 << 24),
1175 },
1176 .sources = &clkset_group,
1177 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1178 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1179 }, {
1180 .clk = {
1181 .name = "sclk_fimg2d", 1115 .name = "sclk_fimg2d",
1182 }, 1116 },
1183 .sources = &clkset_mout_g2d, 1117 .sources = &clkset_mout_g2d,
@@ -1193,42 +1127,6 @@ static struct clksrc_clk clksrcs[] = {
1193 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, 1127 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1194 }, { 1128 }, {
1195 .clk = { 1129 .clk = {
1196 .name = "sclk_mmc",
1197 .devname = "s3c-sdhci.0",
1198 .parent = &clk_dout_mmc0.clk,
1199 .enable = exynos4_clksrc_mask_fsys_ctrl,
1200 .ctrlbit = (1 << 0),
1201 },
1202 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1203 }, {
1204 .clk = {
1205 .name = "sclk_mmc",
1206 .devname = "s3c-sdhci.1",
1207 .parent = &clk_dout_mmc1.clk,
1208 .enable = exynos4_clksrc_mask_fsys_ctrl,
1209 .ctrlbit = (1 << 4),
1210 },
1211 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1212 }, {
1213 .clk = {
1214 .name = "sclk_mmc",
1215 .devname = "s3c-sdhci.2",
1216 .parent = &clk_dout_mmc2.clk,
1217 .enable = exynos4_clksrc_mask_fsys_ctrl,
1218 .ctrlbit = (1 << 8),
1219 },
1220 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1221 }, {
1222 .clk = {
1223 .name = "sclk_mmc",
1224 .devname = "s3c-sdhci.3",
1225 .parent = &clk_dout_mmc3.clk,
1226 .enable = exynos4_clksrc_mask_fsys_ctrl,
1227 .ctrlbit = (1 << 12),
1228 },
1229 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1230 }, {
1231 .clk = {
1232 .name = "sclk_dwmmc", 1130 .name = "sclk_dwmmc",
1233 .parent = &clk_dout_mmc4.clk, 1131 .parent = &clk_dout_mmc4.clk,
1234 .enable = exynos4_clksrc_mask_fsys_ctrl, 1132 .enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1238,6 +1136,134 @@ static struct clksrc_clk clksrcs[] = {
1238 } 1136 }
1239}; 1137};
1240 1138
1139static struct clksrc_clk clk_sclk_uart0 = {
1140 .clk = {
1141 .name = "uclk1",
1142 .devname = "exynos4210-uart.0",
1143 .enable = exynos4_clksrc_mask_peril0_ctrl,
1144 .ctrlbit = (1 << 0),
1145 },
1146 .sources = &clkset_group,
1147 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1148 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1149};
1150
1151static struct clksrc_clk clk_sclk_uart1 = {
1152 .clk = {
1153 .name = "uclk1",
1154 .devname = "exynos4210-uart.1",
1155 .enable = exynos4_clksrc_mask_peril0_ctrl,
1156 .ctrlbit = (1 << 4),
1157 },
1158 .sources = &clkset_group,
1159 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1160 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1161};
1162
1163static struct clksrc_clk clk_sclk_uart2 = {
1164 .clk = {
1165 .name = "uclk1",
1166 .devname = "exynos4210-uart.2",
1167 .enable = exynos4_clksrc_mask_peril0_ctrl,
1168 .ctrlbit = (1 << 8),
1169 },
1170 .sources = &clkset_group,
1171 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1172 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1173};
1174
1175static struct clksrc_clk clk_sclk_uart3 = {
1176 .clk = {
1177 .name = "uclk1",
1178 .devname = "exynos4210-uart.3",
1179 .enable = exynos4_clksrc_mask_peril0_ctrl,
1180 .ctrlbit = (1 << 12),
1181 },
1182 .sources = &clkset_group,
1183 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1184 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1185};
1186
1187static struct clksrc_clk clk_sclk_mmc0 = {
1188 .clk = {
1189 .name = "sclk_mmc",
1190 .devname = "s3c-sdhci.0",
1191 .parent = &clk_dout_mmc0.clk,
1192 .enable = exynos4_clksrc_mask_fsys_ctrl,
1193 .ctrlbit = (1 << 0),
1194 },
1195 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1196};
1197
1198static struct clksrc_clk clk_sclk_mmc1 = {
1199 .clk = {
1200 .name = "sclk_mmc",
1201 .devname = "s3c-sdhci.1",
1202 .parent = &clk_dout_mmc1.clk,
1203 .enable = exynos4_clksrc_mask_fsys_ctrl,
1204 .ctrlbit = (1 << 4),
1205 },
1206 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1207};
1208
1209static struct clksrc_clk clk_sclk_mmc2 = {
1210 .clk = {
1211 .name = "sclk_mmc",
1212 .devname = "s3c-sdhci.2",
1213 .parent = &clk_dout_mmc2.clk,
1214 .enable = exynos4_clksrc_mask_fsys_ctrl,
1215 .ctrlbit = (1 << 8),
1216 },
1217 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1218};
1219
1220static struct clksrc_clk clk_sclk_mmc3 = {
1221 .clk = {
1222 .name = "sclk_mmc",
1223 .devname = "s3c-sdhci.3",
1224 .parent = &clk_dout_mmc3.clk,
1225 .enable = exynos4_clksrc_mask_fsys_ctrl,
1226 .ctrlbit = (1 << 12),
1227 },
1228 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1229};
1230
1231static struct clksrc_clk clk_sclk_spi0 = {
1232 .clk = {
1233 .name = "sclk_spi",
1234 .devname = "s3c64xx-spi.0",
1235 .enable = exynos4_clksrc_mask_peril1_ctrl,
1236 .ctrlbit = (1 << 16),
1237 },
1238 .sources = &clkset_group,
1239 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1240 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1241};
1242
1243static struct clksrc_clk clk_sclk_spi1 = {
1244 .clk = {
1245 .name = "sclk_spi",
1246 .devname = "s3c64xx-spi.1",
1247 .enable = exynos4_clksrc_mask_peril1_ctrl,
1248 .ctrlbit = (1 << 20),
1249 },
1250 .sources = &clkset_group,
1251 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1252 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1253};
1254
1255static struct clksrc_clk clk_sclk_spi2 = {
1256 .clk = {
1257 .name = "sclk_spi",
1258 .devname = "s3c64xx-spi.2",
1259 .enable = exynos4_clksrc_mask_peril1_ctrl,
1260 .ctrlbit = (1 << 24),
1261 },
1262 .sources = &clkset_group,
1263 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1264 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1265};
1266
1241/* Clock initialization code */ 1267/* Clock initialization code */
1242static struct clksrc_clk *sysclks[] = { 1268static struct clksrc_clk *sysclks[] = {
1243 &clk_mout_apll, 1269 &clk_mout_apll,
@@ -1272,6 +1298,42 @@ static struct clksrc_clk *sysclks[] = {
1272 &clk_mout_mfc1, 1298 &clk_mout_mfc1,
1273}; 1299};
1274 1300
1301static struct clk *clk_cdev[] = {
1302 &clk_pdma0,
1303 &clk_pdma1,
1304};
1305
1306static struct clksrc_clk *clksrc_cdev[] = {
1307 &clk_sclk_uart0,
1308 &clk_sclk_uart1,
1309 &clk_sclk_uart2,
1310 &clk_sclk_uart3,
1311 &clk_sclk_mmc0,
1312 &clk_sclk_mmc1,
1313 &clk_sclk_mmc2,
1314 &clk_sclk_mmc3,
1315 &clk_sclk_spi0,
1316 &clk_sclk_spi1,
1317 &clk_sclk_spi2,
1318
1319};
1320
1321static struct clk_lookup exynos4_clk_lookup[] = {
1322 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1323 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1324 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1325 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1326 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1327 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1328 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1329 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1330 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1331 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1332 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
1333 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
1334 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
1335};
1336
1275static int xtal_rate; 1337static int xtal_rate;
1276 1338
1277static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) 1339static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1479,11 +1541,19 @@ void __init exynos4_register_clocks(void)
1479 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) 1541 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1480 s3c_register_clksrc(sclk_tv[ptr], 1); 1542 s3c_register_clksrc(sclk_tv[ptr], 1);
1481 1543
1544 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1545 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1546
1482 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1547 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1483 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1548 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1484 1549
1550 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1551 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1552 s3c_disable_clocks(clk_cdev[ptr], 1);
1553
1485 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1554 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1486 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1555 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1556 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1487 1557
1488 register_syscore_ops(&exynos4_clock_syscore_ops); 1558 register_syscore_ops(&exynos4_clock_syscore_ops);
1489 s3c24xx_register_clock(&dummy_apb_pclk); 1559 s3c24xx_register_clock(&dummy_apb_pclk);
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index b6ac6ee658c0..c59e18871006 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -17,8 +17,11 @@
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/sched.h> 18#include <linux/sched.h>
19#include <linux/serial_core.h> 19#include <linux/serial_core.h>
20#include <linux/of.h>
21#include <linux/of_irq.h>
20 22
21#include <asm/proc-fns.h> 23#include <asm/proc-fns.h>
24#include <asm/exception.h>
22#include <asm/hardware/cache-l2x0.h> 25#include <asm/hardware/cache-l2x0.h>
23#include <asm/hardware/gic.h> 26#include <asm/hardware/gic.h>
24#include <asm/mach/map.h> 27#include <asm/mach/map.h>
@@ -43,8 +46,6 @@
43 46
44#include "common.h" 47#include "common.h"
45 48
46unsigned int gic_bank_offset __read_mostly;
47
48static const char name_exynos4210[] = "EXYNOS4210"; 49static const char name_exynos4210[] = "EXYNOS4210";
49static const char name_exynos4212[] = "EXYNOS4212"; 50static const char name_exynos4212[] = "EXYNOS4212";
50static const char name_exynos4412[] = "EXYNOS4412"; 51static const char name_exynos4412[] = "EXYNOS4412";
@@ -386,27 +387,26 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
386 } 387 }
387} 388}
388 389
389static void exynos4_gic_irq_fix_base(struct irq_data *d) 390#ifdef CONFIG_OF
390{ 391static const struct of_device_id exynos4_dt_irq_match[] = {
391 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 392 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
392 393 {},
393 gic_data->cpu_base = S5P_VA_GIC_CPU + 394};
394 (gic_bank_offset * smp_processor_id()); 395#endif
395
396 gic_data->dist_base = S5P_VA_GIC_DIST +
397 (gic_bank_offset * smp_processor_id());
398}
399 396
400void __init exynos4_init_irq(void) 397void __init exynos4_init_irq(void)
401{ 398{
402 int irq; 399 int irq;
400 unsigned int gic_bank_offset;
403 401
404 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; 402 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
405 403
406 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); 404 if (!of_have_populated_dt())
407 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; 405 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
408 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; 406#ifdef CONFIG_OF
409 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base; 407 else
408 of_irq_init(exynos4_dt_irq_match);
409#endif
410 410
411 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 411 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
412 412
@@ -474,15 +474,6 @@ int __init exynos_init(void)
474 return device_register(&exynos4_dev); 474 return device_register(&exynos4_dev);
475} 475}
476 476
477static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
478 [0] = {
479 .name = "uclk1",
480 .divisor = 1,
481 .min_baud = 0,
482 .max_baud = 0,
483 },
484};
485
486/* uart registration process */ 477/* uart registration process */
487 478
488void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) 479void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
@@ -490,16 +481,10 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
490 struct s3c2410_uartcfg *tcfg = cfg; 481 struct s3c2410_uartcfg *tcfg = cfg;
491 u32 ucnt; 482 u32 ucnt;
492 483
493 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { 484 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
494 if (!tcfg->clocks) { 485 tcfg->has_fracval = 1;
495 tcfg->has_fracval = 1;
496 tcfg->clocks = exynos4_serial_clocks;
497 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
498 }
499 tcfg->flags |= NO_NEED_CHECK_CLKSRC;
500 }
501 486
502 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); 487 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
503} 488}
504 489
505static DEFINE_SPINLOCK(eint_lock); 490static DEFINE_SPINLOCK(eint_lock);
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
new file mode 100644
index 000000000000..b8e75300c77d
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-ohci.c
@@ -0,0 +1,52 @@
1/* linux/arch/arm/mach-exynos/dev-ohci.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS - OHCI support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
15
16#include <mach/irqs.h>
17#include <mach/map.h>
18#include <mach/ohci.h>
19
20#include <plat/devs.h>
21#include <plat/usb-phy.h>
22
23static struct resource exynos4_ohci_resource[] = {
24 [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
25 [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
26};
27
28static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
29
30struct platform_device exynos4_device_ohci = {
31 .name = "exynos-ohci",
32 .id = -1,
33 .num_resources = ARRAY_SIZE(exynos4_ohci_resource),
34 .resource = exynos4_ohci_resource,
35 .dev = {
36 .dma_mask = &exynos4_ohci_dma_mask,
37 .coherent_dma_mask = DMA_BIT_MASK(32),
38 }
39};
40
41void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
42{
43 struct exynos4_ohci_platdata *npd;
44
45 npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
46 &exynos4_device_ohci);
47
48 if (!npd->phy_init)
49 npd->phy_init = s5p_usb_phy_init;
50 if (!npd->phy_exit)
51 npd->phy_exit = s5p_usb_phy_exit;
52}
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 9667c61e64fb..b10fcd270f07 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -24,6 +24,7 @@
24#include <linux/dma-mapping.h> 24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h> 25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h> 26#include <linux/amba/pl330.h>
27#include <linux/of.h>
27 28
28#include <asm/irq.h> 29#include <asm/irq.h>
29#include <plat/devs.h> 30#include <plat/devs.h>
@@ -35,95 +36,42 @@
35 36
36static u64 dma_dmamask = DMA_BIT_MASK(32); 37static u64 dma_dmamask = DMA_BIT_MASK(32);
37 38
38struct dma_pl330_peri pdma0_peri[28] = { 39u8 pdma0_peri[] = {
39 { 40 DMACH_PCM0_RX,
40 .peri_id = (u8)DMACH_PCM0_RX, 41 DMACH_PCM0_TX,
41 .rqtype = DEVTOMEM, 42 DMACH_PCM2_RX,
42 }, { 43 DMACH_PCM2_TX,
43 .peri_id = (u8)DMACH_PCM0_TX, 44 DMACH_MSM_REQ0,
44 .rqtype = MEMTODEV, 45 DMACH_MSM_REQ2,
45 }, { 46 DMACH_SPI0_RX,
46 .peri_id = (u8)DMACH_PCM2_RX, 47 DMACH_SPI0_TX,
47 .rqtype = DEVTOMEM, 48 DMACH_SPI2_RX,
48 }, { 49 DMACH_SPI2_TX,
49 .peri_id = (u8)DMACH_PCM2_TX, 50 DMACH_I2S0S_TX,
50 .rqtype = MEMTODEV, 51 DMACH_I2S0_RX,
51 }, { 52 DMACH_I2S0_TX,
52 .peri_id = (u8)DMACH_MSM_REQ0, 53 DMACH_I2S2_RX,
53 }, { 54 DMACH_I2S2_TX,
54 .peri_id = (u8)DMACH_MSM_REQ2, 55 DMACH_UART0_RX,
55 }, { 56 DMACH_UART0_TX,
56 .peri_id = (u8)DMACH_SPI0_RX, 57 DMACH_UART2_RX,
57 .rqtype = DEVTOMEM, 58 DMACH_UART2_TX,
58 }, { 59 DMACH_UART4_RX,
59 .peri_id = (u8)DMACH_SPI0_TX, 60 DMACH_UART4_TX,
60 .rqtype = MEMTODEV, 61 DMACH_SLIMBUS0_RX,
61 }, { 62 DMACH_SLIMBUS0_TX,
62 .peri_id = (u8)DMACH_SPI2_RX, 63 DMACH_SLIMBUS2_RX,
63 .rqtype = DEVTOMEM, 64 DMACH_SLIMBUS2_TX,
64 }, { 65 DMACH_SLIMBUS4_RX,
65 .peri_id = (u8)DMACH_SPI2_TX, 66 DMACH_SLIMBUS4_TX,
66 .rqtype = MEMTODEV, 67 DMACH_AC97_MICIN,
67 }, { 68 DMACH_AC97_PCMIN,
68 .peri_id = (u8)DMACH_I2S0S_TX, 69 DMACH_AC97_PCMOUT,
69 .rqtype = MEMTODEV,
70 }, {
71 .peri_id = (u8)DMACH_I2S0_RX,
72 .rqtype = DEVTOMEM,
73 }, {
74 .peri_id = (u8)DMACH_I2S0_TX,
75 .rqtype = MEMTODEV,
76 }, {
77 .peri_id = (u8)DMACH_UART0_RX,
78 .rqtype = DEVTOMEM,
79 }, {
80 .peri_id = (u8)DMACH_UART0_TX,
81 .rqtype = MEMTODEV,
82 }, {
83 .peri_id = (u8)DMACH_UART2_RX,
84 .rqtype = DEVTOMEM,
85 }, {
86 .peri_id = (u8)DMACH_UART2_TX,
87 .rqtype = MEMTODEV,
88 }, {
89 .peri_id = (u8)DMACH_UART4_RX,
90 .rqtype = DEVTOMEM,
91 }, {
92 .peri_id = (u8)DMACH_UART4_TX,
93 .rqtype = MEMTODEV,
94 }, {
95 .peri_id = (u8)DMACH_SLIMBUS0_RX,
96 .rqtype = DEVTOMEM,
97 }, {
98 .peri_id = (u8)DMACH_SLIMBUS0_TX,
99 .rqtype = MEMTODEV,
100 }, {
101 .peri_id = (u8)DMACH_SLIMBUS2_RX,
102 .rqtype = DEVTOMEM,
103 }, {
104 .peri_id = (u8)DMACH_SLIMBUS2_TX,
105 .rqtype = MEMTODEV,
106 }, {
107 .peri_id = (u8)DMACH_SLIMBUS4_RX,
108 .rqtype = DEVTOMEM,
109 }, {
110 .peri_id = (u8)DMACH_SLIMBUS4_TX,
111 .rqtype = MEMTODEV,
112 }, {
113 .peri_id = (u8)DMACH_AC97_MICIN,
114 .rqtype = DEVTOMEM,
115 }, {
116 .peri_id = (u8)DMACH_AC97_PCMIN,
117 .rqtype = DEVTOMEM,
118 }, {
119 .peri_id = (u8)DMACH_AC97_PCMOUT,
120 .rqtype = MEMTODEV,
121 },
122}; 70};
123 71
124struct dma_pl330_platdata exynos4_pdma0_pdata = { 72struct dma_pl330_platdata exynos4_pdma0_pdata = {
125 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 73 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
126 .peri = pdma0_peri, 74 .peri_id = pdma0_peri,
127}; 75};
128 76
129struct amba_device exynos4_device_pdma0 = { 77struct amba_device exynos4_device_pdma0 = {
@@ -142,86 +90,37 @@ struct amba_device exynos4_device_pdma0 = {
142 .periphid = 0x00041330, 90 .periphid = 0x00041330,
143}; 91};
144 92
145struct dma_pl330_peri pdma1_peri[25] = { 93u8 pdma1_peri[] = {
146 { 94 DMACH_PCM0_RX,
147 .peri_id = (u8)DMACH_PCM0_RX, 95 DMACH_PCM0_TX,
148 .rqtype = DEVTOMEM, 96 DMACH_PCM1_RX,
149 }, { 97 DMACH_PCM1_TX,
150 .peri_id = (u8)DMACH_PCM0_TX, 98 DMACH_MSM_REQ1,
151 .rqtype = MEMTODEV, 99 DMACH_MSM_REQ3,
152 }, { 100 DMACH_SPI1_RX,
153 .peri_id = (u8)DMACH_PCM1_RX, 101 DMACH_SPI1_TX,
154 .rqtype = DEVTOMEM, 102 DMACH_I2S0S_TX,
155 }, { 103 DMACH_I2S0_RX,
156 .peri_id = (u8)DMACH_PCM1_TX, 104 DMACH_I2S0_TX,
157 .rqtype = MEMTODEV, 105 DMACH_I2S1_RX,
158 }, { 106 DMACH_I2S1_TX,
159 .peri_id = (u8)DMACH_MSM_REQ1, 107 DMACH_UART0_RX,
160 }, { 108 DMACH_UART0_TX,
161 .peri_id = (u8)DMACH_MSM_REQ3, 109 DMACH_UART1_RX,
162 }, { 110 DMACH_UART1_TX,
163 .peri_id = (u8)DMACH_SPI1_RX, 111 DMACH_UART3_RX,
164 .rqtype = DEVTOMEM, 112 DMACH_UART3_TX,
165 }, { 113 DMACH_SLIMBUS1_RX,
166 .peri_id = (u8)DMACH_SPI1_TX, 114 DMACH_SLIMBUS1_TX,
167 .rqtype = MEMTODEV, 115 DMACH_SLIMBUS3_RX,
168 }, { 116 DMACH_SLIMBUS3_TX,
169 .peri_id = (u8)DMACH_I2S0S_TX, 117 DMACH_SLIMBUS5_RX,
170 .rqtype = MEMTODEV, 118 DMACH_SLIMBUS5_TX,
171 }, {
172 .peri_id = (u8)DMACH_I2S0_RX,
173 .rqtype = DEVTOMEM,
174 }, {
175 .peri_id = (u8)DMACH_I2S0_TX,
176 .rqtype = MEMTODEV,
177 }, {
178 .peri_id = (u8)DMACH_I2S1_RX,
179 .rqtype = DEVTOMEM,
180 }, {
181 .peri_id = (u8)DMACH_I2S1_TX,
182 .rqtype = MEMTODEV,
183 }, {
184 .peri_id = (u8)DMACH_UART0_RX,
185 .rqtype = DEVTOMEM,
186 }, {
187 .peri_id = (u8)DMACH_UART0_TX,
188 .rqtype = MEMTODEV,
189 }, {
190 .peri_id = (u8)DMACH_UART1_RX,
191 .rqtype = DEVTOMEM,
192 }, {
193 .peri_id = (u8)DMACH_UART1_TX,
194 .rqtype = MEMTODEV,
195 }, {
196 .peri_id = (u8)DMACH_UART3_RX,
197 .rqtype = DEVTOMEM,
198 }, {
199 .peri_id = (u8)DMACH_UART3_TX,
200 .rqtype = MEMTODEV,
201 }, {
202 .peri_id = (u8)DMACH_SLIMBUS1_RX,
203 .rqtype = DEVTOMEM,
204 }, {
205 .peri_id = (u8)DMACH_SLIMBUS1_TX,
206 .rqtype = MEMTODEV,
207 }, {
208 .peri_id = (u8)DMACH_SLIMBUS3_RX,
209 .rqtype = DEVTOMEM,
210 }, {
211 .peri_id = (u8)DMACH_SLIMBUS3_TX,
212 .rqtype = MEMTODEV,
213 }, {
214 .peri_id = (u8)DMACH_SLIMBUS5_RX,
215 .rqtype = DEVTOMEM,
216 }, {
217 .peri_id = (u8)DMACH_SLIMBUS5_TX,
218 .rqtype = MEMTODEV,
219 },
220}; 119};
221 120
222struct dma_pl330_platdata exynos4_pdma1_pdata = { 121struct dma_pl330_platdata exynos4_pdma1_pdata = {
223 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 122 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
224 .peri = pdma1_peri, 123 .peri_id = pdma1_peri,
225}; 124};
226 125
227struct amba_device exynos4_device_pdma1 = { 126struct amba_device exynos4_device_pdma1 = {
@@ -242,7 +141,15 @@ struct amba_device exynos4_device_pdma1 = {
242 141
243static int __init exynos4_dma_init(void) 142static int __init exynos4_dma_init(void)
244{ 143{
144 if (of_have_populated_dt())
145 return 0;
146
147 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
148 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
245 amba_device_register(&exynos4_device_pdma0, &iomem_resource); 149 amba_device_register(&exynos4_device_pdma0, &iomem_resource);
150
151 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
152 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
246 amba_device_register(&exynos4_device_pdma1, &iomem_resource); 153 amba_device_register(&exynos4_device_pdma1, &iomem_resource);
247 154
248 return 0; 155 return 0;
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index dfd4b7eecb90..f77bce04789a 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -17,13 +17,13 @@
17 17
18/* PPI: Private Peripheral Interrupt */ 18/* PPI: Private Peripheral Interrupt */
19 19
20#define IRQ_PPI(x) S5P_IRQ(x+16) 20#define IRQ_PPI(x) (x+16)
21 21
22#define IRQ_MCT_LOCALTIMER IRQ_PPI(12) 22#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
23 23
24/* SPI: Shared Peripheral Interrupt */ 24/* SPI: Shared Peripheral Interrupt */
25 25
26#define IRQ_SPI(x) S5P_IRQ(x+32) 26#define IRQ_SPI(x) (x+32)
27 27
28#define IRQ_EINT0 IRQ_SPI(16) 28#define IRQ_EINT0 IRQ_SPI(16)
29#define IRQ_EINT1 IRQ_SPI(17) 29#define IRQ_EINT1 IRQ_SPI(17)
@@ -72,6 +72,9 @@
72#define IRQ_IIC5 IRQ_SPI(63) 72#define IRQ_IIC5 IRQ_SPI(63)
73#define IRQ_IIC6 IRQ_SPI(64) 73#define IRQ_IIC6 IRQ_SPI(64)
74#define IRQ_IIC7 IRQ_SPI(65) 74#define IRQ_IIC7 IRQ_SPI(65)
75#define IRQ_SPI0 IRQ_SPI(66)
76#define IRQ_SPI1 IRQ_SPI(67)
77#define IRQ_SPI2 IRQ_SPI(68)
75 78
76#define IRQ_USB_HOST IRQ_SPI(70) 79#define IRQ_USB_HOST IRQ_SPI(70)
77#define IRQ_USB_HSOTG IRQ_SPI(71) 80#define IRQ_USB_HSOTG IRQ_SPI(71)
@@ -163,7 +166,9 @@
163#define IRQ_GPIO2_NR_GROUPS 9 166#define IRQ_GPIO2_NR_GROUPS 9
164#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) 167#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
165 168
169#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
170
166/* Set the default NR_IRQS */ 171/* Set the default NR_IRQS */
167#define NR_IRQS (IRQ_GPIO_END + 64) 172#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
168 173
169#endif /* __ASM_ARCH_IRQS_H */ 174#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index d1829860a0ec..c754a22a2bb3 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -87,6 +87,10 @@
87#define EXYNOS4_PA_SYSMMU_TV 0x12E20000 87#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
88#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 88#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
89#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 89#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
90#define EXYNOS4_PA_SPI0 0x13920000
91#define EXYNOS4_PA_SPI1 0x13930000
92#define EXYNOS4_PA_SPI2 0x13940000
93
90 94
91#define EXYNOS4_PA_GPIO1 0x11400000 95#define EXYNOS4_PA_GPIO1 0x11400000
92#define EXYNOS4_PA_GPIO2 0x11000000 96#define EXYNOS4_PA_GPIO2 0x11000000
@@ -107,6 +111,7 @@
107#define EXYNOS4_PA_SROMC 0x12570000 111#define EXYNOS4_PA_SROMC 0x12570000
108 112
109#define EXYNOS4_PA_EHCI 0x12580000 113#define EXYNOS4_PA_EHCI 0x12580000
114#define EXYNOS4_PA_OHCI 0x12590000
110#define EXYNOS4_PA_HSPHY 0x125B0000 115#define EXYNOS4_PA_HSPHY 0x125B0000
111#define EXYNOS4_PA_MFC 0x13400000 116#define EXYNOS4_PA_MFC 0x13400000
112 117
@@ -148,6 +153,9 @@
148#define S3C_PA_RTC EXYNOS4_PA_RTC 153#define S3C_PA_RTC EXYNOS4_PA_RTC
149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 154#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
150#define S3C_PA_UART EXYNOS4_PA_UART 155#define S3C_PA_UART EXYNOS4_PA_UART
156#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
157#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
158#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
151 159
152#define S5P_PA_EHCI EXYNOS4_PA_EHCI 160#define S5P_PA_EHCI EXYNOS4_PA_EHCI
153#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 161#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/include/mach/ohci.h b/arch/arm/mach-exynos/include/mach/ohci.h
new file mode 100644
index 000000000000..c256c595be5e
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/ohci.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * http://www.samsung.com/
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __MACH_EXYNOS_OHCI_H
12#define __MACH_EXYNOS_OHCI_H
13
14struct exynos4_ohci_platdata {
15 int (*phy_init)(struct platform_device *pdev, int type);
16 int (*phy_exit)(struct platform_device *pdev, int type);
17};
18
19extern void exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd);
20
21#endif /* __MACH_EXYNOS_OHCI_H */
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..576efdf6d091
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2011 Samsung Electronics Co. Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef __ASM_ARCH_SPI_CLKS_H
11#define __ASM_ARCH_SPI_CLKS_H __FILE__
12
13/* Must source from SCLK_SPI */
14#define EXYNOS4_SPI_SRCCLK_SCLK 0
15
16#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
new file mode 100644
index 000000000000..85fa02767d67
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -0,0 +1,85 @@
1/*
2 * Samsung's Exynos4210 flattened device tree enabled machine
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/of_platform.h>
15#include <linux/serial_core.h>
16
17#include <asm/mach/arch.h>
18#include <mach/map.h>
19
20#include <plat/cpu.h>
21#include <plat/regs-serial.h>
22#include <plat/exynos4.h>
23
24/*
25 * The following lookup table is used to override device names when devices
26 * are registered from device tree. This is temporarily added to enable
27 * device tree support addition for the Exynos4 architecture.
28 *
29 * For drivers that require platform data to be provided from the machine
30 * file, a platform data pointer can also be supplied along with the
31 * devices names. Usually, the platform data elements that cannot be parsed
32 * from the device tree by the drivers (example: function pointers) are
33 * supplied. But it should be noted that this is a temporary mechanism and
34 * at some point, the drivers should be capable of parsing all the platform
35 * data from the device tree.
36 */
37static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
38 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0,
39 "exynos4210-uart.0", NULL),
40 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1,
41 "exynos4210-uart.1", NULL),
42 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2,
43 "exynos4210-uart.2", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3,
45 "exynos4210-uart.3", NULL),
46 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
47 "exynos4-sdhci.0", NULL),
48 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
49 "exynos4-sdhci.1", NULL),
50 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
51 "exynos4-sdhci.2", NULL),
52 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
53 "exynos4-sdhci.3", NULL),
54 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
55 "s3c2440-i2c.0", NULL),
56 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
57 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
58 {},
59};
60
61static void __init exynos4210_dt_map_io(void)
62{
63 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
64 s3c24xx_init_clocks(24000000);
65}
66
67static void __init exynos4210_dt_machine_init(void)
68{
69 of_platform_populate(NULL, of_default_bus_match_table,
70 exynos4210_auxdata_lookup, NULL);
71}
72
73static char const *exynos4210_dt_compat[] __initdata = {
74 "samsung,exynos4210",
75 NULL
76};
77
78DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
79 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
80 .init_irq = exynos4_init_irq,
81 .map_io = exynos4210_dt_map_io,
82 .init_machine = exynos4210_dt_machine_init,
83 .timer = &exynos4_timer,
84 .dt_compat = exynos4210_dt_compat,
85MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 635fb97e31ab..b895ec031105 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -249,13 +249,8 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
249 249
250static int nuri_bl_init(struct device *dev) 250static int nuri_bl_init(struct device *dev)
251{ 251{
252 int ret, gpio = EXYNOS4_GPE2(3); 252 return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
253 253 "LCD_LD0_EN");
254 ret = gpio_request(gpio, "LCD_LDO_EN");
255 if (!ret)
256 gpio_direction_output(gpio, 0);
257
258 return ret;
259} 254}
260 255
261static int nuri_bl_notify(struct device *dev, int brightness) 256static int nuri_bl_notify(struct device *dev, int brightness)
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 586eb995aa96..2b11e046d391 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -41,6 +41,7 @@
41#include <plat/fb.h> 41#include <plat/fb.h>
42#include <plat/mfc.h> 42#include <plat/mfc.h>
43 43
44#include <mach/ohci.h>
44#include <mach/map.h> 45#include <mach/map.h>
45 46
46#include "common.h" 47#include "common.h"
@@ -485,6 +486,16 @@ static void __init origen_ehci_init(void)
485 s5p_ehci_set_platdata(pdata); 486 s5p_ehci_set_platdata(pdata);
486} 487}
487 488
489/* USB OHCI */
490static struct exynos4_ohci_platdata origen_ohci_pdata;
491
492static void __init origen_ohci_init(void)
493{
494 struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata;
495
496 exynos4_ohci_set_platdata(pdata);
497}
498
488static struct gpio_keys_button origen_gpio_keys_table[] = { 499static struct gpio_keys_button origen_gpio_keys_table[] = {
489 { 500 {
490 .code = KEY_MENU, 501 .code = KEY_MENU,
@@ -608,6 +619,7 @@ static struct platform_device *origen_devices[] __initdata = {
608 &s5p_device_mfc_l, 619 &s5p_device_mfc_l,
609 &s5p_device_mfc_r, 620 &s5p_device_mfc_r,
610 &s5p_device_mixer, 621 &s5p_device_mixer,
622 &exynos4_device_ohci,
611 &exynos4_device_pd[PD_LCD0], 623 &exynos4_device_pd[PD_LCD0],
612 &exynos4_device_pd[PD_TV], 624 &exynos4_device_pd[PD_TV],
613 &exynos4_device_pd[PD_G3D], 625 &exynos4_device_pd[PD_G3D],
@@ -672,6 +684,7 @@ static void __init origen_machine_init(void)
672 s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata); 684 s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
673 685
674 origen_ehci_init(); 686 origen_ehci_init();
687 origen_ohci_init();
675 clk_xusbxti.rate = 24000000; 688 clk_xusbxti.rate = 24000000;
676 689
677 s5p_tv_setup(); 690 s5p_tv_setup();
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 5b365613b470..b2c5557f50e4 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -42,6 +42,7 @@
42#include <plat/clock.h> 42#include <plat/clock.h>
43 43
44#include <mach/map.h> 44#include <mach/map.h>
45#include <mach/ohci.h>
45 46
46#include "common.h" 47#include "common.h"
47 48
@@ -131,9 +132,7 @@ static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
131 gpio_free(EXYNOS4_GPD0(1)); 132 gpio_free(EXYNOS4_GPD0(1));
132#endif 133#endif
133 /* fire nRESET on power up */ 134 /* fire nRESET on power up */
134 gpio_request(EXYNOS4_GPX0(6), "GPX0"); 135 gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
135
136 gpio_direction_output(EXYNOS4_GPX0(6), 1);
137 mdelay(100); 136 mdelay(100);
138 137
139 gpio_set_value(EXYNOS4_GPX0(6), 0); 138 gpio_set_value(EXYNOS4_GPX0(6), 0);
@@ -247,6 +246,16 @@ static void __init smdkv310_ehci_init(void)
247 s5p_ehci_set_platdata(pdata); 246 s5p_ehci_set_platdata(pdata);
248} 247}
249 248
249/* USB OHCI */
250static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
251
252static void __init smdkv310_ohci_init(void)
253{
254 struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
255
256 exynos4_ohci_set_platdata(pdata);
257}
258
250static struct platform_device *smdkv310_devices[] __initdata = { 259static struct platform_device *smdkv310_devices[] __initdata = {
251 &s3c_device_hsmmc0, 260 &s3c_device_hsmmc0,
252 &s3c_device_hsmmc1, 261 &s3c_device_hsmmc1,
@@ -263,6 +272,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
263 &s5p_device_fimc3, 272 &s5p_device_fimc3,
264 &exynos4_device_ac97, 273 &exynos4_device_ac97,
265 &exynos4_device_i2s0, 274 &exynos4_device_i2s0,
275 &exynos4_device_ohci,
266 &samsung_device_keypad, 276 &samsung_device_keypad,
267 &s5p_device_mfc, 277 &s5p_device_mfc,
268 &s5p_device_mfc_l, 278 &s5p_device_mfc_l,
@@ -365,6 +375,7 @@ static void __init smdkv310_machine_init(void)
365 s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata); 375 s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
366 376
367 smdkv310_ehci_init(); 377 smdkv310_ehci_init();
378 smdkv310_ohci_init();
368 clk_xusbxti.rate = 24000000; 379 clk_xusbxti.rate = 24000000;
369 380
370 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); 381 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 52aea972746a..37ac93e8d6d9 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -610,8 +610,7 @@ static void __init universal_tsp_init(void)
610 610
611 /* TSP_LDO_ON: XMDMADDR_11 */ 611 /* TSP_LDO_ON: XMDMADDR_11 */
612 gpio = EXYNOS4_GPE2(3); 612 gpio = EXYNOS4_GPE2(3);
613 gpio_request(gpio, "TSP_LDO_ON"); 613 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
614 gpio_direction_output(gpio, 1);
615 gpio_export(gpio, 0); 614 gpio_export(gpio, 0);
616 615
617 /* TSP_INT: XMDMADDR_7 */ 616 /* TSP_INT: XMDMADDR_7 */
@@ -671,8 +670,7 @@ static void __init universal_touchkey_init(void)
671 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio); 670 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
672 671
673 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */ 672 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
674 gpio_request(gpio, "3_TOUCH_EN"); 673 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
675 gpio_direction_output(gpio, 1);
676} 674}
677 675
678static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = { 676static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
@@ -1002,9 +1000,7 @@ static void __init universal_map_io(void)
1002void s5p_tv_setup(void) 1000void s5p_tv_setup(void)
1003{ 1001{
1004 /* direct HPD to HDMI chip */ 1002 /* direct HPD to HDMI chip */
1005 gpio_request(EXYNOS4_GPX3(7), "hpd-plug"); 1003 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
1006
1007 gpio_direction_input(EXYNOS4_GPX3(7));
1008 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); 1004 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
1009 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); 1005 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
1010 1006
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c4f792dcad19..a4f61a43c7ba 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -23,6 +23,7 @@
23 23
24#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
25#include <asm/hardware/cache-l2x0.h> 25#include <asm/hardware/cache-l2x0.h>
26#include <asm/smp_scu.h>
26 27
27#include <plat/cpu.h> 28#include <plat/cpu.h>
28#include <plat/pm.h> 29#include <plat/pm.h>
@@ -213,27 +214,6 @@ static int exynos4_pm_add(struct device *dev)
213 return 0; 214 return 0;
214} 215}
215 216
216/* This function copy from linux/arch/arm/kernel/smp_scu.c */
217
218void exynos4_scu_enable(void __iomem *scu_base)
219{
220 u32 scu_ctrl;
221
222 scu_ctrl = __raw_readl(scu_base);
223 /* already enabled? */
224 if (scu_ctrl & 1)
225 return;
226
227 scu_ctrl |= 1;
228 __raw_writel(scu_ctrl, scu_base);
229
230 /*
231 * Ensure that the data accessed by CPU0 before the SCU was
232 * initialised is visible to the other CPUs.
233 */
234 flush_cache_all();
235}
236
237static unsigned long pll_base_rate; 217static unsigned long pll_base_rate;
238 218
239static void exynos4_restore_pll(void) 219static void exynos4_restore_pll(void)
@@ -404,7 +384,7 @@ static void exynos4_pm_resume(void)
404 384
405 exynos4_restore_pll(); 385 exynos4_restore_pll();
406 386
407 exynos4_scu_enable(S5P_VA_SCU); 387 scu_enable(S5P_VA_SCU);
408 388
409#ifdef CONFIG_CACHE_L2X0 389#ifdef CONFIG_CACHE_L2X0
410 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); 390 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
deleted file mode 100644
index 92937b410906..000000000000
--- a/arch/arm/mach-exynos/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-exynos4/setup-sdhci.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14
15/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
16
17char *exynos4_hsmmc_clksrcs[4] = {
18 [0] = NULL,
19 [1] = NULL,
20 [2] = "sclk_mmc", /* mmc_bus */
21 [3] = NULL,
22};
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
new file mode 100644
index 000000000000..833ff40ee0e8
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -0,0 +1,72 @@
1/* linux/arch/arm/mach-exynos4/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x1ff,
20 .rx_lvl_offset = 15,
21 .high_speed = 1,
22 .clk_from_cmu = true,
23 .tx_st_done = 25,
24};
25
26int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
27{
28 s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
30 s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
31 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
32 return 0;
33}
34#endif
35
36#ifdef CONFIG_S3C64XX_DEV_SPI1
37struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
38 .fifo_lvl_mask = 0x7f,
39 .rx_lvl_offset = 15,
40 .high_speed = 1,
41 .clk_from_cmu = true,
42 .tx_st_done = 25,
43};
44
45int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
46{
47 s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
48 s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
49 s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
50 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
51 return 0;
52}
53#endif
54
55#ifdef CONFIG_S3C64XX_DEV_SPI2
56struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
57 .fifo_lvl_mask = 0x7f,
58 .rx_lvl_offset = 15,
59 .high_speed = 1,
60 .clk_from_cmu = true,
61 .tx_st_done = 25,
62};
63
64int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
65{
66 s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
67 s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
68 s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
69 S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
70 return 0;
71}
72#endif
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 39aca045f660..41743d21e8c6 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -19,6 +19,13 @@
19#include <plat/cpu.h> 19#include <plat/cpu.h>
20#include <plat/usb-phy.h> 20#include <plat/usb-phy.h>
21 21
22static atomic_t host_usage;
23
24static int exynos4_usb_host_phy_is_on(void)
25{
26 return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
27}
28
22static int exynos4_usb_phy1_init(struct platform_device *pdev) 29static int exynos4_usb_phy1_init(struct platform_device *pdev)
23{ 30{
24 struct clk *otg_clk; 31 struct clk *otg_clk;
@@ -27,6 +34,8 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
27 u32 rstcon; 34 u32 rstcon;
28 int err; 35 int err;
29 36
37 atomic_inc(&host_usage);
38
30 otg_clk = clk_get(&pdev->dev, "otg"); 39 otg_clk = clk_get(&pdev->dev, "otg");
31 if (IS_ERR(otg_clk)) { 40 if (IS_ERR(otg_clk)) {
32 dev_err(&pdev->dev, "Failed to get otg clock\n"); 41 dev_err(&pdev->dev, "Failed to get otg clock\n");
@@ -39,6 +48,9 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
39 return err; 48 return err;
40 } 49 }
41 50
51 if (exynos4_usb_host_phy_is_on())
52 return 0;
53
42 writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE, 54 writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
43 S5P_USBHOST_PHY_CONTROL); 55 S5P_USBHOST_PHY_CONTROL);
44 56
@@ -95,6 +107,9 @@ static int exynos4_usb_phy1_exit(struct platform_device *pdev)
95 struct clk *otg_clk; 107 struct clk *otg_clk;
96 int err; 108 int err;
97 109
110 if (atomic_dec_return(&host_usage) > 0)
111 return 0;
112
98 otg_clk = clk_get(&pdev->dev, "otg"); 113 otg_clk = clk_get(&pdev->dev, "otg");
99 if (IS_ERR(otg_clk)) { 114 if (IS_ERR(otg_clk)) {
100 dev_err(&pdev->dev, "Failed to get otg clock\n"); 115 dev_err(&pdev->dev, "Failed to get otg clock\n");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 16:06:50 -0500