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-rw-r--r--arch/arm/mach-exynos/dma.c225
1 files changed, 64 insertions, 161 deletions
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 9667c61e64fb..141093d60d0d 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -35,95 +35,42 @@
35 35
36static u64 dma_dmamask = DMA_BIT_MASK(32); 36static u64 dma_dmamask = DMA_BIT_MASK(32);
37 37
38struct dma_pl330_peri pdma0_peri[28] = { 38u8 pdma0_peri[] = {
39 { 39 DMACH_PCM0_RX,
40 .peri_id = (u8)DMACH_PCM0_RX, 40 DMACH_PCM0_TX,
41 .rqtype = DEVTOMEM, 41 DMACH_PCM2_RX,
42 }, { 42 DMACH_PCM2_TX,
43 .peri_id = (u8)DMACH_PCM0_TX, 43 DMACH_MSM_REQ0,
44 .rqtype = MEMTODEV, 44 DMACH_MSM_REQ2,
45 }, { 45 DMACH_SPI0_RX,
46 .peri_id = (u8)DMACH_PCM2_RX, 46 DMACH_SPI0_TX,
47 .rqtype = DEVTOMEM, 47 DMACH_SPI2_RX,
48 }, { 48 DMACH_SPI2_TX,
49 .peri_id = (u8)DMACH_PCM2_TX, 49 DMACH_I2S0S_TX,
50 .rqtype = MEMTODEV, 50 DMACH_I2S0_RX,
51 }, { 51 DMACH_I2S0_TX,
52 .peri_id = (u8)DMACH_MSM_REQ0, 52 DMACH_I2S2_RX,
53 }, { 53 DMACH_I2S2_TX,
54 .peri_id = (u8)DMACH_MSM_REQ2, 54 DMACH_UART0_RX,
55 }, { 55 DMACH_UART0_TX,
56 .peri_id = (u8)DMACH_SPI0_RX, 56 DMACH_UART2_RX,
57 .rqtype = DEVTOMEM, 57 DMACH_UART2_TX,
58 }, { 58 DMACH_UART4_RX,
59 .peri_id = (u8)DMACH_SPI0_TX, 59 DMACH_UART4_TX,
60 .rqtype = MEMTODEV, 60 DMACH_SLIMBUS0_RX,
61 }, { 61 DMACH_SLIMBUS0_TX,
62 .peri_id = (u8)DMACH_SPI2_RX, 62 DMACH_SLIMBUS2_RX,
63 .rqtype = DEVTOMEM, 63 DMACH_SLIMBUS2_TX,
64 }, { 64 DMACH_SLIMBUS4_RX,
65 .peri_id = (u8)DMACH_SPI2_TX, 65 DMACH_SLIMBUS4_TX,
66 .rqtype = MEMTODEV, 66 DMACH_AC97_MICIN,
67 }, { 67 DMACH_AC97_PCMIN,
68 .peri_id = (u8)DMACH_I2S0S_TX, 68 DMACH_AC97_PCMOUT,
69 .rqtype = MEMTODEV,
70 }, {
71 .peri_id = (u8)DMACH_I2S0_RX,
72 .rqtype = DEVTOMEM,
73 }, {
74 .peri_id = (u8)DMACH_I2S0_TX,
75 .rqtype = MEMTODEV,
76 }, {
77 .peri_id = (u8)DMACH_UART0_RX,
78 .rqtype = DEVTOMEM,
79 }, {
80 .peri_id = (u8)DMACH_UART0_TX,
81 .rqtype = MEMTODEV,
82 }, {
83 .peri_id = (u8)DMACH_UART2_RX,
84 .rqtype = DEVTOMEM,
85 }, {
86 .peri_id = (u8)DMACH_UART2_TX,
87 .rqtype = MEMTODEV,
88 }, {
89 .peri_id = (u8)DMACH_UART4_RX,
90 .rqtype = DEVTOMEM,
91 }, {
92 .peri_id = (u8)DMACH_UART4_TX,
93 .rqtype = MEMTODEV,
94 }, {
95 .peri_id = (u8)DMACH_SLIMBUS0_RX,
96 .rqtype = DEVTOMEM,
97 }, {
98 .peri_id = (u8)DMACH_SLIMBUS0_TX,
99 .rqtype = MEMTODEV,
100 }, {
101 .peri_id = (u8)DMACH_SLIMBUS2_RX,
102 .rqtype = DEVTOMEM,
103 }, {
104 .peri_id = (u8)DMACH_SLIMBUS2_TX,
105 .rqtype = MEMTODEV,
106 }, {
107 .peri_id = (u8)DMACH_SLIMBUS4_RX,
108 .rqtype = DEVTOMEM,
109 }, {
110 .peri_id = (u8)DMACH_SLIMBUS4_TX,
111 .rqtype = MEMTODEV,
112 }, {
113 .peri_id = (u8)DMACH_AC97_MICIN,
114 .rqtype = DEVTOMEM,
115 }, {
116 .peri_id = (u8)DMACH_AC97_PCMIN,
117 .rqtype = DEVTOMEM,
118 }, {
119 .peri_id = (u8)DMACH_AC97_PCMOUT,
120 .rqtype = MEMTODEV,
121 },
122}; 69};
123 70
124struct dma_pl330_platdata exynos4_pdma0_pdata = { 71struct dma_pl330_platdata exynos4_pdma0_pdata = {
125 .nr_valid_peri = ARRAY_SIZE(pdma0_peri), 72 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
126 .peri = pdma0_peri, 73 .peri_id = pdma0_peri,
127}; 74};
128 75
129struct amba_device exynos4_device_pdma0 = { 76struct amba_device exynos4_device_pdma0 = {
@@ -142,86 +89,37 @@ struct amba_device exynos4_device_pdma0 = {
142 .periphid = 0x00041330, 89 .periphid = 0x00041330,
143}; 90};
144 91
145struct dma_pl330_peri pdma1_peri[25] = { 92u8 pdma1_peri[] = {
146 { 93 DMACH_PCM0_RX,
147 .peri_id = (u8)DMACH_PCM0_RX, 94 DMACH_PCM0_TX,
148 .rqtype = DEVTOMEM, 95 DMACH_PCM1_RX,
149 }, { 96 DMACH_PCM1_TX,
150 .peri_id = (u8)DMACH_PCM0_TX, 97 DMACH_MSM_REQ1,
151 .rqtype = MEMTODEV, 98 DMACH_MSM_REQ3,
152 }, { 99 DMACH_SPI1_RX,
153 .peri_id = (u8)DMACH_PCM1_RX, 100 DMACH_SPI1_TX,
154 .rqtype = DEVTOMEM, 101 DMACH_I2S0S_TX,
155 }, { 102 DMACH_I2S0_RX,
156 .peri_id = (u8)DMACH_PCM1_TX, 103 DMACH_I2S0_TX,
157 .rqtype = MEMTODEV, 104 DMACH_I2S1_RX,
158 }, { 105 DMACH_I2S1_TX,
159 .peri_id = (u8)DMACH_MSM_REQ1, 106 DMACH_UART0_RX,
160 }, { 107 DMACH_UART0_TX,
161 .peri_id = (u8)DMACH_MSM_REQ3, 108 DMACH_UART1_RX,
162 }, { 109 DMACH_UART1_TX,
163 .peri_id = (u8)DMACH_SPI1_RX, 110 DMACH_UART3_RX,
164 .rqtype = DEVTOMEM, 111 DMACH_UART3_TX,
165 }, { 112 DMACH_SLIMBUS1_RX,
166 .peri_id = (u8)DMACH_SPI1_TX, 113 DMACH_SLIMBUS1_TX,
167 .rqtype = MEMTODEV, 114 DMACH_SLIMBUS3_RX,
168 }, { 115 DMACH_SLIMBUS3_TX,
169 .peri_id = (u8)DMACH_I2S0S_TX, 116 DMACH_SLIMBUS5_RX,
170 .rqtype = MEMTODEV, 117 DMACH_SLIMBUS5_TX,
171 }, {
172 .peri_id = (u8)DMACH_I2S0_RX,
173 .rqtype = DEVTOMEM,
174 }, {
175 .peri_id = (u8)DMACH_I2S0_TX,
176 .rqtype = MEMTODEV,
177 }, {
178 .peri_id = (u8)DMACH_I2S1_RX,
179 .rqtype = DEVTOMEM,
180 }, {
181 .peri_id = (u8)DMACH_I2S1_TX,
182 .rqtype = MEMTODEV,
183 }, {
184 .peri_id = (u8)DMACH_UART0_RX,
185 .rqtype = DEVTOMEM,
186 }, {
187 .peri_id = (u8)DMACH_UART0_TX,
188 .rqtype = MEMTODEV,
189 }, {
190 .peri_id = (u8)DMACH_UART1_RX,
191 .rqtype = DEVTOMEM,
192 }, {
193 .peri_id = (u8)DMACH_UART1_TX,
194 .rqtype = MEMTODEV,
195 }, {
196 .peri_id = (u8)DMACH_UART3_RX,
197 .rqtype = DEVTOMEM,
198 }, {
199 .peri_id = (u8)DMACH_UART3_TX,
200 .rqtype = MEMTODEV,
201 }, {
202 .peri_id = (u8)DMACH_SLIMBUS1_RX,
203 .rqtype = DEVTOMEM,
204 }, {
205 .peri_id = (u8)DMACH_SLIMBUS1_TX,
206 .rqtype = MEMTODEV,
207 }, {
208 .peri_id = (u8)DMACH_SLIMBUS3_RX,
209 .rqtype = DEVTOMEM,
210 }, {
211 .peri_id = (u8)DMACH_SLIMBUS3_TX,
212 .rqtype = MEMTODEV,
213 }, {
214 .peri_id = (u8)DMACH_SLIMBUS5_RX,
215 .rqtype = DEVTOMEM,
216 }, {
217 .peri_id = (u8)DMACH_SLIMBUS5_TX,
218 .rqtype = MEMTODEV,
219 },
220}; 118};
221 119
222struct dma_pl330_platdata exynos4_pdma1_pdata = { 120struct dma_pl330_platdata exynos4_pdma1_pdata = {
223 .nr_valid_peri = ARRAY_SIZE(pdma1_peri), 121 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
224 .peri = pdma1_peri, 122 .peri_id = pdma1_peri,
225}; 123};
226 124
227struct amba_device exynos4_device_pdma1 = { 125struct amba_device exynos4_device_pdma1 = {
@@ -242,7 +140,12 @@ struct amba_device exynos4_device_pdma1 = {
242 140
243static int __init exynos4_dma_init(void) 141static int __init exynos4_dma_init(void)
244{ 142{
143 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
144 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
245 amba_device_register(&exynos4_device_pdma0, &iomem_resource); 145 amba_device_register(&exynos4_device_pdma0, &iomem_resource);
146
147 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
148 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
246 amba_device_register(&exynos4_device_pdma1, &iomem_resource); 149 amba_device_register(&exynos4_device_pdma1, &iomem_resource);
247 150
248 return 0; 151 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-04 22:45:52 -0500