diff options
Diffstat (limited to 'arch/arm/mach-exynos4')
-rw-r--r-- | arch/arm/mach-exynos4/include/mach/regs-clock.h | 22 | ||||
-rw-r--r-- | arch/arm/mach-exynos4/include/mach/regs-pmu.h | 143 |
2 files changed, 154 insertions, 11 deletions
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h index ba8f91c04e19..084c3f05c093 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h | |||
@@ -17,13 +17,13 @@ | |||
17 | 17 | ||
18 | #define S5P_CLKREG(x) (S5P_VA_CMU + (x)) | 18 | #define S5P_CLKREG(x) (S5P_VA_CMU + (x)) |
19 | 19 | ||
20 | #define S5P_INFORM0 S5P_CLKREG(0x800) | ||
21 | |||
22 | #define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) | 20 | #define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) |
23 | #define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) | 21 | #define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) |
22 | #define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800) | ||
24 | 23 | ||
25 | #define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) | 24 | #define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) |
26 | #define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) | 25 | #define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) |
26 | #define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) | ||
27 | 27 | ||
28 | #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) | 28 | #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) |
29 | #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) | 29 | #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) |
@@ -33,18 +33,24 @@ | |||
33 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) | 33 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) |
34 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) | 34 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) |
35 | #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) | 35 | #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) |
36 | #define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) | ||
36 | #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) | 37 | #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) |
37 | #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) | 38 | #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) |
38 | #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) | 39 | #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) |
40 | #define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) | ||
39 | #define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) | 41 | #define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) |
40 | #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) | 42 | #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) |
41 | #define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) | 43 | #define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) |
42 | 44 | ||
43 | #define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) | 45 | #define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) |
44 | #define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) | 46 | #define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) |
47 | #define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) | ||
48 | #define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528) | ||
49 | #define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) | ||
45 | #define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) | 50 | #define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) |
46 | #define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) | 51 | #define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) |
47 | #define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) | 52 | #define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) |
53 | #define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) | ||
48 | #define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) | 54 | #define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) |
49 | #define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) | 55 | #define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) |
50 | #define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) | 56 | #define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) |
@@ -58,25 +64,36 @@ | |||
58 | 64 | ||
59 | #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) | 65 | #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) |
60 | #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) | 66 | #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) |
67 | #define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) | ||
61 | #define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) | 68 | #define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) |
62 | #define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) | 69 | #define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) |
70 | #define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) | ||
63 | #define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) | 71 | #define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) |
64 | #define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) | 72 | #define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) |
65 | #define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) | 73 | #define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) |
66 | 74 | ||
67 | #define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) | 75 | #define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) |
68 | 76 | ||
77 | #define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) | ||
69 | #define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) | 78 | #define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) |
79 | #define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) | ||
80 | #define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) | ||
81 | #define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) | ||
70 | #define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) | 82 | #define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) |
71 | #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) | 83 | #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) |
72 | #define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) | 84 | #define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) |
73 | #define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) | 85 | #define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) |
86 | #define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) | ||
74 | #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) | 87 | #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) |
75 | #define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) | 88 | #define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) |
89 | #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) | ||
76 | 90 | ||
91 | #define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) | ||
77 | #define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) | 92 | #define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) |
78 | #define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) | 93 | #define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) |
94 | #define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504) | ||
79 | #define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) | 95 | #define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) |
96 | #define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) | ||
80 | 97 | ||
81 | #define S5P_APLL_LOCK S5P_CLKREG(0x14000) | 98 | #define S5P_APLL_LOCK S5P_CLKREG(0x14000) |
82 | #define S5P_MPLL_LOCK S5P_CLKREG(0x14004) | 99 | #define S5P_MPLL_LOCK S5P_CLKREG(0x14004) |
@@ -94,6 +111,7 @@ | |||
94 | #define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) | 111 | #define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) |
95 | 112 | ||
96 | #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) | 113 | #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) |
114 | #define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900) | ||
97 | 115 | ||
98 | /* APLL_LOCK */ | 116 | /* APLL_LOCK */ |
99 | #define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ | 117 | #define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ |
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h index 2ddd6175dfa0..84aa17bd4dd8 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h | |||
@@ -15,16 +15,141 @@ | |||
15 | 15 | ||
16 | #include <mach/map.h> | 16 | #include <mach/map.h> |
17 | 17 | ||
18 | #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) | 18 | #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) |
19 | 19 | ||
20 | #define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) | 20 | #define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200) |
21 | #define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) | ||
22 | #define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) | ||
23 | #define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) | ||
24 | #define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) | ||
25 | #define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) | ||
26 | #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) | ||
27 | 21 | ||
28 | #define S5P_INT_LOCAL_PWR_EN 0x7 | 22 | #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) |
23 | |||
24 | #define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) | ||
25 | |||
26 | #define S5P_USE_STANDBY_WFI0 (1 << 16) | ||
27 | #define S5P_USE_STANDBY_WFI1 (1 << 17) | ||
28 | #define S5P_USE_STANDBY_WFE0 (1 << 24) | ||
29 | #define S5P_USE_STANDBY_WFE1 (1 << 25) | ||
30 | #define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24)) | ||
31 | |||
32 | #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) | ||
33 | #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) | ||
34 | #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) | ||
35 | |||
36 | #define S5P_INFORM0 S5P_PMUREG(0x0800) | ||
37 | #define S5P_INFORM1 S5P_PMUREG(0x0804) | ||
38 | #define S5P_INFORM2 S5P_PMUREG(0x0808) | ||
39 | #define S5P_INFORM3 S5P_PMUREG(0x080C) | ||
40 | #define S5P_INFORM4 S5P_PMUREG(0x0810) | ||
41 | #define S5P_INFORM5 S5P_PMUREG(0x0814) | ||
42 | #define S5P_INFORM6 S5P_PMUREG(0x0818) | ||
43 | #define S5P_INFORM7 S5P_PMUREG(0x081C) | ||
44 | |||
45 | #define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000) | ||
46 | #define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004) | ||
47 | #define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008) | ||
48 | #define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010) | ||
49 | #define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014) | ||
50 | #define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018) | ||
51 | #define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080) | ||
52 | #define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0) | ||
53 | #define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4) | ||
54 | #define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100) | ||
55 | #define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104) | ||
56 | #define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C) | ||
57 | #define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120) | ||
58 | #define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124) | ||
59 | #define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128) | ||
60 | #define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C) | ||
61 | #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138) | ||
62 | #define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C) | ||
63 | #define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140) | ||
64 | #define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144) | ||
65 | #define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) | ||
66 | #define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) | ||
67 | #define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) | ||
68 | #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) | ||
69 | #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) | ||
70 | #define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) | ||
71 | #define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) | ||
72 | #define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164) | ||
73 | #define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) | ||
74 | #define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) | ||
75 | #define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) | ||
76 | #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) | ||
77 | #define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) | ||
78 | #define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) | ||
79 | #define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) | ||
80 | #define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184) | ||
81 | #define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) | ||
82 | #define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) | ||
83 | #define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) | ||
84 | #define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) | ||
85 | #define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) | ||
86 | #define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) | ||
87 | #define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) | ||
88 | #define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) | ||
89 | #define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) | ||
90 | #define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) | ||
91 | #define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) | ||
92 | #define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) | ||
93 | #define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) | ||
94 | #define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) | ||
95 | #define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224) | ||
96 | #define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228) | ||
97 | #define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C) | ||
98 | #define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230) | ||
99 | #define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234) | ||
100 | #define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240) | ||
101 | #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260) | ||
102 | #define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280) | ||
103 | #define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284) | ||
104 | #define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0) | ||
105 | #define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300) | ||
106 | #define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340) | ||
107 | #define S5P_CAM_LOWPWR S5P_PMUREG(0x1380) | ||
108 | #define S5P_TV_LOWPWR S5P_PMUREG(0x1384) | ||
109 | #define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) | ||
110 | #define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) | ||
111 | #define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) | ||
112 | #define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) | ||
113 | #define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) | ||
114 | #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) | ||
115 | #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) | ||
116 | |||
117 | #define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) | ||
118 | #define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008) | ||
119 | #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) | ||
120 | #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) | ||
121 | #define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088) | ||
122 | |||
123 | #define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408) | ||
124 | #define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48) | ||
125 | #define S5P_CAM_OPTION S5P_PMUREG(0x3C08) | ||
126 | #define S5P_TV_OPTION S5P_PMUREG(0x3C28) | ||
127 | #define S5P_MFC_OPTION S5P_PMUREG(0x3C48) | ||
128 | #define S5P_G3D_OPTION S5P_PMUREG(0x3C68) | ||
129 | #define S5P_LCD0_OPTION S5P_PMUREG(0x3C88) | ||
130 | #define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8) | ||
131 | #define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8) | ||
132 | #define S5P_GPS_OPTION S5P_PMUREG(0x3CE8) | ||
133 | #define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08) | ||
134 | |||
135 | #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) | ||
136 | #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) | ||
137 | #define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128) | ||
138 | #define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148) | ||
139 | #define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168) | ||
140 | #define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) | ||
141 | #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) | ||
142 | |||
143 | #define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) | ||
144 | #define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) | ||
145 | #define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) | ||
146 | #define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) | ||
147 | #define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) | ||
148 | #define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) | ||
149 | #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) | ||
150 | |||
151 | #define S5P_INT_LOCAL_PWR_EN 0x7 | ||
152 | |||
153 | #define S5P_CHECK_SLEEP 0x00000BAD | ||
29 | 154 | ||
30 | #endif /* __ASM_ARCH_REGS_PMU_H */ | 155 | #endif /* __ASM_ARCH_REGS_PMU_H */ |