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-rw-r--r--arch/arm/mach-exynos4/irq-combiner.c14
-rw-r--r--arch/arm/mach-exynos4/irq-eint.c15
2 files changed, 15 insertions, 14 deletions
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index 31618d91ce15..0c180800c8a7 100644
--- a/arch/arm/mach-exynos4/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data)
54 54
55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
56{ 56{
57 struct combiner_chip_data *chip_data = get_irq_data(irq); 57 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
58 struct irq_chip *chip = get_irq_chip(irq); 58 struct irq_chip *chip = irq_get_chip(irq);
59 unsigned int cascade_irq, combiner_irq; 59 unsigned int cascade_irq, combiner_irq;
60 unsigned long status; 60 unsigned long status;
61 61
@@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
93{ 93{
94 if (combiner_nr >= MAX_COMBINER_NR) 94 if (combiner_nr >= MAX_COMBINER_NR)
95 BUG(); 95 BUG();
96 if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0) 96 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
97 BUG(); 97 BUG();
98 set_irq_chained_handler(irq, combiner_handle_cascade_irq); 98 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
99} 99}
100 100
101void __init combiner_init(unsigned int combiner_nr, void __iomem *base, 101void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
@@ -119,9 +119,9 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
119 119
120 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset 120 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
121 + MAX_IRQ_IN_COMBINER; i++) { 121 + MAX_IRQ_IN_COMBINER; i++) {
122 set_irq_chip(i, &combiner_chip); 122 irq_set_chip(i, &combiner_chip);
123 set_irq_chip_data(i, &combiner_data[combiner_nr]); 123 irq_set_chip_data(i, &combiner_data[combiner_nr]);
124 set_irq_handler(i, handle_level_irq); 124 irq_set_handler(i, handle_level_irq);
125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126 } 126 }
127} 127}
diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
index 4f7ad4a796e4..0441dfc7c924 100644
--- a/arch/arm/mach-exynos4/irq-eint.c
+++ b/arch/arm/mach-exynos4/irq-eint.c
@@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
190 190
191static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 191static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
192{ 192{
193 u32 *irq_data = get_irq_data(irq); 193 u32 *irq_data = irq_get_handler_data(irq);
194 struct irq_chip *chip = get_irq_chip(irq); 194 struct irq_chip *chip = irq_get_chip(irq);
195 195
196 chip->irq_mask(&desc->irq_data); 196 chip->irq_mask(&desc->irq_data);
197 197
@@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void)
208 int irq; 208 int irq;
209 209
210 for (irq = 0 ; irq <= 31 ; irq++) { 210 for (irq = 0 ; irq <= 31 ; irq++) {
211 set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint); 211 irq_set_chip(IRQ_EINT(irq), &exynos4_irq_eint);
212 set_irq_handler(IRQ_EINT(irq), handle_level_irq); 212 irq_set_handler(IRQ_EINT(irq), handle_level_irq);
213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID); 213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
214 } 214 }
215 215
216 set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); 216 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
217 217
218 for (irq = 0 ; irq <= 15 ; irq++) { 218 for (irq = 0 ; irq <= 15 ; irq++) {
219 eint0_15_data[irq] = IRQ_EINT(irq); 219 eint0_15_data[irq] = IRQ_EINT(irq);
220 220
221 set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]); 221 irq_set_handler_data(exynos4_get_irq_nr(irq),
222 set_irq_chained_handler(exynos4_get_irq_nr(irq), 222 &eint0_15_data[irq]);
223 irq_set_chained_handler(exynos4_get_irq_nr(irq),
223 exynos4_irq_eint0_15); 224 exynos4_irq_eint0_15);
224 } 225 }
225 226