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-rw-r--r--arch/arm/mach-exynos4/Kconfig34
-rw-r--r--arch/arm/mach-exynos4/Makefile12
-rw-r--r--arch/arm/mach-exynos4/clock.c238
-rw-r--r--arch/arm/mach-exynos4/cpu.c39
-rw-r--r--arch/arm/mach-exynos4/cpufreq.c569
-rw-r--r--arch/arm/mach-exynos4/dev-audio.c2
-rw-r--r--arch/arm/mach-exynos4/dev-dwmci.c82
-rw-r--r--arch/arm/mach-exynos4/hotplug.c13
-rw-r--r--arch/arm/mach-exynos4/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-exynos4/include/mach/dwmci.h20
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S11
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h196
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h19
-rw-r--r--arch/arm/mach-exynos4/include/mach/pm-core.h10
-rw-r--r--arch/arm/mach-exynos4/include/mach/pmu.h25
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-audss.h18
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h12
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h1
-rw-r--r--arch/arm/mach-exynos4/localtimer.c26
-rw-r--r--arch/arm/mach-exynos4/mach-nuri.c753
-rw-r--r--arch/arm/mach-exynos4/mach-smdkc210.c86
-rw-r--r--arch/arm/mach-exynos4/mach-smdkv310.c19
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c121
-rw-r--r--arch/arm/mach-exynos4/mct.c2
-rw-r--r--arch/arm/mach-exynos4/platsmp.c57
-rw-r--r--arch/arm/mach-exynos4/pm.c273
-rw-r--r--arch/arm/mach-exynos4/pmu.c175
-rw-r--r--arch/arm/mach-exynos4/setup-fimd0.c43
-rw-r--r--arch/arm/mach-exynos4/time.c301
29 files changed, 1907 insertions, 1257 deletions
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 1435fc31c4b2..0c77ab99fa16 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -16,7 +16,8 @@ config CPU_EXYNOS4210
16 Enable EXYNOS4210 CPU support 16 Enable EXYNOS4210 CPU support
17 17
18config EXYNOS4_MCT 18config EXYNOS4_MCT
19 bool "Kernel timer support by MCT" 19 bool
20 default y
20 help 21 help
21 Use MCT (Multi Core Timer) as kernel timers 22 Use MCT (Multi Core Timer) as kernel timers
22 23
@@ -25,6 +26,11 @@ config EXYNOS4_DEV_AHCI
25 help 26 help
26 Compile in platform device definitions for AHCI 27 Compile in platform device definitions for AHCI
27 28
29config EXYNOS4_SETUP_FIMD0
30 bool
31 help
32 Common setup code for FIMD0.
33
28config EXYNOS4_DEV_PD 34config EXYNOS4_DEV_PD
29 bool 35 bool
30 help 36 help
@@ -35,6 +41,11 @@ config EXYNOS4_DEV_SYSMMU
35 help 41 help
36 Common setup code for SYSTEM MMU in EXYNOS4 42 Common setup code for SYSTEM MMU in EXYNOS4
37 43
44config EXYNOS4_DEV_DWMCI
45 bool
46 help
47 Compile in platform device definitions for DWMCI
48
38config EXYNOS4_SETUP_I2C1 49config EXYNOS4_SETUP_I2C1
39 bool 50 bool
40 help 51 help
@@ -103,6 +114,7 @@ menu "EXYNOS4 Machines"
103config MACH_SMDKC210 114config MACH_SMDKC210
104 bool "SMDKC210" 115 bool "SMDKC210"
105 select CPU_EXYNOS4210 116 select CPU_EXYNOS4210
117 select S5P_DEV_FIMD0
106 select S3C_DEV_RTC 118 select S3C_DEV_RTC
107 select S3C_DEV_WDT 119 select S3C_DEV_WDT
108 select S3C_DEV_I2C1 120 select S3C_DEV_I2C1
@@ -110,8 +122,11 @@ config MACH_SMDKC210
110 select S3C_DEV_HSMMC1 122 select S3C_DEV_HSMMC1
111 select S3C_DEV_HSMMC2 123 select S3C_DEV_HSMMC2
112 select S3C_DEV_HSMMC3 124 select S3C_DEV_HSMMC3
125 select SAMSUNG_DEV_PWM
126 select SAMSUNG_DEV_BACKLIGHT
113 select EXYNOS4_DEV_PD 127 select EXYNOS4_DEV_PD
114 select EXYNOS4_DEV_SYSMMU 128 select EXYNOS4_DEV_SYSMMU
129 select EXYNOS4_SETUP_FIMD0
115 select EXYNOS4_SETUP_I2C1 130 select EXYNOS4_SETUP_I2C1
116 select EXYNOS4_SETUP_SDHCI 131 select EXYNOS4_SETUP_SDHCI
117 help 132 help
@@ -120,6 +135,7 @@ config MACH_SMDKC210
120config MACH_SMDKV310 135config MACH_SMDKV310
121 bool "SMDKV310" 136 bool "SMDKV310"
122 select CPU_EXYNOS4210 137 select CPU_EXYNOS4210
138 select S5P_DEV_FIMD0
123 select S3C_DEV_RTC 139 select S3C_DEV_RTC
124 select S3C_DEV_WDT 140 select S3C_DEV_WDT
125 select S3C_DEV_I2C1 141 select S3C_DEV_I2C1
@@ -127,9 +143,13 @@ config MACH_SMDKV310
127 select S3C_DEV_HSMMC1 143 select S3C_DEV_HSMMC1
128 select S3C_DEV_HSMMC2 144 select S3C_DEV_HSMMC2
129 select S3C_DEV_HSMMC3 145 select S3C_DEV_HSMMC3
146 select SAMSUNG_DEV_BACKLIGHT
147 select EXYNOS4_DEV_AHCI
130 select SAMSUNG_DEV_KEYPAD 148 select SAMSUNG_DEV_KEYPAD
131 select EXYNOS4_DEV_PD 149 select EXYNOS4_DEV_PD
150 select SAMSUNG_DEV_PWM
132 select EXYNOS4_DEV_SYSMMU 151 select EXYNOS4_DEV_SYSMMU
152 select EXYNOS4_SETUP_FIMD0
133 select EXYNOS4_SETUP_I2C1 153 select EXYNOS4_SETUP_I2C1
134 select EXYNOS4_SETUP_KEYPAD 154 select EXYNOS4_SETUP_KEYPAD
135 select EXYNOS4_SETUP_SDHCI 155 select EXYNOS4_SETUP_SDHCI
@@ -153,13 +173,22 @@ config MACH_ARMLEX4210
153config MACH_UNIVERSAL_C210 173config MACH_UNIVERSAL_C210
154 bool "Mobile UNIVERSAL_C210 Board" 174 bool "Mobile UNIVERSAL_C210 Board"
155 select CPU_EXYNOS4210 175 select CPU_EXYNOS4210
176 select S5P_GPIO_INT
177 select S5P_DEV_FIMC0
178 select S5P_DEV_FIMC1
179 select S5P_DEV_FIMC2
180 select S5P_DEV_FIMC3
156 select S3C_DEV_HSMMC 181 select S3C_DEV_HSMMC
157 select S3C_DEV_HSMMC2 182 select S3C_DEV_HSMMC2
158 select S3C_DEV_HSMMC3 183 select S3C_DEV_HSMMC3
159 select S3C_DEV_I2C1 184 select S3C_DEV_I2C1
185 select S3C_DEV_I2C3
160 select S3C_DEV_I2C5 186 select S3C_DEV_I2C5
187 select S5P_DEV_MFC
161 select S5P_DEV_ONENAND 188 select S5P_DEV_ONENAND
189 select EXYNOS4_DEV_PD
162 select EXYNOS4_SETUP_I2C1 190 select EXYNOS4_SETUP_I2C1
191 select EXYNOS4_SETUP_I2C3
163 select EXYNOS4_SETUP_I2C5 192 select EXYNOS4_SETUP_I2C5
164 select EXYNOS4_SETUP_SDHCI 193 select EXYNOS4_SETUP_SDHCI
165 help 194 help
@@ -176,13 +205,16 @@ config MACH_NURI
176 select S3C_DEV_I2C1 205 select S3C_DEV_I2C1
177 select S3C_DEV_I2C3 206 select S3C_DEV_I2C3
178 select S3C_DEV_I2C5 207 select S3C_DEV_I2C5
208 select S5P_DEV_MFC
179 select S5P_DEV_USB_EHCI 209 select S5P_DEV_USB_EHCI
210 select EXYNOS4_DEV_PD
180 select EXYNOS4_SETUP_I2C1 211 select EXYNOS4_SETUP_I2C1
181 select EXYNOS4_SETUP_I2C3 212 select EXYNOS4_SETUP_I2C3
182 select EXYNOS4_SETUP_I2C5 213 select EXYNOS4_SETUP_I2C5
183 select EXYNOS4_SETUP_SDHCI 214 select EXYNOS4_SETUP_SDHCI
184 select EXYNOS4_SETUP_USB_PHY 215 select EXYNOS4_SETUP_USB_PHY
185 select SAMSUNG_DEV_PWM 216 select SAMSUNG_DEV_PWM
217 select SAMSUNG_DEV_ADC
186 help 218 help
187 Machine support for Samsung Mobile NURI Board. 219 Machine support for Samsung Mobile NURI Board.
188 220
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ecf3599..b7fe1d7b0b1f 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,19 +13,13 @@ obj- :=
13# Core support for EXYNOS4 system 13# Core support for EXYNOS4 system
14 14
15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o 16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
17obj-$(CONFIG_PM) += pm.o sleep.o 17obj-$(CONFIG_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
19obj-$(CONFIG_CPU_IDLE) += cpuidle.o 18obj-$(CONFIG_CPU_IDLE) += cpuidle.o
20 19
21obj-$(CONFIG_SMP) += platsmp.o headsmp.o 20obj-$(CONFIG_SMP) += platsmp.o headsmp.o
22 21
23ifeq ($(CONFIG_EXYNOS4_MCT),y) 22obj-$(CONFIG_EXYNOS4_MCT) += mct.o
24obj-y += mct.o
25else
26obj-y += time.o
27obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
28endif
29 23
30obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 24obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
31 25
@@ -43,8 +37,10 @@ obj-y += dev-audio.o
43obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 37obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
44obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o 38obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
45obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 39obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
40obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
46 41
47obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 42obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
43obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
48obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o 44obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
49obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o 45obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
50obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o 46obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 871f9d508fde..851dea018578 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -27,24 +27,20 @@
27 27
28static struct clk clk_sclk_hdmi27m = { 28static struct clk clk_sclk_hdmi27m = {
29 .name = "sclk_hdmi27m", 29 .name = "sclk_hdmi27m",
30 .id = -1,
31 .rate = 27000000, 30 .rate = 27000000,
32}; 31};
33 32
34static struct clk clk_sclk_hdmiphy = { 33static struct clk clk_sclk_hdmiphy = {
35 .name = "sclk_hdmiphy", 34 .name = "sclk_hdmiphy",
36 .id = -1,
37}; 35};
38 36
39static struct clk clk_sclk_usbphy0 = { 37static struct clk clk_sclk_usbphy0 = {
40 .name = "sclk_usbphy0", 38 .name = "sclk_usbphy0",
41 .id = -1,
42 .rate = 27000000, 39 .rate = 27000000,
43}; 40};
44 41
45static struct clk clk_sclk_usbphy1 = { 42static struct clk clk_sclk_usbphy1 = {
46 .name = "sclk_usbphy1", 43 .name = "sclk_usbphy1",
47 .id = -1,
48}; 44};
49 45
50static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) 46static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
132static struct clksrc_clk clk_mout_apll = { 128static struct clksrc_clk clk_mout_apll = {
133 .clk = { 129 .clk = {
134 .name = "mout_apll", 130 .name = "mout_apll",
135 .id = -1,
136 }, 131 },
137 .sources = &clk_src_apll, 132 .sources = &clk_src_apll,
138 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 133 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
141static struct clksrc_clk clk_sclk_apll = { 136static struct clksrc_clk clk_sclk_apll = {
142 .clk = { 137 .clk = {
143 .name = "sclk_apll", 138 .name = "sclk_apll",
144 .id = -1,
145 .parent = &clk_mout_apll.clk, 139 .parent = &clk_mout_apll.clk,
146 }, 140 },
147 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 141 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
150static struct clksrc_clk clk_mout_epll = { 144static struct clksrc_clk clk_mout_epll = {
151 .clk = { 145 .clk = {
152 .name = "mout_epll", 146 .name = "mout_epll",
153 .id = -1,
154 }, 147 },
155 .sources = &clk_src_epll, 148 .sources = &clk_src_epll,
156 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, 149 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
159static struct clksrc_clk clk_mout_mpll = { 152static struct clksrc_clk clk_mout_mpll = {
160 .clk = { 153 .clk = {
161 .name = "mout_mpll", 154 .name = "mout_mpll",
162 .id = -1,
163 }, 155 },
164 .sources = &clk_src_mpll, 156 .sources = &clk_src_mpll,
165 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, 157 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
178static struct clksrc_clk clk_moutcore = { 170static struct clksrc_clk clk_moutcore = {
179 .clk = { 171 .clk = {
180 .name = "moutcore", 172 .name = "moutcore",
181 .id = -1,
182 }, 173 },
183 .sources = &clkset_moutcore, 174 .sources = &clkset_moutcore,
184 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, 175 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
187static struct clksrc_clk clk_coreclk = { 178static struct clksrc_clk clk_coreclk = {
188 .clk = { 179 .clk = {
189 .name = "core_clk", 180 .name = "core_clk",
190 .id = -1,
191 .parent = &clk_moutcore.clk, 181 .parent = &clk_moutcore.clk,
192 }, 182 },
193 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, 183 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
196static struct clksrc_clk clk_armclk = { 186static struct clksrc_clk clk_armclk = {
197 .clk = { 187 .clk = {
198 .name = "armclk", 188 .name = "armclk",
199 .id = -1,
200 .parent = &clk_coreclk.clk, 189 .parent = &clk_coreclk.clk,
201 }, 190 },
202}; 191};
@@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
204static struct clksrc_clk clk_aclk_corem0 = { 193static struct clksrc_clk clk_aclk_corem0 = {
205 .clk = { 194 .clk = {
206 .name = "aclk_corem0", 195 .name = "aclk_corem0",
207 .id = -1,
208 .parent = &clk_coreclk.clk, 196 .parent = &clk_coreclk.clk,
209 }, 197 },
210 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 198 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
213static struct clksrc_clk clk_aclk_cores = { 201static struct clksrc_clk clk_aclk_cores = {
214 .clk = { 202 .clk = {
215 .name = "aclk_cores", 203 .name = "aclk_cores",
216 .id = -1,
217 .parent = &clk_coreclk.clk, 204 .parent = &clk_coreclk.clk,
218 }, 205 },
219 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 206 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
222static struct clksrc_clk clk_aclk_corem1 = { 209static struct clksrc_clk clk_aclk_corem1 = {
223 .clk = { 210 .clk = {
224 .name = "aclk_corem1", 211 .name = "aclk_corem1",
225 .id = -1,
226 .parent = &clk_coreclk.clk, 212 .parent = &clk_coreclk.clk,
227 }, 213 },
228 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, 214 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
231static struct clksrc_clk clk_periphclk = { 217static struct clksrc_clk clk_periphclk = {
232 .clk = { 218 .clk = {
233 .name = "periphclk", 219 .name = "periphclk",
234 .id = -1,
235 .parent = &clk_coreclk.clk, 220 .parent = &clk_coreclk.clk,
236 }, 221 },
237 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, 222 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
252static struct clksrc_clk clk_mout_corebus = { 237static struct clksrc_clk clk_mout_corebus = {
253 .clk = { 238 .clk = {
254 .name = "mout_corebus", 239 .name = "mout_corebus",
255 .id = -1,
256 }, 240 },
257 .sources = &clkset_mout_corebus, 241 .sources = &clkset_mout_corebus,
258 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, 242 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
261static struct clksrc_clk clk_sclk_dmc = { 245static struct clksrc_clk clk_sclk_dmc = {
262 .clk = { 246 .clk = {
263 .name = "sclk_dmc", 247 .name = "sclk_dmc",
264 .id = -1,
265 .parent = &clk_mout_corebus.clk, 248 .parent = &clk_mout_corebus.clk,
266 }, 249 },
267 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, 250 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
270static struct clksrc_clk clk_aclk_cored = { 253static struct clksrc_clk clk_aclk_cored = {
271 .clk = { 254 .clk = {
272 .name = "aclk_cored", 255 .name = "aclk_cored",
273 .id = -1,
274 .parent = &clk_sclk_dmc.clk, 256 .parent = &clk_sclk_dmc.clk,
275 }, 257 },
276 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, 258 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
279static struct clksrc_clk clk_aclk_corep = { 261static struct clksrc_clk clk_aclk_corep = {
280 .clk = { 262 .clk = {
281 .name = "aclk_corep", 263 .name = "aclk_corep",
282 .id = -1,
283 .parent = &clk_aclk_cored.clk, 264 .parent = &clk_aclk_cored.clk,
284 }, 265 },
285 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, 266 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
288static struct clksrc_clk clk_aclk_acp = { 269static struct clksrc_clk clk_aclk_acp = {
289 .clk = { 270 .clk = {
290 .name = "aclk_acp", 271 .name = "aclk_acp",
291 .id = -1,
292 .parent = &clk_mout_corebus.clk, 272 .parent = &clk_mout_corebus.clk,
293 }, 273 },
294 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, 274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
297static struct clksrc_clk clk_pclk_acp = { 277static struct clksrc_clk clk_pclk_acp = {
298 .clk = { 278 .clk = {
299 .name = "pclk_acp", 279 .name = "pclk_acp",
300 .id = -1,
301 .parent = &clk_aclk_acp.clk, 280 .parent = &clk_aclk_acp.clk,
302 }, 281 },
303 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, 282 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
318static struct clksrc_clk clk_aclk_200 = { 297static struct clksrc_clk clk_aclk_200 = {
319 .clk = { 298 .clk = {
320 .name = "aclk_200", 299 .name = "aclk_200",
321 .id = -1,
322 }, 300 },
323 .sources = &clkset_aclk, 301 .sources = &clkset_aclk,
324 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, 302 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
328static struct clksrc_clk clk_aclk_100 = { 306static struct clksrc_clk clk_aclk_100 = {
329 .clk = { 307 .clk = {
330 .name = "aclk_100", 308 .name = "aclk_100",
331 .id = -1,
332 }, 309 },
333 .sources = &clkset_aclk, 310 .sources = &clkset_aclk,
334 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, 311 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
338static struct clksrc_clk clk_aclk_160 = { 315static struct clksrc_clk clk_aclk_160 = {
339 .clk = { 316 .clk = {
340 .name = "aclk_160", 317 .name = "aclk_160",
341 .id = -1,
342 }, 318 },
343 .sources = &clkset_aclk, 319 .sources = &clkset_aclk,
344 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, 320 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
348static struct clksrc_clk clk_aclk_133 = { 324static struct clksrc_clk clk_aclk_133 = {
349 .clk = { 325 .clk = {
350 .name = "aclk_133", 326 .name = "aclk_133",
351 .id = -1,
352 }, 327 },
353 .sources = &clkset_aclk, 328 .sources = &clkset_aclk,
354 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, 329 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
368static struct clksrc_clk clk_vpllsrc = { 343static struct clksrc_clk clk_vpllsrc = {
369 .clk = { 344 .clk = {
370 .name = "vpll_src", 345 .name = "vpll_src",
371 .id = -1,
372 .enable = exynos4_clksrc_mask_top_ctrl, 346 .enable = exynos4_clksrc_mask_top_ctrl,
373 .ctrlbit = (1 << 0), 347 .ctrlbit = (1 << 0),
374 }, 348 },
@@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
389static struct clksrc_clk clk_sclk_vpll = { 363static struct clksrc_clk clk_sclk_vpll = {
390 .clk = { 364 .clk = {
391 .name = "sclk_vpll", 365 .name = "sclk_vpll",
392 .id = -1,
393 }, 366 },
394 .sources = &clkset_sclk_vpll, 367 .sources = &clkset_sclk_vpll,
395 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, 368 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = {
398static struct clk init_clocks_off[] = { 371static struct clk init_clocks_off[] = {
399 { 372 {
400 .name = "timers", 373 .name = "timers",
401 .id = -1,
402 .parent = &clk_aclk_100.clk, 374 .parent = &clk_aclk_100.clk,
403 .enable = exynos4_clk_ip_peril_ctrl, 375 .enable = exynos4_clk_ip_peril_ctrl,
404 .ctrlbit = (1<<24), 376 .ctrlbit = (1<<24),
405 }, { 377 }, {
406 .name = "csis", 378 .name = "csis",
407 .id = 0, 379 .devname = "s5p-mipi-csis.0",
408 .enable = exynos4_clk_ip_cam_ctrl, 380 .enable = exynos4_clk_ip_cam_ctrl,
409 .ctrlbit = (1 << 4), 381 .ctrlbit = (1 << 4),
410 }, { 382 }, {
411 .name = "csis", 383 .name = "csis",
412 .id = 1, 384 .devname = "s5p-mipi-csis.1",
413 .enable = exynos4_clk_ip_cam_ctrl, 385 .enable = exynos4_clk_ip_cam_ctrl,
414 .ctrlbit = (1 << 5), 386 .ctrlbit = (1 << 5),
415 }, { 387 }, {
416 .name = "fimc", 388 .name = "fimc",
417 .id = 0, 389 .devname = "exynos4-fimc.0",
418 .enable = exynos4_clk_ip_cam_ctrl, 390 .enable = exynos4_clk_ip_cam_ctrl,
419 .ctrlbit = (1 << 0), 391 .ctrlbit = (1 << 0),
420 }, { 392 }, {
421 .name = "fimc", 393 .name = "fimc",
422 .id = 1, 394 .devname = "exynos4-fimc.1",
423 .enable = exynos4_clk_ip_cam_ctrl, 395 .enable = exynos4_clk_ip_cam_ctrl,
424 .ctrlbit = (1 << 1), 396 .ctrlbit = (1 << 1),
425 }, { 397 }, {
426 .name = "fimc", 398 .name = "fimc",
427 .id = 2, 399 .devname = "exynos4-fimc.2",
428 .enable = exynos4_clk_ip_cam_ctrl, 400 .enable = exynos4_clk_ip_cam_ctrl,
429 .ctrlbit = (1 << 2), 401 .ctrlbit = (1 << 2),
430 }, { 402 }, {
431 .name = "fimc", 403 .name = "fimc",
432 .id = 3, 404 .devname = "exynos4-fimc.3",
433 .enable = exynos4_clk_ip_cam_ctrl, 405 .enable = exynos4_clk_ip_cam_ctrl,
434 .ctrlbit = (1 << 3), 406 .ctrlbit = (1 << 3),
435 }, { 407 }, {
436 .name = "fimd", 408 .name = "fimd",
437 .id = 0, 409 .devname = "exynos4-fb.0",
438 .enable = exynos4_clk_ip_lcd0_ctrl, 410 .enable = exynos4_clk_ip_lcd0_ctrl,
439 .ctrlbit = (1 << 0), 411 .ctrlbit = (1 << 0),
440 }, { 412 }, {
441 .name = "fimd", 413 .name = "fimd",
442 .id = 1, 414 .devname = "exynos4-fb.1",
443 .enable = exynos4_clk_ip_lcd1_ctrl, 415 .enable = exynos4_clk_ip_lcd1_ctrl,
444 .ctrlbit = (1 << 0), 416 .ctrlbit = (1 << 0),
445 }, { 417 }, {
446 .name = "sataphy", 418 .name = "sataphy",
447 .id = -1,
448 .parent = &clk_aclk_133.clk, 419 .parent = &clk_aclk_133.clk,
449 .enable = exynos4_clk_ip_fsys_ctrl, 420 .enable = exynos4_clk_ip_fsys_ctrl,
450 .ctrlbit = (1 << 3), 421 .ctrlbit = (1 << 3),
451 }, { 422 }, {
452 .name = "hsmmc", 423 .name = "hsmmc",
453 .id = 0, 424 .devname = "s3c-sdhci.0",
454 .parent = &clk_aclk_133.clk, 425 .parent = &clk_aclk_133.clk,
455 .enable = exynos4_clk_ip_fsys_ctrl, 426 .enable = exynos4_clk_ip_fsys_ctrl,
456 .ctrlbit = (1 << 5), 427 .ctrlbit = (1 << 5),
457 }, { 428 }, {
458 .name = "hsmmc", 429 .name = "hsmmc",
459 .id = 1, 430 .devname = "s3c-sdhci.1",
460 .parent = &clk_aclk_133.clk, 431 .parent = &clk_aclk_133.clk,
461 .enable = exynos4_clk_ip_fsys_ctrl, 432 .enable = exynos4_clk_ip_fsys_ctrl,
462 .ctrlbit = (1 << 6), 433 .ctrlbit = (1 << 6),
463 }, { 434 }, {
464 .name = "hsmmc", 435 .name = "hsmmc",
465 .id = 2, 436 .devname = "s3c-sdhci.2",
466 .parent = &clk_aclk_133.clk, 437 .parent = &clk_aclk_133.clk,
467 .enable = exynos4_clk_ip_fsys_ctrl, 438 .enable = exynos4_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 7), 439 .ctrlbit = (1 << 7),
469 }, { 440 }, {
470 .name = "hsmmc", 441 .name = "hsmmc",
471 .id = 3, 442 .devname = "s3c-sdhci.3",
472 .parent = &clk_aclk_133.clk, 443 .parent = &clk_aclk_133.clk,
473 .enable = exynos4_clk_ip_fsys_ctrl, 444 .enable = exynos4_clk_ip_fsys_ctrl,
474 .ctrlbit = (1 << 8), 445 .ctrlbit = (1 << 8),
475 }, { 446 }, {
476 .name = "hsmmc", 447 .name = "dwmmc",
477 .id = 4,
478 .parent = &clk_aclk_133.clk, 448 .parent = &clk_aclk_133.clk,
479 .enable = exynos4_clk_ip_fsys_ctrl, 449 .enable = exynos4_clk_ip_fsys_ctrl,
480 .ctrlbit = (1 << 9), 450 .ctrlbit = (1 << 9),
481 }, { 451 }, {
482 .name = "sata", 452 .name = "sata",
483 .id = -1,
484 .parent = &clk_aclk_133.clk, 453 .parent = &clk_aclk_133.clk,
485 .enable = exynos4_clk_ip_fsys_ctrl, 454 .enable = exynos4_clk_ip_fsys_ctrl,
486 .ctrlbit = (1 << 10), 455 .ctrlbit = (1 << 10),
487 }, { 456 }, {
488 .name = "pdma", 457 .name = "pdma",
489 .id = 0, 458 .devname = "s3c-pl330.0",
490 .enable = exynos4_clk_ip_fsys_ctrl, 459 .enable = exynos4_clk_ip_fsys_ctrl,
491 .ctrlbit = (1 << 0), 460 .ctrlbit = (1 << 0),
492 }, { 461 }, {
493 .name = "pdma", 462 .name = "pdma",
494 .id = 1, 463 .devname = "s3c-pl330.1",
495 .enable = exynos4_clk_ip_fsys_ctrl, 464 .enable = exynos4_clk_ip_fsys_ctrl,
496 .ctrlbit = (1 << 1), 465 .ctrlbit = (1 << 1),
497 }, { 466 }, {
498 .name = "adc", 467 .name = "adc",
499 .id = -1,
500 .enable = exynos4_clk_ip_peril_ctrl, 468 .enable = exynos4_clk_ip_peril_ctrl,
501 .ctrlbit = (1 << 15), 469 .ctrlbit = (1 << 15),
502 }, { 470 }, {
503 .name = "keypad", 471 .name = "keypad",
504 .id = -1,
505 .enable = exynos4_clk_ip_perir_ctrl, 472 .enable = exynos4_clk_ip_perir_ctrl,
506 .ctrlbit = (1 << 16), 473 .ctrlbit = (1 << 16),
507 }, { 474 }, {
508 .name = "rtc", 475 .name = "rtc",
509 .id = -1,
510 .enable = exynos4_clk_ip_perir_ctrl, 476 .enable = exynos4_clk_ip_perir_ctrl,
511 .ctrlbit = (1 << 15), 477 .ctrlbit = (1 << 15),
512 }, { 478 }, {
513 .name = "watchdog", 479 .name = "watchdog",
514 .id = -1,
515 .parent = &clk_aclk_100.clk, 480 .parent = &clk_aclk_100.clk,
516 .enable = exynos4_clk_ip_perir_ctrl, 481 .enable = exynos4_clk_ip_perir_ctrl,
517 .ctrlbit = (1 << 14), 482 .ctrlbit = (1 << 14),
518 }, { 483 }, {
519 .name = "usbhost", 484 .name = "usbhost",
520 .id = -1,
521 .enable = exynos4_clk_ip_fsys_ctrl , 485 .enable = exynos4_clk_ip_fsys_ctrl ,
522 .ctrlbit = (1 << 12), 486 .ctrlbit = (1 << 12),
523 }, { 487 }, {
524 .name = "otg", 488 .name = "otg",
525 .id = -1,
526 .enable = exynos4_clk_ip_fsys_ctrl, 489 .enable = exynos4_clk_ip_fsys_ctrl,
527 .ctrlbit = (1 << 13), 490 .ctrlbit = (1 << 13),
528 }, { 491 }, {
529 .name = "spi", 492 .name = "spi",
530 .id = 0, 493 .devname = "s3c64xx-spi.0",
531 .enable = exynos4_clk_ip_peril_ctrl, 494 .enable = exynos4_clk_ip_peril_ctrl,
532 .ctrlbit = (1 << 16), 495 .ctrlbit = (1 << 16),
533 }, { 496 }, {
534 .name = "spi", 497 .name = "spi",
535 .id = 1, 498 .devname = "s3c64xx-spi.1",
536 .enable = exynos4_clk_ip_peril_ctrl, 499 .enable = exynos4_clk_ip_peril_ctrl,
537 .ctrlbit = (1 << 17), 500 .ctrlbit = (1 << 17),
538 }, { 501 }, {
539 .name = "spi", 502 .name = "spi",
540 .id = 2, 503 .devname = "s3c64xx-spi.2",
541 .enable = exynos4_clk_ip_peril_ctrl, 504 .enable = exynos4_clk_ip_peril_ctrl,
542 .ctrlbit = (1 << 18), 505 .ctrlbit = (1 << 18),
543 }, { 506 }, {
544 .name = "iis", 507 .name = "iis",
545 .id = 0, 508 .devname = "samsung-i2s.0",
546 .enable = exynos4_clk_ip_peril_ctrl, 509 .enable = exynos4_clk_ip_peril_ctrl,
547 .ctrlbit = (1 << 19), 510 .ctrlbit = (1 << 19),
548 }, { 511 }, {
549 .name = "iis", 512 .name = "iis",
550 .id = 1, 513 .devname = "samsung-i2s.1",
551 .enable = exynos4_clk_ip_peril_ctrl, 514 .enable = exynos4_clk_ip_peril_ctrl,
552 .ctrlbit = (1 << 20), 515 .ctrlbit = (1 << 20),
553 }, { 516 }, {
554 .name = "iis", 517 .name = "iis",
555 .id = 2, 518 .devname = "samsung-i2s.2",
556 .enable = exynos4_clk_ip_peril_ctrl, 519 .enable = exynos4_clk_ip_peril_ctrl,
557 .ctrlbit = (1 << 21), 520 .ctrlbit = (1 << 21),
558 }, { 521 }, {
@@ -562,125 +525,115 @@ static struct clk init_clocks_off[] = {
562 .ctrlbit = (1 << 27), 525 .ctrlbit = (1 << 27),
563 }, { 526 }, {
564 .name = "fimg2d", 527 .name = "fimg2d",
565 .id = -1,
566 .enable = exynos4_clk_ip_image_ctrl, 528 .enable = exynos4_clk_ip_image_ctrl,
567 .ctrlbit = (1 << 0), 529 .ctrlbit = (1 << 0),
568 }, { 530 }, {
531 .name = "mfc",
532 .devname = "s5p-mfc",
533 .enable = exynos4_clk_ip_mfc_ctrl,
534 .ctrlbit = (1 << 0),
535 }, {
569 .name = "i2c", 536 .name = "i2c",
570 .id = 0, 537 .devname = "s3c2440-i2c.0",
571 .parent = &clk_aclk_100.clk, 538 .parent = &clk_aclk_100.clk,
572 .enable = exynos4_clk_ip_peril_ctrl, 539 .enable = exynos4_clk_ip_peril_ctrl,
573 .ctrlbit = (1 << 6), 540 .ctrlbit = (1 << 6),
574 }, { 541 }, {
575 .name = "i2c", 542 .name = "i2c",
576 .id = 1, 543 .devname = "s3c2440-i2c.1",
577 .parent = &clk_aclk_100.clk, 544 .parent = &clk_aclk_100.clk,
578 .enable = exynos4_clk_ip_peril_ctrl, 545 .enable = exynos4_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 7), 546 .ctrlbit = (1 << 7),
580 }, { 547 }, {
581 .name = "i2c", 548 .name = "i2c",
582 .id = 2, 549 .devname = "s3c2440-i2c.2",
583 .parent = &clk_aclk_100.clk, 550 .parent = &clk_aclk_100.clk,
584 .enable = exynos4_clk_ip_peril_ctrl, 551 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 8), 552 .ctrlbit = (1 << 8),
586 }, { 553 }, {
587 .name = "i2c", 554 .name = "i2c",
588 .id = 3, 555 .devname = "s3c2440-i2c.3",
589 .parent = &clk_aclk_100.clk, 556 .parent = &clk_aclk_100.clk,
590 .enable = exynos4_clk_ip_peril_ctrl, 557 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 9), 558 .ctrlbit = (1 << 9),
592 }, { 559 }, {
593 .name = "i2c", 560 .name = "i2c",
594 .id = 4, 561 .devname = "s3c2440-i2c.4",
595 .parent = &clk_aclk_100.clk, 562 .parent = &clk_aclk_100.clk,
596 .enable = exynos4_clk_ip_peril_ctrl, 563 .enable = exynos4_clk_ip_peril_ctrl,
597 .ctrlbit = (1 << 10), 564 .ctrlbit = (1 << 10),
598 }, { 565 }, {
599 .name = "i2c", 566 .name = "i2c",
600 .id = 5, 567 .devname = "s3c2440-i2c.5",
601 .parent = &clk_aclk_100.clk, 568 .parent = &clk_aclk_100.clk,
602 .enable = exynos4_clk_ip_peril_ctrl, 569 .enable = exynos4_clk_ip_peril_ctrl,
603 .ctrlbit = (1 << 11), 570 .ctrlbit = (1 << 11),
604 }, { 571 }, {
605 .name = "i2c", 572 .name = "i2c",
606 .id = 6, 573 .devname = "s3c2440-i2c.6",
607 .parent = &clk_aclk_100.clk, 574 .parent = &clk_aclk_100.clk,
608 .enable = exynos4_clk_ip_peril_ctrl, 575 .enable = exynos4_clk_ip_peril_ctrl,
609 .ctrlbit = (1 << 12), 576 .ctrlbit = (1 << 12),
610 }, { 577 }, {
611 .name = "i2c", 578 .name = "i2c",
612 .id = 7, 579 .devname = "s3c2440-i2c.7",
613 .parent = &clk_aclk_100.clk, 580 .parent = &clk_aclk_100.clk,
614 .enable = exynos4_clk_ip_peril_ctrl, 581 .enable = exynos4_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 13), 582 .ctrlbit = (1 << 13),
616 }, { 583 }, {
617 .name = "SYSMMU_MDMA", 584 .name = "SYSMMU_MDMA",
618 .id = -1,
619 .enable = exynos4_clk_ip_image_ctrl, 585 .enable = exynos4_clk_ip_image_ctrl,
620 .ctrlbit = (1 << 5), 586 .ctrlbit = (1 << 5),
621 }, { 587 }, {
622 .name = "SYSMMU_FIMC0", 588 .name = "SYSMMU_FIMC0",
623 .id = -1,
624 .enable = exynos4_clk_ip_cam_ctrl, 589 .enable = exynos4_clk_ip_cam_ctrl,
625 .ctrlbit = (1 << 7), 590 .ctrlbit = (1 << 7),
626 }, { 591 }, {
627 .name = "SYSMMU_FIMC1", 592 .name = "SYSMMU_FIMC1",
628 .id = -1,
629 .enable = exynos4_clk_ip_cam_ctrl, 593 .enable = exynos4_clk_ip_cam_ctrl,
630 .ctrlbit = (1 << 8), 594 .ctrlbit = (1 << 8),
631 }, { 595 }, {
632 .name = "SYSMMU_FIMC2", 596 .name = "SYSMMU_FIMC2",
633 .id = -1,
634 .enable = exynos4_clk_ip_cam_ctrl, 597 .enable = exynos4_clk_ip_cam_ctrl,
635 .ctrlbit = (1 << 9), 598 .ctrlbit = (1 << 9),
636 }, { 599 }, {
637 .name = "SYSMMU_FIMC3", 600 .name = "SYSMMU_FIMC3",
638 .id = -1,
639 .enable = exynos4_clk_ip_cam_ctrl, 601 .enable = exynos4_clk_ip_cam_ctrl,
640 .ctrlbit = (1 << 10), 602 .ctrlbit = (1 << 10),
641 }, { 603 }, {
642 .name = "SYSMMU_JPEG", 604 .name = "SYSMMU_JPEG",
643 .id = -1,
644 .enable = exynos4_clk_ip_cam_ctrl, 605 .enable = exynos4_clk_ip_cam_ctrl,
645 .ctrlbit = (1 << 11), 606 .ctrlbit = (1 << 11),
646 }, { 607 }, {
647 .name = "SYSMMU_FIMD0", 608 .name = "SYSMMU_FIMD0",
648 .id = -1,
649 .enable = exynos4_clk_ip_lcd0_ctrl, 609 .enable = exynos4_clk_ip_lcd0_ctrl,
650 .ctrlbit = (1 << 4), 610 .ctrlbit = (1 << 4),
651 }, { 611 }, {
652 .name = "SYSMMU_FIMD1", 612 .name = "SYSMMU_FIMD1",
653 .id = -1,
654 .enable = exynos4_clk_ip_lcd1_ctrl, 613 .enable = exynos4_clk_ip_lcd1_ctrl,
655 .ctrlbit = (1 << 4), 614 .ctrlbit = (1 << 4),
656 }, { 615 }, {
657 .name = "SYSMMU_PCIe", 616 .name = "SYSMMU_PCIe",
658 .id = -1,
659 .enable = exynos4_clk_ip_fsys_ctrl, 617 .enable = exynos4_clk_ip_fsys_ctrl,
660 .ctrlbit = (1 << 18), 618 .ctrlbit = (1 << 18),
661 }, { 619 }, {
662 .name = "SYSMMU_G2D", 620 .name = "SYSMMU_G2D",
663 .id = -1,
664 .enable = exynos4_clk_ip_image_ctrl, 621 .enable = exynos4_clk_ip_image_ctrl,
665 .ctrlbit = (1 << 3), 622 .ctrlbit = (1 << 3),
666 }, { 623 }, {
667 .name = "SYSMMU_ROTATOR", 624 .name = "SYSMMU_ROTATOR",
668 .id = -1,
669 .enable = exynos4_clk_ip_image_ctrl, 625 .enable = exynos4_clk_ip_image_ctrl,
670 .ctrlbit = (1 << 4), 626 .ctrlbit = (1 << 4),
671 }, { 627 }, {
672 .name = "SYSMMU_TV", 628 .name = "SYSMMU_TV",
673 .id = -1,
674 .enable = exynos4_clk_ip_tv_ctrl, 629 .enable = exynos4_clk_ip_tv_ctrl,
675 .ctrlbit = (1 << 4), 630 .ctrlbit = (1 << 4),
676 }, { 631 }, {
677 .name = "SYSMMU_MFC_L", 632 .name = "SYSMMU_MFC_L",
678 .id = -1,
679 .enable = exynos4_clk_ip_mfc_ctrl, 633 .enable = exynos4_clk_ip_mfc_ctrl,
680 .ctrlbit = (1 << 1), 634 .ctrlbit = (1 << 1),
681 }, { 635 }, {
682 .name = "SYSMMU_MFC_R", 636 .name = "SYSMMU_MFC_R",
683 .id = -1,
684 .enable = exynos4_clk_ip_mfc_ctrl, 637 .enable = exynos4_clk_ip_mfc_ctrl,
685 .ctrlbit = (1 << 2), 638 .ctrlbit = (1 << 2),
686 } 639 }
@@ -689,32 +642,32 @@ static struct clk init_clocks_off[] = {
689static struct clk init_clocks[] = { 642static struct clk init_clocks[] = {
690 { 643 {
691 .name = "uart", 644 .name = "uart",
692 .id = 0, 645 .devname = "s5pv210-uart.0",
693 .enable = exynos4_clk_ip_peril_ctrl, 646 .enable = exynos4_clk_ip_peril_ctrl,
694 .ctrlbit = (1 << 0), 647 .ctrlbit = (1 << 0),
695 }, { 648 }, {
696 .name = "uart", 649 .name = "uart",
697 .id = 1, 650 .devname = "s5pv210-uart.1",
698 .enable = exynos4_clk_ip_peril_ctrl, 651 .enable = exynos4_clk_ip_peril_ctrl,
699 .ctrlbit = (1 << 1), 652 .ctrlbit = (1 << 1),
700 }, { 653 }, {
701 .name = "uart", 654 .name = "uart",
702 .id = 2, 655 .devname = "s5pv210-uart.2",
703 .enable = exynos4_clk_ip_peril_ctrl, 656 .enable = exynos4_clk_ip_peril_ctrl,
704 .ctrlbit = (1 << 2), 657 .ctrlbit = (1 << 2),
705 }, { 658 }, {
706 .name = "uart", 659 .name = "uart",
707 .id = 3, 660 .devname = "s5pv210-uart.3",
708 .enable = exynos4_clk_ip_peril_ctrl, 661 .enable = exynos4_clk_ip_peril_ctrl,
709 .ctrlbit = (1 << 3), 662 .ctrlbit = (1 << 3),
710 }, { 663 }, {
711 .name = "uart", 664 .name = "uart",
712 .id = 4, 665 .devname = "s5pv210-uart.4",
713 .enable = exynos4_clk_ip_peril_ctrl, 666 .enable = exynos4_clk_ip_peril_ctrl,
714 .ctrlbit = (1 << 4), 667 .ctrlbit = (1 << 4),
715 }, { 668 }, {
716 .name = "uart", 669 .name = "uart",
717 .id = 5, 670 .devname = "s5pv210-uart.5",
718 .enable = exynos4_clk_ip_peril_ctrl, 671 .enable = exynos4_clk_ip_peril_ctrl,
719 .ctrlbit = (1 << 5), 672 .ctrlbit = (1 << 5),
720 } 673 }
@@ -750,7 +703,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
750static struct clksrc_clk clk_mout_g2d0 = { 703static struct clksrc_clk clk_mout_g2d0 = {
751 .clk = { 704 .clk = {
752 .name = "mout_g2d0", 705 .name = "mout_g2d0",
753 .id = -1,
754 }, 706 },
755 .sources = &clkset_mout_g2d0, 707 .sources = &clkset_mout_g2d0,
756 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, 708 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@@ -769,7 +721,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
769static struct clksrc_clk clk_mout_g2d1 = { 721static struct clksrc_clk clk_mout_g2d1 = {
770 .clk = { 722 .clk = {
771 .name = "mout_g2d1", 723 .name = "mout_g2d1",
772 .id = -1,
773 }, 724 },
774 .sources = &clkset_mout_g2d1, 725 .sources = &clkset_mout_g2d1,
775 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, 726 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@@ -785,10 +736,55 @@ static struct clksrc_sources clkset_mout_g2d = {
785 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), 736 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
786}; 737};
787 738
739static struct clk *clkset_mout_mfc0_list[] = {
740 [0] = &clk_mout_mpll.clk,
741 [1] = &clk_sclk_apll.clk,
742};
743
744static struct clksrc_sources clkset_mout_mfc0 = {
745 .sources = clkset_mout_mfc0_list,
746 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
747};
748
749static struct clksrc_clk clk_mout_mfc0 = {
750 .clk = {
751 .name = "mout_mfc0",
752 },
753 .sources = &clkset_mout_mfc0,
754 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
755};
756
757static struct clk *clkset_mout_mfc1_list[] = {
758 [0] = &clk_mout_epll.clk,
759 [1] = &clk_sclk_vpll.clk,
760};
761
762static struct clksrc_sources clkset_mout_mfc1 = {
763 .sources = clkset_mout_mfc1_list,
764 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
765};
766
767static struct clksrc_clk clk_mout_mfc1 = {
768 .clk = {
769 .name = "mout_mfc1",
770 },
771 .sources = &clkset_mout_mfc1,
772 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
773};
774
775static struct clk *clkset_mout_mfc_list[] = {
776 [0] = &clk_mout_mfc0.clk,
777 [1] = &clk_mout_mfc1.clk,
778};
779
780static struct clksrc_sources clkset_mout_mfc = {
781 .sources = clkset_mout_mfc_list,
782 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
783};
784
788static struct clksrc_clk clk_dout_mmc0 = { 785static struct clksrc_clk clk_dout_mmc0 = {
789 .clk = { 786 .clk = {
790 .name = "dout_mmc0", 787 .name = "dout_mmc0",
791 .id = -1,
792 }, 788 },
793 .sources = &clkset_group, 789 .sources = &clkset_group,
794 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, 790 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@@ -798,7 +794,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
798static struct clksrc_clk clk_dout_mmc1 = { 794static struct clksrc_clk clk_dout_mmc1 = {
799 .clk = { 795 .clk = {
800 .name = "dout_mmc1", 796 .name = "dout_mmc1",
801 .id = -1,
802 }, 797 },
803 .sources = &clkset_group, 798 .sources = &clkset_group,
804 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, 799 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@@ -808,7 +803,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
808static struct clksrc_clk clk_dout_mmc2 = { 803static struct clksrc_clk clk_dout_mmc2 = {
809 .clk = { 804 .clk = {
810 .name = "dout_mmc2", 805 .name = "dout_mmc2",
811 .id = -1,
812 }, 806 },
813 .sources = &clkset_group, 807 .sources = &clkset_group,
814 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, 808 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@@ -818,7 +812,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
818static struct clksrc_clk clk_dout_mmc3 = { 812static struct clksrc_clk clk_dout_mmc3 = {
819 .clk = { 813 .clk = {
820 .name = "dout_mmc3", 814 .name = "dout_mmc3",
821 .id = -1,
822 }, 815 },
823 .sources = &clkset_group, 816 .sources = &clkset_group,
824 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, 817 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@@ -828,7 +821,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
828static struct clksrc_clk clk_dout_mmc4 = { 821static struct clksrc_clk clk_dout_mmc4 = {
829 .clk = { 822 .clk = {
830 .name = "dout_mmc4", 823 .name = "dout_mmc4",
831 .id = -1,
832 }, 824 },
833 .sources = &clkset_group, 825 .sources = &clkset_group,
834 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, 826 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@@ -839,7 +831,7 @@ static struct clksrc_clk clksrcs[] = {
839 { 831 {
840 .clk = { 832 .clk = {
841 .name = "uclk1", 833 .name = "uclk1",
842 .id = 0, 834 .devname = "s5pv210-uart.0",
843 .enable = exynos4_clksrc_mask_peril0_ctrl, 835 .enable = exynos4_clksrc_mask_peril0_ctrl,
844 .ctrlbit = (1 << 0), 836 .ctrlbit = (1 << 0),
845 }, 837 },
@@ -849,7 +841,7 @@ static struct clksrc_clk clksrcs[] = {
849 }, { 841 }, {
850 .clk = { 842 .clk = {
851 .name = "uclk1", 843 .name = "uclk1",
852 .id = 1, 844 .devname = "s5pv210-uart.1",
853 .enable = exynos4_clksrc_mask_peril0_ctrl, 845 .enable = exynos4_clksrc_mask_peril0_ctrl,
854 .ctrlbit = (1 << 4), 846 .ctrlbit = (1 << 4),
855 }, 847 },
@@ -859,7 +851,7 @@ static struct clksrc_clk clksrcs[] = {
859 }, { 851 }, {
860 .clk = { 852 .clk = {
861 .name = "uclk1", 853 .name = "uclk1",
862 .id = 2, 854 .devname = "s5pv210-uart.2",
863 .enable = exynos4_clksrc_mask_peril0_ctrl, 855 .enable = exynos4_clksrc_mask_peril0_ctrl,
864 .ctrlbit = (1 << 8), 856 .ctrlbit = (1 << 8),
865 }, 857 },
@@ -869,7 +861,7 @@ static struct clksrc_clk clksrcs[] = {
869 }, { 861 }, {
870 .clk = { 862 .clk = {
871 .name = "uclk1", 863 .name = "uclk1",
872 .id = 3, 864 .devname = "s5pv210-uart.3",
873 .enable = exynos4_clksrc_mask_peril0_ctrl, 865 .enable = exynos4_clksrc_mask_peril0_ctrl,
874 .ctrlbit = (1 << 12), 866 .ctrlbit = (1 << 12),
875 }, 867 },
@@ -879,7 +871,6 @@ static struct clksrc_clk clksrcs[] = {
879 }, { 871 }, {
880 .clk = { 872 .clk = {
881 .name = "sclk_pwm", 873 .name = "sclk_pwm",
882 .id = -1,
883 .enable = exynos4_clksrc_mask_peril0_ctrl, 874 .enable = exynos4_clksrc_mask_peril0_ctrl,
884 .ctrlbit = (1 << 24), 875 .ctrlbit = (1 << 24),
885 }, 876 },
@@ -889,7 +880,7 @@ static struct clksrc_clk clksrcs[] = {
889 }, { 880 }, {
890 .clk = { 881 .clk = {
891 .name = "sclk_csis", 882 .name = "sclk_csis",
892 .id = 0, 883 .devname = "s5p-mipi-csis.0",
893 .enable = exynos4_clksrc_mask_cam_ctrl, 884 .enable = exynos4_clksrc_mask_cam_ctrl,
894 .ctrlbit = (1 << 24), 885 .ctrlbit = (1 << 24),
895 }, 886 },
@@ -899,7 +890,7 @@ static struct clksrc_clk clksrcs[] = {
899 }, { 890 }, {
900 .clk = { 891 .clk = {
901 .name = "sclk_csis", 892 .name = "sclk_csis",
902 .id = 1, 893 .devname = "s5p-mipi-csis.1",
903 .enable = exynos4_clksrc_mask_cam_ctrl, 894 .enable = exynos4_clksrc_mask_cam_ctrl,
904 .ctrlbit = (1 << 28), 895 .ctrlbit = (1 << 28),
905 }, 896 },
@@ -909,7 +900,7 @@ static struct clksrc_clk clksrcs[] = {
909 }, { 900 }, {
910 .clk = { 901 .clk = {
911 .name = "sclk_cam", 902 .name = "sclk_cam",
912 .id = 0, 903 .devname = "exynos4-fimc.0",
913 .enable = exynos4_clksrc_mask_cam_ctrl, 904 .enable = exynos4_clksrc_mask_cam_ctrl,
914 .ctrlbit = (1 << 16), 905 .ctrlbit = (1 << 16),
915 }, 906 },
@@ -919,7 +910,7 @@ static struct clksrc_clk clksrcs[] = {
919 }, { 910 }, {
920 .clk = { 911 .clk = {
921 .name = "sclk_cam", 912 .name = "sclk_cam",
922 .id = 1, 913 .devname = "exynos4-fimc.1",
923 .enable = exynos4_clksrc_mask_cam_ctrl, 914 .enable = exynos4_clksrc_mask_cam_ctrl,
924 .ctrlbit = (1 << 20), 915 .ctrlbit = (1 << 20),
925 }, 916 },
@@ -929,7 +920,7 @@ static struct clksrc_clk clksrcs[] = {
929 }, { 920 }, {
930 .clk = { 921 .clk = {
931 .name = "sclk_fimc", 922 .name = "sclk_fimc",
932 .id = 0, 923 .devname = "exynos4-fimc.0",
933 .enable = exynos4_clksrc_mask_cam_ctrl, 924 .enable = exynos4_clksrc_mask_cam_ctrl,
934 .ctrlbit = (1 << 0), 925 .ctrlbit = (1 << 0),
935 }, 926 },
@@ -939,7 +930,7 @@ static struct clksrc_clk clksrcs[] = {
939 }, { 930 }, {
940 .clk = { 931 .clk = {
941 .name = "sclk_fimc", 932 .name = "sclk_fimc",
942 .id = 1, 933 .devname = "exynos4-fimc.1",
943 .enable = exynos4_clksrc_mask_cam_ctrl, 934 .enable = exynos4_clksrc_mask_cam_ctrl,
944 .ctrlbit = (1 << 4), 935 .ctrlbit = (1 << 4),
945 }, 936 },
@@ -949,7 +940,7 @@ static struct clksrc_clk clksrcs[] = {
949 }, { 940 }, {
950 .clk = { 941 .clk = {
951 .name = "sclk_fimc", 942 .name = "sclk_fimc",
952 .id = 2, 943 .devname = "exynos4-fimc.2",
953 .enable = exynos4_clksrc_mask_cam_ctrl, 944 .enable = exynos4_clksrc_mask_cam_ctrl,
954 .ctrlbit = (1 << 8), 945 .ctrlbit = (1 << 8),
955 }, 946 },
@@ -959,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
959 }, { 950 }, {
960 .clk = { 951 .clk = {
961 .name = "sclk_fimc", 952 .name = "sclk_fimc",
962 .id = 3, 953 .devname = "exynos4-fimc.3",
963 .enable = exynos4_clksrc_mask_cam_ctrl, 954 .enable = exynos4_clksrc_mask_cam_ctrl,
964 .ctrlbit = (1 << 12), 955 .ctrlbit = (1 << 12),
965 }, 956 },
@@ -969,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
969 }, { 960 }, {
970 .clk = { 961 .clk = {
971 .name = "sclk_fimd", 962 .name = "sclk_fimd",
972 .id = 0, 963 .devname = "exynos4-fb.0",
973 .enable = exynos4_clksrc_mask_lcd0_ctrl, 964 .enable = exynos4_clksrc_mask_lcd0_ctrl,
974 .ctrlbit = (1 << 0), 965 .ctrlbit = (1 << 0),
975 }, 966 },
@@ -979,7 +970,7 @@ static struct clksrc_clk clksrcs[] = {
979 }, { 970 }, {
980 .clk = { 971 .clk = {
981 .name = "sclk_fimd", 972 .name = "sclk_fimd",
982 .id = 1, 973 .devname = "exynos4-fb.1",
983 .enable = exynos4_clksrc_mask_lcd1_ctrl, 974 .enable = exynos4_clksrc_mask_lcd1_ctrl,
984 .ctrlbit = (1 << 0), 975 .ctrlbit = (1 << 0),
985 }, 976 },
@@ -989,7 +980,6 @@ static struct clksrc_clk clksrcs[] = {
989 }, { 980 }, {
990 .clk = { 981 .clk = {
991 .name = "sclk_sata", 982 .name = "sclk_sata",
992 .id = -1,
993 .enable = exynos4_clksrc_mask_fsys_ctrl, 983 .enable = exynos4_clksrc_mask_fsys_ctrl,
994 .ctrlbit = (1 << 24), 984 .ctrlbit = (1 << 24),
995 }, 985 },
@@ -999,7 +989,7 @@ static struct clksrc_clk clksrcs[] = {
999 }, { 989 }, {
1000 .clk = { 990 .clk = {
1001 .name = "sclk_spi", 991 .name = "sclk_spi",
1002 .id = 0, 992 .devname = "s3c64xx-spi.0",
1003 .enable = exynos4_clksrc_mask_peril1_ctrl, 993 .enable = exynos4_clksrc_mask_peril1_ctrl,
1004 .ctrlbit = (1 << 16), 994 .ctrlbit = (1 << 16),
1005 }, 995 },
@@ -1009,7 +999,7 @@ static struct clksrc_clk clksrcs[] = {
1009 }, { 999 }, {
1010 .clk = { 1000 .clk = {
1011 .name = "sclk_spi", 1001 .name = "sclk_spi",
1012 .id = 1, 1002 .devname = "s3c64xx-spi.1",
1013 .enable = exynos4_clksrc_mask_peril1_ctrl, 1003 .enable = exynos4_clksrc_mask_peril1_ctrl,
1014 .ctrlbit = (1 << 20), 1004 .ctrlbit = (1 << 20),
1015 }, 1005 },
@@ -1019,7 +1009,7 @@ static struct clksrc_clk clksrcs[] = {
1019 }, { 1009 }, {
1020 .clk = { 1010 .clk = {
1021 .name = "sclk_spi", 1011 .name = "sclk_spi",
1022 .id = 2, 1012 .devname = "s3c64xx-spi.2",
1023 .enable = exynos4_clksrc_mask_peril1_ctrl, 1013 .enable = exynos4_clksrc_mask_peril1_ctrl,
1024 .ctrlbit = (1 << 24), 1014 .ctrlbit = (1 << 24),
1025 }, 1015 },
@@ -1029,15 +1019,22 @@ static struct clksrc_clk clksrcs[] = {
1029 }, { 1019 }, {
1030 .clk = { 1020 .clk = {
1031 .name = "sclk_fimg2d", 1021 .name = "sclk_fimg2d",
1032 .id = -1,
1033 }, 1022 },
1034 .sources = &clkset_mout_g2d, 1023 .sources = &clkset_mout_g2d,
1035 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, 1024 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1036 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, 1025 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1037 }, { 1026 }, {
1038 .clk = { 1027 .clk = {
1028 .name = "sclk_mfc",
1029 .devname = "s5p-mfc",
1030 },
1031 .sources = &clkset_mout_mfc,
1032 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1033 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1034 }, {
1035 .clk = {
1039 .name = "sclk_mmc", 1036 .name = "sclk_mmc",
1040 .id = 0, 1037 .devname = "s3c-sdhci.0",
1041 .parent = &clk_dout_mmc0.clk, 1038 .parent = &clk_dout_mmc0.clk,
1042 .enable = exynos4_clksrc_mask_fsys_ctrl, 1039 .enable = exynos4_clksrc_mask_fsys_ctrl,
1043 .ctrlbit = (1 << 0), 1040 .ctrlbit = (1 << 0),
@@ -1046,7 +1043,7 @@ static struct clksrc_clk clksrcs[] = {
1046 }, { 1043 }, {
1047 .clk = { 1044 .clk = {
1048 .name = "sclk_mmc", 1045 .name = "sclk_mmc",
1049 .id = 1, 1046 .devname = "s3c-sdhci.1",
1050 .parent = &clk_dout_mmc1.clk, 1047 .parent = &clk_dout_mmc1.clk,
1051 .enable = exynos4_clksrc_mask_fsys_ctrl, 1048 .enable = exynos4_clksrc_mask_fsys_ctrl,
1052 .ctrlbit = (1 << 4), 1049 .ctrlbit = (1 << 4),
@@ -1055,7 +1052,7 @@ static struct clksrc_clk clksrcs[] = {
1055 }, { 1052 }, {
1056 .clk = { 1053 .clk = {
1057 .name = "sclk_mmc", 1054 .name = "sclk_mmc",
1058 .id = 2, 1055 .devname = "s3c-sdhci.2",
1059 .parent = &clk_dout_mmc2.clk, 1056 .parent = &clk_dout_mmc2.clk,
1060 .enable = exynos4_clksrc_mask_fsys_ctrl, 1057 .enable = exynos4_clksrc_mask_fsys_ctrl,
1061 .ctrlbit = (1 << 8), 1058 .ctrlbit = (1 << 8),
@@ -1064,7 +1061,7 @@ static struct clksrc_clk clksrcs[] = {
1064 }, { 1061 }, {
1065 .clk = { 1062 .clk = {
1066 .name = "sclk_mmc", 1063 .name = "sclk_mmc",
1067 .id = 3, 1064 .devname = "s3c-sdhci.3",
1068 .parent = &clk_dout_mmc3.clk, 1065 .parent = &clk_dout_mmc3.clk,
1069 .enable = exynos4_clksrc_mask_fsys_ctrl, 1066 .enable = exynos4_clksrc_mask_fsys_ctrl,
1070 .ctrlbit = (1 << 12), 1067 .ctrlbit = (1 << 12),
@@ -1072,8 +1069,7 @@ static struct clksrc_clk clksrcs[] = {
1072 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 1069 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1073 }, { 1070 }, {
1074 .clk = { 1071 .clk = {
1075 .name = "sclk_mmc", 1072 .name = "sclk_dwmmc",
1076 .id = 4,
1077 .parent = &clk_dout_mmc4.clk, 1073 .parent = &clk_dout_mmc4.clk,
1078 .enable = exynos4_clksrc_mask_fsys_ctrl, 1074 .enable = exynos4_clksrc_mask_fsys_ctrl,
1079 .ctrlbit = (1 << 16), 1075 .ctrlbit = (1 << 16),
@@ -1112,6 +1108,8 @@ static struct clksrc_clk *sysclks[] = {
1112 &clk_dout_mmc2, 1108 &clk_dout_mmc2,
1113 &clk_dout_mmc3, 1109 &clk_dout_mmc3,
1114 &clk_dout_mmc4, 1110 &clk_dout_mmc4,
1111 &clk_mout_mfc0,
1112 &clk_mout_mfc1,
1115}; 1113};
1116 1114
1117static int xtal_rate; 1115static int xtal_rate;
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index bfd621460abf..2d8a40c9e6e5 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -16,12 +16,16 @@
16 16
17#include <asm/proc-fns.h> 17#include <asm/proc-fns.h>
18#include <asm/hardware/cache-l2x0.h> 18#include <asm/hardware/cache-l2x0.h>
19#include <asm/hardware/gic.h>
19 20
20#include <plat/cpu.h> 21#include <plat/cpu.h>
21#include <plat/clock.h> 22#include <plat/clock.h>
23#include <plat/devs.h>
22#include <plat/exynos4.h> 24#include <plat/exynos4.h>
25#include <plat/adc-core.h>
23#include <plat/sdhci.h> 26#include <plat/sdhci.h>
24#include <plat/devs.h> 27#include <plat/devs.h>
28#include <plat/fb-core.h>
25#include <plat/fimc-core.h> 29#include <plat/fimc-core.h>
26#include <plat/iic-core.h> 30#include <plat/iic-core.h>
27 31
@@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = {
103 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), 107 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
104 .length = SZ_4K, 108 .length = SZ_4K,
105 .type = MT_DEVICE, 109 .type = MT_DEVICE,
106 } 110 }, {
111 .virtual = (unsigned long)S5P_VA_GIC_CPU,
112 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
113 .length = SZ_64K,
114 .type = MT_DEVICE,
115 }, {
116 .virtual = (unsigned long)S5P_VA_GIC_DIST,
117 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
118 .length = SZ_64K,
119 .type = MT_DEVICE,
120 },
107}; 121};
108 122
109static void exynos4_idle(void) 123static void exynos4_idle(void)
@@ -129,6 +143,8 @@ void __init exynos4_map_io(void)
129 exynos4_default_sdhci2(); 143 exynos4_default_sdhci2();
130 exynos4_default_sdhci3(); 144 exynos4_default_sdhci3();
131 145
146 s3c_adc_setname("samsung-adc-v3");
147
132 s3c_fimc_setname(0, "exynos4-fimc"); 148 s3c_fimc_setname(0, "exynos4-fimc");
133 s3c_fimc_setname(1, "exynos4-fimc"); 149 s3c_fimc_setname(1, "exynos4-fimc");
134 s3c_fimc_setname(2, "exynos4-fimc"); 150 s3c_fimc_setname(2, "exynos4-fimc");
@@ -138,6 +154,8 @@ void __init exynos4_map_io(void)
138 s3c_i2c0_setname("s3c2440-i2c"); 154 s3c_i2c0_setname("s3c2440-i2c");
139 s3c_i2c1_setname("s3c2440-i2c"); 155 s3c_i2c1_setname("s3c2440-i2c");
140 s3c_i2c2_setname("s3c2440-i2c"); 156 s3c_i2c2_setname("s3c2440-i2c");
157
158 s5p_fb_setname(0, "exynos4-fb");
141} 159}
142 160
143void __init exynos4_init_clocks(int xtal) 161void __init exynos4_init_clocks(int xtal)
@@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal)
150 exynos4_setup_clocks(); 168 exynos4_setup_clocks();
151} 169}
152 170
171static void exynos4_gic_irq_eoi(struct irq_data *d)
172{
173 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
174
175 gic_data->cpu_base = S5P_VA_GIC_CPU +
176 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
177}
178
153void __init exynos4_init_irq(void) 179void __init exynos4_init_irq(void)
154{ 180{
155 int irq; 181 int irq;
156 182
157 gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); 183 gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
184 gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
158 185
159 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 186 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
160 187
161 /*
162 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
163 * connected to the interrupt combiner. These irqs
164 * should be initialized to support cascade interrupt.
165 */
166 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
167 continue;
168
169 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), 188 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
170 COMBINER_IRQ(irq, 0)); 189 COMBINER_IRQ(irq, 0));
171 combiner_cascade_irq(irq, IRQ_SPI(irq)); 190 combiner_cascade_irq(irq, IRQ_SPI(irq));
diff --git a/arch/arm/mach-exynos4/cpufreq.c b/arch/arm/mach-exynos4/cpufreq.c
deleted file mode 100644
index a1bd258f0c4d..000000000000
--- a/arch/arm/mach-exynos4/cpufreq.c
+++ /dev/null
@@ -1,569 +0,0 @@
1/* linux/arch/arm/mach-exynos4/cpufreq.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - CPU frequency scaling support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/regulator/consumer.h>
20#include <linux/cpufreq.h>
21
22#include <mach/map.h>
23#include <mach/regs-clock.h>
24#include <mach/regs-mem.h>
25
26#include <plat/clock.h>
27#include <plat/pm.h>
28
29static struct clk *cpu_clk;
30static struct clk *moutcore;
31static struct clk *mout_mpll;
32static struct clk *mout_apll;
33
34static struct regulator *arm_regulator;
35static struct regulator *int_regulator;
36
37static struct cpufreq_freqs freqs;
38static unsigned int memtype;
39
40enum exynos4_memory_type {
41 DDR2 = 4,
42 LPDDR2,
43 DDR3,
44};
45
46enum cpufreq_level_index {
47 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
48};
49
50static struct cpufreq_frequency_table exynos4_freq_table[] = {
51 {L0, 1000*1000},
52 {L1, 800*1000},
53 {L2, 400*1000},
54 {L3, 100*1000},
55 {0, CPUFREQ_TABLE_END},
56};
57
58static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
59 /*
60 * Clock divider value for following
61 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
62 * DIVATB, DIVPCLK_DBG, DIVAPLL }
63 */
64
65 /* ARM L0: 1000MHz */
66 { 0, 3, 7, 3, 3, 0, 1 },
67
68 /* ARM L1: 800MHz */
69 { 0, 3, 7, 3, 3, 0, 1 },
70
71 /* ARM L2: 400MHz */
72 { 0, 1, 3, 1, 3, 0, 1 },
73
74 /* ARM L3: 100MHz */
75 { 0, 0, 1, 0, 3, 1, 1 },
76};
77
78static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
79 /*
80 * Clock divider value for following
81 * { DIVCOPY, DIVHPM }
82 */
83
84 /* ARM L0: 1000MHz */
85 { 3, 0 },
86
87 /* ARM L1: 800MHz */
88 { 3, 0 },
89
90 /* ARM L2: 400MHz */
91 { 3, 0 },
92
93 /* ARM L3: 100MHz */
94 { 3, 0 },
95};
96
97static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
98 /*
99 * Clock divider value for following
100 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
101 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
102 */
103
104 /* DMC L0: 400MHz */
105 { 3, 1, 1, 1, 1, 1, 3, 1 },
106
107 /* DMC L1: 400MHz */
108 { 3, 1, 1, 1, 1, 1, 3, 1 },
109
110 /* DMC L2: 266.7MHz */
111 { 7, 1, 1, 2, 1, 1, 3, 1 },
112
113 /* DMC L3: 200MHz */
114 { 7, 1, 1, 3, 1, 1, 3, 1 },
115};
116
117static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
118 /*
119 * Clock divider value for following
120 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
121 */
122
123 /* ACLK200 L0: 200MHz */
124 { 3, 7, 4, 5, 1 },
125
126 /* ACLK200 L1: 200MHz */
127 { 3, 7, 4, 5, 1 },
128
129 /* ACLK200 L2: 160MHz */
130 { 4, 7, 5, 7, 1 },
131
132 /* ACLK200 L3: 133.3MHz */
133 { 5, 7, 7, 7, 1 },
134};
135
136static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
137 /*
138 * Clock divider value for following
139 * { DIVGDL/R, DIVGPL/R }
140 */
141
142 /* ACLK_GDL/R L0: 200MHz */
143 { 3, 1 },
144
145 /* ACLK_GDL/R L1: 200MHz */
146 { 3, 1 },
147
148 /* ACLK_GDL/R L2: 160MHz */
149 { 4, 1 },
150
151 /* ACLK_GDL/R L3: 133.3MHz */
152 { 5, 1 },
153};
154
155struct cpufreq_voltage_table {
156 unsigned int index; /* any */
157 unsigned int arm_volt; /* uV */
158 unsigned int int_volt;
159};
160
161static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
162 {
163 .index = L0,
164 .arm_volt = 1200000,
165 .int_volt = 1100000,
166 }, {
167 .index = L1,
168 .arm_volt = 1100000,
169 .int_volt = 1100000,
170 }, {
171 .index = L2,
172 .arm_volt = 1000000,
173 .int_volt = 1000000,
174 }, {
175 .index = L3,
176 .arm_volt = 900000,
177 .int_volt = 1000000,
178 },
179};
180
181static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
182 /* APLL FOUT L0: 1000MHz */
183 ((250 << 16) | (6 << 8) | 1),
184
185 /* APLL FOUT L1: 800MHz */
186 ((200 << 16) | (6 << 8) | 1),
187
188 /* APLL FOUT L2 : 400MHz */
189 ((200 << 16) | (6 << 8) | 2),
190
191 /* APLL FOUT L3: 100MHz */
192 ((200 << 16) | (6 << 8) | 4),
193};
194
195int exynos4_verify_speed(struct cpufreq_policy *policy)
196{
197 return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
198}
199
200unsigned int exynos4_getspeed(unsigned int cpu)
201{
202 return clk_get_rate(cpu_clk) / 1000;
203}
204
205void exynos4_set_clkdiv(unsigned int div_index)
206{
207 unsigned int tmp;
208
209 /* Change Divider - CPU0 */
210
211 tmp = __raw_readl(S5P_CLKDIV_CPU);
212
213 tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
214 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
215 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
216 S5P_CLKDIV_CPU0_APLL_MASK);
217
218 tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
219 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
220 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
221 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
222 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
223 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
224 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
225
226 __raw_writel(tmp, S5P_CLKDIV_CPU);
227
228 do {
229 tmp = __raw_readl(S5P_CLKDIV_STATCPU);
230 } while (tmp & 0x1111111);
231
232 /* Change Divider - CPU1 */
233
234 tmp = __raw_readl(S5P_CLKDIV_CPU1);
235
236 tmp &= ~((0x7 << 4) | 0x7);
237
238 tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
239 (clkdiv_cpu1[div_index][1] << 0));
240
241 __raw_writel(tmp, S5P_CLKDIV_CPU1);
242
243 do {
244 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
245 } while (tmp & 0x11);
246
247 /* Change Divider - DMC0 */
248
249 tmp = __raw_readl(S5P_CLKDIV_DMC0);
250
251 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
252 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
253 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
254 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
255
256 tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
257 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
258 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
259 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
260 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
261 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
262 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
263 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
264
265 __raw_writel(tmp, S5P_CLKDIV_DMC0);
266
267 do {
268 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
269 } while (tmp & 0x11111111);
270
271 /* Change Divider - TOP */
272
273 tmp = __raw_readl(S5P_CLKDIV_TOP);
274
275 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
276 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
277 S5P_CLKDIV_TOP_ONENAND_MASK);
278
279 tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
280 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
281 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
282 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
283 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
284
285 __raw_writel(tmp, S5P_CLKDIV_TOP);
286
287 do {
288 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
289 } while (tmp & 0x11111);
290
291 /* Change Divider - LEFTBUS */
292
293 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
294
295 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
296
297 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
298 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
299
300 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
301
302 do {
303 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
304 } while (tmp & 0x11);
305
306 /* Change Divider - RIGHTBUS */
307
308 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
309
310 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
311
312 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
313 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
314
315 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
316
317 do {
318 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
319 } while (tmp & 0x11);
320}
321
322static void exynos4_set_apll(unsigned int index)
323{
324 unsigned int tmp;
325
326 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
327 clk_set_parent(moutcore, mout_mpll);
328
329 do {
330 tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
331 >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
332 tmp &= 0x7;
333 } while (tmp != 0x2);
334
335 /* 2. Set APLL Lock time */
336 __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
337
338 /* 3. Change PLL PMS values */
339 tmp = __raw_readl(S5P_APLL_CON0);
340 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
341 tmp |= exynos4_apll_pms_table[index];
342 __raw_writel(tmp, S5P_APLL_CON0);
343
344 /* 4. wait_lock_time */
345 do {
346 tmp = __raw_readl(S5P_APLL_CON0);
347 } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
348
349 /* 5. MUX_CORE_SEL = APLL */
350 clk_set_parent(moutcore, mout_apll);
351
352 do {
353 tmp = __raw_readl(S5P_CLKMUX_STATCPU);
354 tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
355 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
356}
357
358static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
359{
360 unsigned int tmp;
361
362 if (old_index > new_index) {
363 /* The frequency changing to L0 needs to change apll */
364 if (freqs.new == exynos4_freq_table[L0].frequency) {
365 /* 1. Change the system clock divider values */
366 exynos4_set_clkdiv(new_index);
367
368 /* 2. Change the apll m,p,s value */
369 exynos4_set_apll(new_index);
370 } else {
371 /* 1. Change the system clock divider values */
372 exynos4_set_clkdiv(new_index);
373
374 /* 2. Change just s value in apll m,p,s value */
375 tmp = __raw_readl(S5P_APLL_CON0);
376 tmp &= ~(0x7 << 0);
377 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
378 __raw_writel(tmp, S5P_APLL_CON0);
379 }
380 }
381
382 else if (old_index < new_index) {
383 /* The frequency changing from L0 needs to change apll */
384 if (freqs.old == exynos4_freq_table[L0].frequency) {
385 /* 1. Change the apll m,p,s value */
386 exynos4_set_apll(new_index);
387
388 /* 2. Change the system clock divider values */
389 exynos4_set_clkdiv(new_index);
390 } else {
391 /* 1. Change just s value in apll m,p,s value */
392 tmp = __raw_readl(S5P_APLL_CON0);
393 tmp &= ~(0x7 << 0);
394 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
395 __raw_writel(tmp, S5P_APLL_CON0);
396
397 /* 2. Change the system clock divider values */
398 exynos4_set_clkdiv(new_index);
399 }
400 }
401}
402
403static int exynos4_target(struct cpufreq_policy *policy,
404 unsigned int target_freq,
405 unsigned int relation)
406{
407 unsigned int index, old_index;
408 unsigned int arm_volt, int_volt;
409
410 freqs.old = exynos4_getspeed(policy->cpu);
411
412 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
413 freqs.old, relation, &old_index))
414 return -EINVAL;
415
416 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
417 target_freq, relation, &index))
418 return -EINVAL;
419
420 freqs.new = exynos4_freq_table[index].frequency;
421 freqs.cpu = policy->cpu;
422
423 if (freqs.new == freqs.old)
424 return 0;
425
426 /* get the voltage value */
427 arm_volt = exynos4_volt_table[index].arm_volt;
428 int_volt = exynos4_volt_table[index].int_volt;
429
430 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
431
432 /* control regulator */
433 if (freqs.new > freqs.old) {
434 /* Voltage up */
435 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
436 regulator_set_voltage(int_regulator, int_volt, int_volt);
437 }
438
439 /* Clock Configuration Procedure */
440 exynos4_set_frequency(old_index, index);
441
442 /* control regulator */
443 if (freqs.new < freqs.old) {
444 /* Voltage down */
445 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
446 regulator_set_voltage(int_regulator, int_volt, int_volt);
447 }
448
449 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
450
451 return 0;
452}
453
454#ifdef CONFIG_PM
455static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
456{
457 return 0;
458}
459
460static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
461{
462 return 0;
463}
464#endif
465
466static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
467{
468 policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
469
470 cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
471
472 /* set the transition latency value */
473 policy->cpuinfo.transition_latency = 100000;
474
475 /*
476 * EXYNOS4 multi-core processors has 2 cores
477 * that the frequency cannot be set independently.
478 * Each cpu is bound to the same speed.
479 * So the affected cpu is all of the cpus.
480 */
481 cpumask_setall(policy->cpus);
482
483 return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
484}
485
486static struct cpufreq_driver exynos4_driver = {
487 .flags = CPUFREQ_STICKY,
488 .verify = exynos4_verify_speed,
489 .target = exynos4_target,
490 .get = exynos4_getspeed,
491 .init = exynos4_cpufreq_cpu_init,
492 .name = "exynos4_cpufreq",
493#ifdef CONFIG_PM
494 .suspend = exynos4_cpufreq_suspend,
495 .resume = exynos4_cpufreq_resume,
496#endif
497};
498
499static int __init exynos4_cpufreq_init(void)
500{
501 cpu_clk = clk_get(NULL, "armclk");
502 if (IS_ERR(cpu_clk))
503 return PTR_ERR(cpu_clk);
504
505 moutcore = clk_get(NULL, "moutcore");
506 if (IS_ERR(moutcore))
507 goto out;
508
509 mout_mpll = clk_get(NULL, "mout_mpll");
510 if (IS_ERR(mout_mpll))
511 goto out;
512
513 mout_apll = clk_get(NULL, "mout_apll");
514 if (IS_ERR(mout_apll))
515 goto out;
516
517 arm_regulator = regulator_get(NULL, "vdd_arm");
518 if (IS_ERR(arm_regulator)) {
519 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
520 goto out;
521 }
522
523 int_regulator = regulator_get(NULL, "vdd_int");
524 if (IS_ERR(int_regulator)) {
525 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
526 goto out;
527 }
528
529 /*
530 * Check DRAM type.
531 * Because DVFS level is different according to DRAM type.
532 */
533 memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
534 memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
535 memtype &= S5P_DMC0_MEMTYPE_MASK;
536
537 if ((memtype < DDR2) && (memtype > DDR3)) {
538 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
539 goto out;
540 } else {
541 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
542 }
543
544 return cpufreq_register_driver(&exynos4_driver);
545
546out:
547 if (!IS_ERR(cpu_clk))
548 clk_put(cpu_clk);
549
550 if (!IS_ERR(moutcore))
551 clk_put(moutcore);
552
553 if (!IS_ERR(mout_mpll))
554 clk_put(mout_mpll);
555
556 if (!IS_ERR(mout_apll))
557 clk_put(mout_apll);
558
559 if (!IS_ERR(arm_regulator))
560 regulator_put(arm_regulator);
561
562 if (!IS_ERR(int_regulator))
563 regulator_put(int_regulator);
564
565 printk(KERN_ERR "%s: failed initialization\n", __func__);
566
567 return -EINVAL;
568}
569late_initcall(exynos4_cpufreq_init);
diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index 983069a53239..5a9f9c2e53bf 100644
--- a/arch/arm/mach-exynos4/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -21,6 +21,7 @@
21#include <mach/map.h> 21#include <mach/map.h>
22#include <mach/dma.h> 22#include <mach/dma.h>
23#include <mach/irqs.h> 23#include <mach/irqs.h>
24#include <mach/regs-audss.h>
24 25
25static const char *rclksrc[] = { 26static const char *rclksrc[] = {
26 [0] = "busclk", 27 [0] = "busclk",
@@ -55,6 +56,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
55 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI 56 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
56 | QUIRK_NEED_RSTCLR, 57 | QUIRK_NEED_RSTCLR,
57 .src_clk = rclksrc, 58 .src_clk = rclksrc,
59 .idma_addr = EXYNOS4_AUDSS_INT_MEM,
58 }, 60 },
59 }, 61 },
60}; 62};
diff --git a/arch/arm/mach-exynos4/dev-dwmci.c b/arch/arm/mach-exynos4/dev-dwmci.c
new file mode 100644
index 000000000000..b025db4bf602
--- /dev/null
+++ b/arch/arm/mach-exynos4/dev-dwmci.c
@@ -0,0 +1,82 @@
1/*
2 * linux/arch/arm/mach-exynos4/dev-dwmci.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Platform device for Synopsys DesignWare Mobile Storage IP
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18#include <linux/interrupt.h>
19#include <linux/mmc/dw_mmc.h>
20
21#include <plat/devs.h>
22
23#include <mach/map.h>
24
25static int exynos4_dwmci_get_bus_wd(u32 slot_id)
26{
27 return 4;
28}
29
30static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
31{
32 return 0;
33}
34
35static struct resource exynos4_dwmci_resource[] = {
36 [0] = {
37 .start = EXYNOS4_PA_DWMCI,
38 .end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
39 .flags = IORESOURCE_MEM,
40 },
41 [1] = {
42 .start = IRQ_DWMCI,
43 .end = IRQ_DWMCI,
44 .flags = IORESOURCE_IRQ,
45 }
46};
47
48static struct dw_mci_board exynos4_dwci_pdata = {
49 .num_slots = 1,
50 .quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
51 .bus_hz = 80 * 1000 * 1000,
52 .detect_delay_ms = 200,
53 .init = exynos4_dwmci_init,
54 .get_bus_wd = exynos4_dwmci_get_bus_wd,
55};
56
57static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
58
59struct platform_device exynos4_device_dwmci = {
60 .name = "dw_mmc",
61 .id = -1,
62 .num_resources = ARRAY_SIZE(exynos4_dwmci_resource),
63 .resource = exynos4_dwmci_resource,
64 .dev = {
65 .dma_mask = &exynos4_dwmci_dmamask,
66 .coherent_dma_mask = DMA_BIT_MASK(32),
67 .platform_data = &exynos4_dwci_pdata,
68 },
69};
70
71void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
72{
73 struct dw_mci_board *npd;
74
75 npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
76 &exynos4_device_dwmci);
77
78 if (!npd->init)
79 npd->init = exynos4_dwmci_init;
80 if (!npd->get_bus_wd)
81 npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
82}
diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index 2b5909e2ccd3..7490789784c9 100644
--- a/arch/arm/mach-exynos4/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -13,9 +13,12 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/errno.h> 14#include <linux/errno.h>
15#include <linux/smp.h> 15#include <linux/smp.h>
16#include <linux/io.h>
16 17
17#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
18 19
20#include <mach/regs-pmu.h>
21
19extern volatile int pen_release; 22extern volatile int pen_release;
20 23
21static inline void cpu_enter_lowpower(void) 24static inline void cpu_enter_lowpower(void)
@@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void)
58 61
59static inline void platform_do_lowpower(unsigned int cpu, int *spurious) 62static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
60{ 63{
61 /*
62 * there is no power-control hardware on this platform, so all
63 * we can do is put the core into WFI; this is safe as the calling
64 * code will have already disabled interrupts
65 */
66 for (;;) { 64 for (;;) {
65
66 /* make cpu1 to be turned off at next WFI command */
67 if (cpu == 1)
68 __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
69
67 /* 70 /*
68 * here's the WFI 71 * here's the WFI
69 */ 72 */
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-exynos4/include/mach/dwmci.h b/arch/arm/mach-exynos4/include/mach/dwmci.h
new file mode 100644
index 000000000000..7ce657459cc0
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/dwmci.h
@@ -0,0 +1,20 @@
1/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Synopsys DesignWare Mobile Storage for EXYNOS4210
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARM_ARCH_DWMCI_H
14#define __ASM_ARM_ARCH_DWMCI_H __FILE__
15
16#include <linux/mmc/dw_mmc.h>
17
18extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
19
20#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d8f38c2e5654..d7a1e281ce7a 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -10,6 +10,7 @@
10*/ 10*/
11 11
12#include <mach/hardware.h> 12#include <mach/hardware.h>
13#include <mach/map.h>
13#include <asm/hardware/gic.h> 14#include <asm/hardware/gic.h>
14 15
15 .macro disable_fiq 16 .macro disable_fiq
@@ -18,6 +19,10 @@
18 .macro get_irqnr_preamble, base, tmp 19 .macro get_irqnr_preamble, base, tmp
19 ldr \base, =gic_cpu_base_addr 20 ldr \base, =gic_cpu_base_addr
20 ldr \base, [\base] 21 ldr \base, [\base]
22 mrc p15, 0, \tmp, c0, c0, 5
23 and \tmp, \tmp, #3
24 cmp \tmp, #1
25 addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
21 .endm 26 .endm
22 27
23 .macro arch_ret_to_user, tmp1, tmp2 28 .macro arch_ret_to_user, tmp1, tmp2
@@ -75,10 +80,4 @@
75 /* As above, this assumes that irqstat and base are preserved.. */ 80 /* As above, this assumes that irqstat and base are preserved.. */
76 81
77 .macro test_for_ltirq, irqnr, irqstat, base, tmp 82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
78 bic \irqnr, \irqstat, #0x1c00
79 mov \tmp, #0
80 cmp \irqnr, #29
81 moveq \tmp, #1
82 streq \irqstat, [\base, #GIC_CPU_EOI]
83 cmp \tmp, #0
84 .endm 83 .endm
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 5d037301d21a..934d2a493982 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,40 +19,105 @@
19 19
20#define IRQ_PPI(x) S5P_IRQ(x+16) 20#define IRQ_PPI(x) S5P_IRQ(x+16)
21 21
22#define IRQ_LOCALTIMER IRQ_PPI(13)
23
24/* SPI: Shared Peripheral Interrupt */ 22/* SPI: Shared Peripheral Interrupt */
25 23
26#define IRQ_SPI(x) S5P_IRQ(x+32) 24#define IRQ_SPI(x) S5P_IRQ(x+32)
27 25
28#define IRQ_MCT1 IRQ_SPI(35) 26#define IRQ_EINT0 IRQ_SPI(16)
29 27#define IRQ_EINT1 IRQ_SPI(17)
30#define IRQ_EINT0 IRQ_SPI(40) 28#define IRQ_EINT2 IRQ_SPI(18)
31#define IRQ_EINT1 IRQ_SPI(41) 29#define IRQ_EINT3 IRQ_SPI(19)
32#define IRQ_EINT2 IRQ_SPI(42) 30#define IRQ_EINT4 IRQ_SPI(20)
33#define IRQ_EINT3 IRQ_SPI(43) 31#define IRQ_EINT5 IRQ_SPI(21)
34#define IRQ_USB_HSOTG IRQ_SPI(44) 32#define IRQ_EINT6 IRQ_SPI(22)
35#define IRQ_USB_HOST IRQ_SPI(45) 33#define IRQ_EINT7 IRQ_SPI(23)
36#define IRQ_MODEM_IF IRQ_SPI(46) 34#define IRQ_EINT8 IRQ_SPI(24)
37#define IRQ_ROTATOR IRQ_SPI(47) 35#define IRQ_EINT9 IRQ_SPI(25)
38#define IRQ_JPEG IRQ_SPI(48) 36#define IRQ_EINT10 IRQ_SPI(26)
39#define IRQ_2D IRQ_SPI(49) 37#define IRQ_EINT11 IRQ_SPI(27)
40#define IRQ_PCIE IRQ_SPI(50) 38#define IRQ_EINT12 IRQ_SPI(28)
41#define IRQ_MCT0 IRQ_SPI(51) 39#define IRQ_EINT13 IRQ_SPI(29)
42#define IRQ_MFC IRQ_SPI(52) 40#define IRQ_EINT14 IRQ_SPI(30)
43#define IRQ_AUDIO_SS IRQ_SPI(54) 41#define IRQ_EINT15 IRQ_SPI(31)
44#define IRQ_AC97 IRQ_SPI(55) 42#define IRQ_EINT16_31 IRQ_SPI(32)
45#define IRQ_SPDIF IRQ_SPI(56) 43
46#define IRQ_KEYPAD IRQ_SPI(57) 44#define IRQ_PDMA0 IRQ_SPI(35)
47#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58) 45#define IRQ_PDMA1 IRQ_SPI(36)
48#define IRQ_SLIMBUS IRQ_SPI(59) 46#define IRQ_TIMER0_VIC IRQ_SPI(37)
49#define IRQ_PMU IRQ_SPI(60) 47#define IRQ_TIMER1_VIC IRQ_SPI(38)
50#define IRQ_TSI IRQ_SPI(61) 48#define IRQ_TIMER2_VIC IRQ_SPI(39)
51#define IRQ_SATA IRQ_SPI(62) 49#define IRQ_TIMER3_VIC IRQ_SPI(40)
52#define IRQ_GPS IRQ_SPI(63) 50#define IRQ_TIMER4_VIC IRQ_SPI(41)
51#define IRQ_MCT_L0 IRQ_SPI(42)
52#define IRQ_WDT IRQ_SPI(43)
53#define IRQ_RTC_ALARM IRQ_SPI(44)
54#define IRQ_RTC_TIC IRQ_SPI(45)
55#define IRQ_GPIO_XB IRQ_SPI(46)
56#define IRQ_GPIO_XA IRQ_SPI(47)
57#define IRQ_MCT_L1 IRQ_SPI(48)
58
59#define IRQ_UART0 IRQ_SPI(52)
60#define IRQ_UART1 IRQ_SPI(53)
61#define IRQ_UART2 IRQ_SPI(54)
62#define IRQ_UART3 IRQ_SPI(55)
63#define IRQ_UART4 IRQ_SPI(56)
64#define IRQ_MCT_G0 IRQ_SPI(57)
65#define IRQ_IIC IRQ_SPI(58)
66#define IRQ_IIC1 IRQ_SPI(59)
67#define IRQ_IIC2 IRQ_SPI(60)
68#define IRQ_IIC3 IRQ_SPI(61)
69#define IRQ_IIC4 IRQ_SPI(62)
70#define IRQ_IIC5 IRQ_SPI(63)
71#define IRQ_IIC6 IRQ_SPI(64)
72#define IRQ_IIC7 IRQ_SPI(65)
73
74#define IRQ_USB_HOST IRQ_SPI(70)
75#define IRQ_USB_HSOTG IRQ_SPI(71)
76#define IRQ_MODEM_IF IRQ_SPI(72)
77#define IRQ_HSMMC0 IRQ_SPI(73)
78#define IRQ_HSMMC1 IRQ_SPI(74)
79#define IRQ_HSMMC2 IRQ_SPI(75)
80#define IRQ_HSMMC3 IRQ_SPI(76)
81#define IRQ_DWMCI IRQ_SPI(77)
82
83#define IRQ_MIPICSI0 IRQ_SPI(78)
84
85#define IRQ_MIPICSI1 IRQ_SPI(80)
86
87#define IRQ_ONENAND_AUDI IRQ_SPI(82)
88#define IRQ_ROTATOR IRQ_SPI(83)
89#define IRQ_FIMC0 IRQ_SPI(84)
90#define IRQ_FIMC1 IRQ_SPI(85)
91#define IRQ_FIMC2 IRQ_SPI(86)
92#define IRQ_FIMC3 IRQ_SPI(87)
93#define IRQ_JPEG IRQ_SPI(88)
94#define IRQ_2D IRQ_SPI(89)
95#define IRQ_PCIE IRQ_SPI(90)
96
97#define IRQ_MFC IRQ_SPI(94)
98
99#define IRQ_AUDIO_SS IRQ_SPI(96)
100#define IRQ_I2S0 IRQ_SPI(97)
101#define IRQ_I2S1 IRQ_SPI(98)
102#define IRQ_I2S2 IRQ_SPI(99)
103#define IRQ_AC97 IRQ_SPI(100)
104
105#define IRQ_SPDIF IRQ_SPI(104)
106#define IRQ_ADC0 IRQ_SPI(105)
107#define IRQ_PEN0 IRQ_SPI(106)
108#define IRQ_ADC1 IRQ_SPI(107)
109#define IRQ_PEN1 IRQ_SPI(108)
110#define IRQ_KEYPAD IRQ_SPI(109)
111#define IRQ_PMU IRQ_SPI(110)
112#define IRQ_GPS IRQ_SPI(111)
113#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
114#define IRQ_SLIMBUS IRQ_SPI(113)
115
116#define IRQ_TSI IRQ_SPI(115)
117#define IRQ_SATA IRQ_SPI(116)
53 118
54#define MAX_IRQ_IN_COMBINER 8 119#define MAX_IRQ_IN_COMBINER 8
55#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) 120#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
56#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) 121#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
57 122
58#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) 123#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
@@ -73,75 +138,14 @@
73#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) 138#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
74#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) 139#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
75 140
76#define IRQ_PDMA0 COMBINER_IRQ(21, 0) 141#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
77#define IRQ_PDMA1 COMBINER_IRQ(21, 1) 142#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
78 143#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
79#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
80#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
81#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
82#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
83#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
84
85#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
86#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
87
88#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
89#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
90
91#define IRQ_UART0 COMBINER_IRQ(26, 0)
92#define IRQ_UART1 COMBINER_IRQ(26, 1)
93#define IRQ_UART2 COMBINER_IRQ(26, 2)
94#define IRQ_UART3 COMBINER_IRQ(26, 3)
95#define IRQ_UART4 COMBINER_IRQ(26, 4)
96
97#define IRQ_IIC COMBINER_IRQ(27, 0)
98#define IRQ_IIC1 COMBINER_IRQ(27, 1)
99#define IRQ_IIC2 COMBINER_IRQ(27, 2)
100#define IRQ_IIC3 COMBINER_IRQ(27, 3)
101#define IRQ_IIC4 COMBINER_IRQ(27, 4)
102#define IRQ_IIC5 COMBINER_IRQ(27, 5)
103#define IRQ_IIC6 COMBINER_IRQ(27, 6)
104#define IRQ_IIC7 COMBINER_IRQ(27, 7)
105
106#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
107#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
108#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
109#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
110
111#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
112#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
113
114#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
115#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
116#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
117#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
118
119#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
120
121#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
122
123#define IRQ_EINT4 COMBINER_IRQ(37, 0)
124#define IRQ_EINT5 COMBINER_IRQ(37, 1)
125#define IRQ_EINT6 COMBINER_IRQ(37, 2)
126#define IRQ_EINT7 COMBINER_IRQ(37, 3)
127#define IRQ_EINT8 COMBINER_IRQ(38, 0)
128
129#define IRQ_EINT9 COMBINER_IRQ(38, 1)
130#define IRQ_EINT10 COMBINER_IRQ(38, 2)
131#define IRQ_EINT11 COMBINER_IRQ(38, 3)
132#define IRQ_EINT12 COMBINER_IRQ(38, 4)
133#define IRQ_EINT13 COMBINER_IRQ(38, 5)
134#define IRQ_EINT14 COMBINER_IRQ(38, 6)
135#define IRQ_EINT15 COMBINER_IRQ(38, 7)
136
137#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
138
139#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
140 144
141#define IRQ_WDT COMBINER_IRQ(53, 0) 145#define MAX_COMBINER_NR 16
142#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
143 146
144#define MAX_COMBINER_NR 54 147#define IRQ_ADC IRQ_ADC0
148#define IRQ_TC IRQ_PEN0
145 149
146#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) 150#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
147 151
@@ -155,6 +159,6 @@
155#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) 159#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
156 160
157/* Set the default NR_IRQS */ 161/* Set the default NR_IRQS */
158#define NR_IRQS (IRQ_GPIO_END) 162#define NR_IRQS (IRQ_GPIO_END + 64)
159 163
160#endif /* __ASM_ARCH_IRQS_H */ 164#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 0009e77a05fc..d32296dc65e2 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -57,12 +57,14 @@
57 57
58#define EXYNOS4_PA_DMC0 0x10400000 58#define EXYNOS4_PA_DMC0 0x10400000
59 59
60#define EXYNOS4_PA_COMBINER 0x10448000 60#define EXYNOS4_PA_COMBINER 0x10440000
61
62#define EXYNOS4_PA_GIC_CPU 0x10480000
63#define EXYNOS4_PA_GIC_DIST 0x10490000
64#define EXYNOS4_GIC_BANK_OFFSET 0x8000
61 65
62#define EXYNOS4_PA_COREPERI 0x10500000 66#define EXYNOS4_PA_COREPERI 0x10500000
63#define EXYNOS4_PA_GIC_CPU 0x10500100
64#define EXYNOS4_PA_TWD 0x10500600 67#define EXYNOS4_PA_TWD 0x10500600
65#define EXYNOS4_PA_GIC_DIST 0x10501000
66#define EXYNOS4_PA_L2CC 0x10502000 68#define EXYNOS4_PA_L2CC 0x10502000
67 69
68#define EXYNOS4_PA_MDMA 0x10810000 70#define EXYNOS4_PA_MDMA 0x10810000
@@ -93,7 +95,10 @@
93#define EXYNOS4_PA_MIPI_CSIS0 0x11880000 95#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
94#define EXYNOS4_PA_MIPI_CSIS1 0x11890000 96#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
95 97
98#define EXYNOS4_PA_FIMD0 0x11C00000
99
96#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 100#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
101#define EXYNOS4_PA_DWMCI 0x12550000
97 102
98#define EXYNOS4_PA_SATA 0x12560000 103#define EXYNOS4_PA_SATA 0x12560000
99#define EXYNOS4_PA_SATAPHY 0x125D0000 104#define EXYNOS4_PA_SATAPHY 0x125D0000
@@ -103,11 +108,15 @@
103 108
104#define EXYNOS4_PA_EHCI 0x12580000 109#define EXYNOS4_PA_EHCI 0x12580000
105#define EXYNOS4_PA_HSPHY 0x125B0000 110#define EXYNOS4_PA_HSPHY 0x125B0000
111#define EXYNOS4_PA_MFC 0x13400000
106 112
107#define EXYNOS4_PA_UART 0x13800000 113#define EXYNOS4_PA_UART 0x13800000
108 114
109#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 115#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
110 116
117#define EXYNOS4_PA_ADC 0x13910000
118#define EXYNOS4_PA_ADC1 0x13911000
119
111#define EXYNOS4_PA_AC97 0x139A0000 120#define EXYNOS4_PA_AC97 0x139A0000
112 121
113#define EXYNOS4_PA_SPDIF 0x139B0000 122#define EXYNOS4_PA_SPDIF 0x139B0000
@@ -130,6 +139,8 @@
130#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) 139#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
131#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) 140#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
132#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) 141#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
142#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
143#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
133#define S3C_PA_RTC EXYNOS4_PA_RTC 144#define S3C_PA_RTC EXYNOS4_PA_RTC
134#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 145#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
135 146
@@ -140,10 +151,12 @@
140#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 151#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
141#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 152#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
142#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 153#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
154#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
143#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND 155#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
144#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA 156#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
145#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM 157#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
146#define S5P_PA_SROMC EXYNOS4_PA_SROMC 158#define S5P_PA_SROMC EXYNOS4_PA_SROMC
159#define S5P_PA_MFC EXYNOS4_PA_MFC
147#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON 160#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
148#define S5P_PA_TIMER EXYNOS4_PA_TIMER 161#define S5P_PA_TIMER EXYNOS4_PA_TIMER
149#define S5P_PA_EHCI EXYNOS4_PA_EHCI 162#define S5P_PA_EHCI EXYNOS4_PA_EHCI
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
index f26e46bc06ca..1df3b81f96e8 100644
--- a/arch/arm/mach-exynos4/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
47{ 47{
48 /* nothing here yet */ 48 /* nothing here yet */
49} 49}
50
51static inline void s3c_pm_restored_gpios(void)
52{
53 /* nothing here yet */
54}
55
56static inline void s3c_pm_saved_gpios(void)
57{
58 /* nothing here yet */
59}
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
new file mode 100644
index 000000000000..a952904b010e
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4210 - PMU(Power Management Unit) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_PMU_H
14#define __ASM_ARCH_PMU_H __FILE__
15
16enum sys_powerdown {
17 SYS_AFTR,
18 SYS_LPA,
19 SYS_SLEEP,
20 NUM_SYS_POWERDOWN,
21};
22
23extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
24
25#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-audss.h b/arch/arm/mach-exynos4/include/mach/regs-audss.h
new file mode 100644
index 000000000000..ca5a8b64218a
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-exynos4/include/mach/regs-audss.h
2 *
3 * Copyright (c) 2011 Samsung Electronics
4 * http://www.samsung.com
5 *
6 * Exynos4 Audio SubSystem clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_REGS_AUDSS_H
14#define __PLAT_REGS_AUDSS_H __FILE__
15
16#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
17
18#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1157f5..d493fdb422ff 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
25#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) 25#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
26#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) 26#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
27 27
28#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
29#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
30
28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) 31#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) 32#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
30#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) 33#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@@ -33,7 +36,9 @@
33#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) 36#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
34#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) 37#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
35#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) 38#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
39#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
36#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) 40#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
41#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
37#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) 42#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
38#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) 43#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
39#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) 44#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
@@ -61,6 +66,7 @@
61#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) 66#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
62#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) 67#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
63#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) 68#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
69#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
64 70
65#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) 71#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
66#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) 72#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
@@ -120,6 +126,12 @@
120#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) 126#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
121#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) 127#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
122 128
129#define S5P_EPLLCON0_ENABLE_SHIFT (31)
130#define S5P_EPLLCON0_LOCKED_SHIFT (29)
131
132#define S5P_VPLLCON0_ENABLE_SHIFT (31)
133#define S5P_VPLLCON0_LOCKED_SHIFT (29)
134
123#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) 135#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
124#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) 136#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
125 137
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index a9643371f8e7..fa49bbb8e7b0 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -158,6 +158,7 @@
158#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) 158#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
159 159
160#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 160#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
161#define S5P_CORE_LOCAL_PWR_EN 0x3
161#define S5P_INT_LOCAL_PWR_EN 0x7 162#define S5P_INT_LOCAL_PWR_EN 0x7
162 163
163#define S5P_CHECK_SLEEP 0x00000BAD 164#define S5P_CHECK_SLEEP 0x00000BAD
diff --git a/arch/arm/mach-exynos4/localtimer.c b/arch/arm/mach-exynos4/localtimer.c
deleted file mode 100644
index 6bf3d0ab9627..000000000000
--- a/arch/arm/mach-exynos4/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
1/* linux/arch/arm/mach-exynos4/localtimer.c
2 *
3 * Cloned from linux/arch/arm/mach-realview/localtimer.c
4 *
5 * Copyright (C) 2002 ARM Ltd.
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/clockchips.h>
14
15#include <asm/irq.h>
16#include <asm/localtimer.h>
17
18/*
19 * Setup the local clock events for a CPU.
20 */
21int __cpuinit local_timer_setup(struct clock_event_device *evt)
22{
23 evt->irq = IRQ_LOCALTIMER;
24 twd_timer_setup(evt);
25 return 0;
26}
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 642702bb5b12..43be71b799cb 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -13,10 +13,15 @@
13#include <linux/input.h> 13#include <linux/input.h>
14#include <linux/i2c.h> 14#include <linux/i2c.h>
15#include <linux/i2c/atmel_mxt_ts.h> 15#include <linux/i2c/atmel_mxt_ts.h>
16#include <linux/i2c-gpio.h>
16#include <linux/gpio_keys.h> 17#include <linux/gpio_keys.h>
17#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include <linux/power/max8903_charger.h>
20#include <linux/power/max17042_battery.h>
18#include <linux/regulator/machine.h> 21#include <linux/regulator/machine.h>
19#include <linux/regulator/fixed.h> 22#include <linux/regulator/fixed.h>
23#include <linux/mfd/max8997.h>
24#include <linux/mfd/max8997-private.h>
20#include <linux/mmc/host.h> 25#include <linux/mmc/host.h>
21#include <linux/fb.h> 26#include <linux/fb.h>
22#include <linux/pwm_backlight.h> 27#include <linux/pwm_backlight.h>
@@ -26,6 +31,7 @@
26#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
27#include <asm/mach-types.h> 32#include <asm/mach-types.h>
28 33
34#include <plat/adc.h>
29#include <plat/regs-serial.h> 35#include <plat/regs-serial.h>
30#include <plat/exynos4.h> 36#include <plat/exynos4.h>
31#include <plat/cpu.h> 37#include <plat/cpu.h>
@@ -35,6 +41,8 @@
35#include <plat/clock.h> 41#include <plat/clock.h>
36#include <plat/gpio-cfg.h> 42#include <plat/gpio-cfg.h>
37#include <plat/iic.h> 43#include <plat/iic.h>
44#include <plat/mfc.h>
45#include <plat/pd.h>
38 46
39#include <mach/map.h> 47#include <mach/map.h>
40 48
@@ -54,6 +62,7 @@
54 62
55enum fixed_regulator_id { 63enum fixed_regulator_id {
56 FIXED_REG_ID_MMC = 0, 64 FIXED_REG_ID_MMC = 0,
65 FIXED_REG_ID_MAX8903,
57}; 66};
58 67
59static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = { 68static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -344,10 +353,730 @@ static void __init nuri_tsp_init(void)
344 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 353 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
345} 354}
346 355
356static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
357 REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
358};
359static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
360 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
361};
362static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
363 REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
364};
365static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
366 REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
367};
368static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
369 REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
370};
371static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
372 REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */
373 REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
374};
375static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
376 REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
377};
378static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
379 REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
380};
381static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
382 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
383};
384static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
385 REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
386};
387static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
388 REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
389};
390static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
391 REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
392};
393static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
394 REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
395};
396static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
397 REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
398};
399static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
400 REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
401};
402static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
403 REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
404};
405static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
406 REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
407};
408static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
409 REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
410};
411static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
412 REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
413};
414static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
415 REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
416};
417
418static struct regulator_consumer_supply __initdata max8997_charger_[] = {
419 REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
420};
421static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
422 REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
423};
424
425static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
426 REGULATOR_SUPPLY("gps_clk", "bcm4751"),
427 REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
428 REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
429};
430
431static struct regulator_init_data __initdata max8997_ldo1_data = {
432 .constraints = {
433 .name = "VADC_3.3V_C210",
434 .min_uV = 3300000,
435 .max_uV = 3300000,
436 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
437 .apply_uV = 1,
438 .state_mem = {
439 .disabled = 1,
440 },
441 },
442 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo1_),
443 .consumer_supplies = max8997_ldo1_,
444};
445
446static struct regulator_init_data __initdata max8997_ldo2_data = {
447 .constraints = {
448 .name = "VALIVE_1.1V_C210",
449 .min_uV = 1100000,
450 .max_uV = 1100000,
451 .apply_uV = 1,
452 .always_on = 1,
453 .state_mem = {
454 .enabled = 1,
455 },
456 },
457};
458
459static struct regulator_init_data __initdata max8997_ldo3_data = {
460 .constraints = {
461 .name = "VUSB_1.1V_C210",
462 .min_uV = 1100000,
463 .max_uV = 1100000,
464 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
465 .apply_uV = 1,
466 .state_mem = {
467 .disabled = 1,
468 },
469 },
470 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo3_),
471 .consumer_supplies = max8997_ldo3_,
472};
473
474static struct regulator_init_data __initdata max8997_ldo4_data = {
475 .constraints = {
476 .name = "VMIPI_1.8V",
477 .min_uV = 1800000,
478 .max_uV = 1800000,
479 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
480 .apply_uV = 1,
481 .state_mem = {
482 .disabled = 1,
483 },
484 },
485 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo4_),
486 .consumer_supplies = max8997_ldo4_,
487};
488
489static struct regulator_init_data __initdata max8997_ldo5_data = {
490 .constraints = {
491 .name = "VHSIC_1.2V_C210",
492 .min_uV = 1200000,
493 .max_uV = 1200000,
494 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
495 .apply_uV = 1,
496 .state_mem = {
497 .disabled = 1,
498 },
499 },
500 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo5_),
501 .consumer_supplies = max8997_ldo5_,
502};
503
504static struct regulator_init_data __initdata max8997_ldo6_data = {
505 .constraints = {
506 .name = "VCC_1.8V_PDA",
507 .min_uV = 1800000,
508 .max_uV = 1800000,
509 .apply_uV = 1,
510 .always_on = 1,
511 .state_mem = {
512 .enabled = 1,
513 },
514 },
515};
516
517static struct regulator_init_data __initdata max8997_ldo7_data = {
518 .constraints = {
519 .name = "CAM_ISP_1.8V",
520 .min_uV = 1800000,
521 .max_uV = 1800000,
522 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
523 .apply_uV = 1,
524 .state_mem = {
525 .disabled = 1,
526 },
527 },
528 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo7_),
529 .consumer_supplies = max8997_ldo7_,
530};
531
532static struct regulator_init_data __initdata max8997_ldo8_data = {
533 .constraints = {
534 .name = "VUSB/VDAC_3.3V_C210",
535 .min_uV = 3300000,
536 .max_uV = 3300000,
537 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
538 .apply_uV = 1,
539 .state_mem = {
540 .disabled = 1,
541 },
542 },
543 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo8_),
544 .consumer_supplies = max8997_ldo8_,
545};
546
547static struct regulator_init_data __initdata max8997_ldo9_data = {
548 .constraints = {
549 .name = "VCC_2.8V_PDA",
550 .min_uV = 2800000,
551 .max_uV = 2800000,
552 .apply_uV = 1,
553 .always_on = 1,
554 .state_mem = {
555 .enabled = 1,
556 },
557 },
558};
559
560static struct regulator_init_data __initdata max8997_ldo10_data = {
561 .constraints = {
562 .name = "VPLL_1.1V_C210",
563 .min_uV = 1100000,
564 .max_uV = 1100000,
565 .apply_uV = 1,
566 .always_on = 1,
567 .state_mem = {
568 .disabled = 1,
569 },
570 },
571};
572
573static struct regulator_init_data __initdata max8997_ldo11_data = {
574 .constraints = {
575 .name = "LVDS_VDD3.3V",
576 .min_uV = 3300000,
577 .max_uV = 3300000,
578 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
579 .apply_uV = 1,
580 .boot_on = 1,
581 .state_mem = {
582 .disabled = 1,
583 },
584 },
585 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo11_),
586 .consumer_supplies = max8997_ldo11_,
587};
588
589static struct regulator_init_data __initdata max8997_ldo12_data = {
590 .constraints = {
591 .name = "VT_CAM_1.8V",
592 .min_uV = 1800000,
593 .max_uV = 1800000,
594 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
595 .apply_uV = 1,
596 .state_mem = {
597 .disabled = 1,
598 },
599 },
600 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo12_),
601 .consumer_supplies = max8997_ldo12_,
602};
603
604static struct regulator_init_data __initdata max8997_ldo13_data = {
605 .constraints = {
606 .name = "VTF_2.8V",
607 .min_uV = 2800000,
608 .max_uV = 2800000,
609 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
610 .apply_uV = 1,
611 .state_mem = {
612 .disabled = 1,
613 },
614 },
615 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo13_),
616 .consumer_supplies = max8997_ldo13_,
617};
618
619static struct regulator_init_data __initdata max8997_ldo14_data = {
620 .constraints = {
621 .name = "VCC_3.0V_MOTOR",
622 .min_uV = 3000000,
623 .max_uV = 3000000,
624 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
625 .apply_uV = 1,
626 .state_mem = {
627 .disabled = 1,
628 },
629 },
630 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo14_),
631 .consumer_supplies = max8997_ldo14_,
632};
633
634static struct regulator_init_data __initdata max8997_ldo15_data = {
635 .constraints = {
636 .name = "VTOUCH_ADVV2.8V",
637 .min_uV = 2800000,
638 .max_uV = 2800000,
639 .apply_uV = 1,
640 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
641 .state_mem = {
642 .disabled = 1,
643 },
644 },
645 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo15_),
646 .consumer_supplies = max8997_ldo15_,
647};
648
649static struct regulator_init_data __initdata max8997_ldo16_data = {
650 .constraints = {
651 .name = "CAM_SENSOR_IO_1.8V",
652 .min_uV = 1800000,
653 .max_uV = 1800000,
654 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
655 .apply_uV = 1,
656 .state_mem = {
657 .disabled = 1,
658 },
659 },
660 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo16_),
661 .consumer_supplies = max8997_ldo16_,
662};
663
664static struct regulator_init_data __initdata max8997_ldo18_data = {
665 .constraints = {
666 .name = "VTOUCH_VDD2.8V",
667 .min_uV = 2800000,
668 .max_uV = 2800000,
669 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
670 .apply_uV = 1,
671 .state_mem = {
672 .disabled = 1,
673 },
674 },
675 .num_consumer_supplies = ARRAY_SIZE(max8997_ldo18_),
676 .consumer_supplies = max8997_ldo18_,
677};
678
679static struct regulator_init_data __initdata max8997_ldo21_data = {
680 .constraints = {
681 .name = "VDDQ_M1M2_1.2V",
682 .min_uV = 1200000,
683 .max_uV = 1200000,
684 .apply_uV = 1,
685 .always_on = 1,
686 .state_mem = {
687 .disabled = 1,
688 },
689 },
690};
691
692static struct regulator_init_data __initdata max8997_buck1_data = {
693 .constraints = {
694 .name = "VARM_1.2V_C210",
695 .min_uV = 900000,
696 .max_uV = 1350000,
697 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
698 .always_on = 1,
699 .state_mem = {
700 .disabled = 1,
701 },
702 },
703 .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
704 .consumer_supplies = max8997_buck1_,
705};
706
707static struct regulator_init_data __initdata max8997_buck2_data = {
708 .constraints = {
709 .name = "VINT_1.1V_C210",
710 .min_uV = 900000,
711 .max_uV = 1100000,
712 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
713 .always_on = 1,
714 .state_mem = {
715 .disabled = 1,
716 },
717 },
718 .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
719 .consumer_supplies = max8997_buck2_,
720};
721
722static struct regulator_init_data __initdata max8997_buck3_data = {
723 .constraints = {
724 .name = "VG3D_1.1V_C210",
725 .min_uV = 900000,
726 .max_uV = 1100000,
727 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
728 REGULATOR_CHANGE_STATUS,
729 .state_mem = {
730 .disabled = 1,
731 },
732 },
733 .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
734 .consumer_supplies = max8997_buck3_,
735};
736
737static struct regulator_init_data __initdata max8997_buck4_data = {
738 .constraints = {
739 .name = "CAM_ISP_CORE_1.2V",
740 .min_uV = 1200000,
741 .max_uV = 1200000,
742 .apply_uV = 1,
743 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
744 .state_mem = {
745 .disabled = 1,
746 },
747 },
748 .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
749 .consumer_supplies = max8997_buck4_,
750};
751
752static struct regulator_init_data __initdata max8997_buck5_data = {
753 .constraints = {
754 .name = "VMEM_1.2V_C210",
755 .min_uV = 1200000,
756 .max_uV = 1200000,
757 .apply_uV = 1,
758 .always_on = 1,
759 .state_mem = {
760 .enabled = 1,
761 },
762 },
763};
764
765static struct regulator_init_data __initdata max8997_buck6_data = {
766 .constraints = {
767 .name = "CAM_AF_2.8V",
768 .min_uV = 2800000,
769 .max_uV = 2800000,
770 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
771 .state_mem = {
772 .disabled = 1,
773 },
774 },
775 .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
776 .consumer_supplies = max8997_buck6_,
777};
778
779static struct regulator_init_data __initdata max8997_buck7_data = {
780 .constraints = {
781 .name = "VCC_SUB_2.0V",
782 .min_uV = 2000000,
783 .max_uV = 2000000,
784 .apply_uV = 1,
785 .always_on = 1,
786 .state_mem = {
787 .enabled = 1,
788 },
789 },
790};
791
792static struct regulator_init_data __initdata max8997_32khz_ap_data = {
793 .constraints = {
794 .name = "32KHz AP",
795 .always_on = 1,
796 .state_mem = {
797 .enabled = 1,
798 },
799 },
800 .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
801 .consumer_supplies = max8997_32khz_ap_,
802};
803
804static struct regulator_init_data __initdata max8997_32khz_cp_data = {
805 .constraints = {
806 .name = "32KHz CP",
807 .state_mem = {
808 .disabled = 1,
809 },
810 },
811};
812
813static struct regulator_init_data __initdata max8997_vichg_data = {
814 .constraints = {
815 .name = "VICHG",
816 .state_mem = {
817 .disabled = 1,
818 },
819 },
820};
821
822static struct regulator_init_data __initdata max8997_esafeout1_data = {
823 .constraints = {
824 .name = "SAFEOUT1",
825 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
826 .state_mem = {
827 .disabled = 1,
828 },
829 },
830 .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout1_),
831 .consumer_supplies = max8997_esafeout1_,
832};
833
834static struct regulator_init_data __initdata max8997_esafeout2_data = {
835 .constraints = {
836 .name = "SAFEOUT2",
837 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
838 .state_mem = {
839 .disabled = 1,
840 },
841 },
842 .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout2_),
843 .consumer_supplies = max8997_esafeout2_,
844};
845
846static struct regulator_init_data __initdata max8997_charger_cv_data = {
847 .constraints = {
848 .name = "CHARGER_CV",
849 .min_uV = 4200000,
850 .max_uV = 4200000,
851 .apply_uV = 1,
852 },
853};
854
855static struct regulator_init_data __initdata max8997_charger_data = {
856 .constraints = {
857 .name = "CHARGER",
858 .min_uA = 200000,
859 .max_uA = 950000,
860 .boot_on = 1,
861 .valid_ops_mask = REGULATOR_CHANGE_STATUS |
862 REGULATOR_CHANGE_CURRENT,
863 },
864 .num_consumer_supplies = ARRAY_SIZE(max8997_charger_),
865 .consumer_supplies = max8997_charger_,
866};
867
868static struct regulator_init_data __initdata max8997_charger_topoff_data = {
869 .constraints = {
870 .name = "CHARGER TOPOFF",
871 .min_uA = 50000,
872 .max_uA = 200000,
873 .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
874 },
875 .num_consumer_supplies = ARRAY_SIZE(max8997_chg_toff_),
876 .consumer_supplies = max8997_chg_toff_,
877};
878
879static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
880 { MAX8997_LDO1, &max8997_ldo1_data },
881 { MAX8997_LDO2, &max8997_ldo2_data },
882 { MAX8997_LDO3, &max8997_ldo3_data },
883 { MAX8997_LDO4, &max8997_ldo4_data },
884 { MAX8997_LDO5, &max8997_ldo5_data },
885 { MAX8997_LDO6, &max8997_ldo6_data },
886 { MAX8997_LDO7, &max8997_ldo7_data },
887 { MAX8997_LDO8, &max8997_ldo8_data },
888 { MAX8997_LDO9, &max8997_ldo9_data },
889 { MAX8997_LDO10, &max8997_ldo10_data },
890 { MAX8997_LDO11, &max8997_ldo11_data },
891 { MAX8997_LDO12, &max8997_ldo12_data },
892 { MAX8997_LDO13, &max8997_ldo13_data },
893 { MAX8997_LDO14, &max8997_ldo14_data },
894 { MAX8997_LDO15, &max8997_ldo15_data },
895 { MAX8997_LDO16, &max8997_ldo16_data },
896
897 { MAX8997_LDO18, &max8997_ldo18_data },
898 { MAX8997_LDO21, &max8997_ldo21_data },
899
900 { MAX8997_BUCK1, &max8997_buck1_data },
901 { MAX8997_BUCK2, &max8997_buck2_data },
902 { MAX8997_BUCK3, &max8997_buck3_data },
903 { MAX8997_BUCK4, &max8997_buck4_data },
904 { MAX8997_BUCK5, &max8997_buck5_data },
905 { MAX8997_BUCK6, &max8997_buck6_data },
906 { MAX8997_BUCK7, &max8997_buck7_data },
907
908 { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
909 { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
910
911 { MAX8997_ENVICHG, &max8997_vichg_data },
912 { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
913 { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
914 { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
915 { MAX8997_CHARGER, &max8997_charger_data },
916 { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
917};
918
919static struct max8997_platform_data __initdata nuri_max8997_pdata = {
920 .wakeup = 1,
921
922 .num_regulators = ARRAY_SIZE(nuri_max8997_regulators),
923 .regulators = nuri_max8997_regulators,
924
925 .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
926 .buck2_gpiodvs = true,
927
928 .buck1_voltage[0] = 1350000, /* 1.35V */
929 .buck1_voltage[1] = 1300000, /* 1.3V */
930 .buck1_voltage[2] = 1250000, /* 1.25V */
931 .buck1_voltage[3] = 1200000, /* 1.2V */
932 .buck1_voltage[4] = 1150000, /* 1.15V */
933 .buck1_voltage[5] = 1100000, /* 1.1V */
934 .buck1_voltage[6] = 1000000, /* 1.0V */
935 .buck1_voltage[7] = 950000, /* 0.95V */
936
937 .buck2_voltage[0] = 1100000, /* 1.1V */
938 .buck2_voltage[1] = 1000000, /* 1.0V */
939 .buck2_voltage[2] = 950000, /* 0.95V */
940 .buck2_voltage[3] = 900000, /* 0.9V */
941 .buck2_voltage[4] = 1100000, /* 1.1V */
942 .buck2_voltage[5] = 1000000, /* 1.0V */
943 .buck2_voltage[6] = 950000, /* 0.95V */
944 .buck2_voltage[7] = 900000, /* 0.9V */
945
946 .buck5_voltage[0] = 1200000, /* 1.2V */
947 .buck5_voltage[1] = 1200000, /* 1.2V */
948 .buck5_voltage[2] = 1200000, /* 1.2V */
949 .buck5_voltage[3] = 1200000, /* 1.2V */
950 .buck5_voltage[4] = 1200000, /* 1.2V */
951 .buck5_voltage[5] = 1200000, /* 1.2V */
952 .buck5_voltage[6] = 1200000, /* 1.2V */
953 .buck5_voltage[7] = 1200000, /* 1.2V */
954};
955
347/* GPIO I2C 5 (PMIC) */ 956/* GPIO I2C 5 (PMIC) */
957enum { I2C5_MAX8997 };
348static struct i2c_board_info i2c5_devs[] __initdata = { 958static struct i2c_board_info i2c5_devs[] __initdata = {
349 /* max8997, To be updated */ 959 [I2C5_MAX8997] = {
960 I2C_BOARD_INFO("max8997", 0xCC >> 1),
961 .platform_data = &nuri_max8997_pdata,
962 },
963};
964
965static struct max17042_platform_data nuri_battery_platform_data = {
966};
967
968/* GPIO I2C 9 (Fuel Gauge) */
969static struct i2c_gpio_platform_data i2c9_gpio_data = {
970 .sda_pin = EXYNOS4_GPY4(0), /* XM0ADDR_8 */
971 .scl_pin = EXYNOS4_GPY4(1), /* XM0ADDR_9 */
972};
973static struct platform_device i2c9_gpio = {
974 .name = "i2c-gpio",
975 .id = 9,
976 .dev = {
977 .platform_data = &i2c9_gpio_data,
978 },
350}; 979};
980enum { I2C9_MAX17042};
981static struct i2c_board_info i2c9_devs[] __initdata = {
982 [I2C9_MAX17042] = {
983 I2C_BOARD_INFO("max17042", 0x36),
984 .platform_data = &nuri_battery_platform_data,
985 },
986};
987
988/* MAX8903 Secondary Charger */
989static struct regulator_consumer_supply supplies_max8903[] = {
990 REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
991};
992
993static struct regulator_init_data max8903_charger_en_data = {
994 .constraints = {
995 .name = "VOUT_CHARGER",
996 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
997 .boot_on = 1,
998 },
999 .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
1000 .consumer_supplies = supplies_max8903,
1001};
1002
1003static struct fixed_voltage_config max8903_charger_en = {
1004 .supply_name = "VOUT_CHARGER",
1005 .microvolts = 5000000, /* Assume 5VDC */
1006 .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
1007 .enable_high = 0, /* Enable = Low */
1008 .enabled_at_boot = 1,
1009 .init_data = &max8903_charger_en_data,
1010};
1011
1012static struct platform_device max8903_fixed_reg_dev = {
1013 .name = "reg-fixed-voltage",
1014 .id = FIXED_REG_ID_MAX8903,
1015 .dev = { .platform_data = &max8903_charger_en },
1016};
1017
1018static struct max8903_pdata nuri_max8903 = {
1019 /*
1020 * cen: don't control with the driver, let it be
1021 * controlled by regulator above
1022 */
1023 .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
1024 /* uok, usus: not connected */
1025 .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
1026 /* flt: vcc_1.8V_pda */
1027 .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
1028
1029 .dc_valid = true,
1030 .usb_valid = false, /* USB is not wired to MAX8903 */
1031};
1032
1033static struct platform_device nuri_max8903_device = {
1034 .name = "max8903-charger",
1035 .dev = {
1036 .platform_data = &nuri_max8903,
1037 },
1038};
1039
1040static struct device *nuri_cm_devices[] = {
1041 &s3c_device_i2c5.dev,
1042 &s3c_device_adc.dev,
1043 NULL, /* Reserved for UART */
1044 NULL,
1045};
1046
1047static void __init nuri_power_init(void)
1048{
1049 int gpio;
1050 int irq_base = IRQ_GPIO_END + 1;
1051 int ta_en = 0;
1052
1053 nuri_max8997_pdata.irq_base = irq_base;
1054 irq_base += MAX8997_IRQ_NR;
1055
1056 gpio = EXYNOS4_GPX0(7);
1057 gpio_request(gpio, "AP_PMIC_IRQ");
1058 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
1059 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
1060
1061 gpio = EXYNOS4_GPX2(3);
1062 gpio_request(gpio, "FUEL_ALERT");
1063 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
1064 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
1065
1066 gpio = nuri_max8903.dok;
1067 gpio_request(gpio, "TA_nCONNECTED");
1068 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
1069 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
1070 ta_en = gpio_get_value(gpio) ? 0 : 1;
1071
1072 gpio = nuri_max8903.chg;
1073 gpio_request(gpio, "TA_nCHG");
1074 gpio_direction_input(gpio);
1075
1076 gpio = nuri_max8903.dcm;
1077 gpio_request(gpio, "CURR_ADJ");
1078 gpio_direction_output(gpio, ta_en);
1079}
351 1080
352/* USB EHCI */ 1081/* USB EHCI */
353static struct s5p_ehci_platdata nuri_ehci_pdata; 1082static struct s5p_ehci_platdata nuri_ehci_pdata;
@@ -361,6 +1090,7 @@ static void __init nuri_ehci_init(void)
361 1090
362static struct platform_device *nuri_devices[] __initdata = { 1091static struct platform_device *nuri_devices[] __initdata = {
363 /* Samsung Platform Devices */ 1092 /* Samsung Platform Devices */
1093 &s3c_device_i2c5, /* PMIC should initialize first */
364 &emmc_fixed_voltage, 1094 &emmc_fixed_voltage,
365 &s3c_device_hsmmc0, 1095 &s3c_device_hsmmc0,
366 &s3c_device_hsmmc2, 1096 &s3c_device_hsmmc2,
@@ -369,11 +1099,20 @@ static struct platform_device *nuri_devices[] __initdata = {
369 &s3c_device_timer[0], 1099 &s3c_device_timer[0],
370 &s5p_device_ehci, 1100 &s5p_device_ehci,
371 &s3c_device_i2c3, 1101 &s3c_device_i2c3,
1102 &i2c9_gpio,
1103 &s3c_device_adc,
1104 &s3c_device_rtc,
1105 &s5p_device_mfc,
1106 &s5p_device_mfc_l,
1107 &s5p_device_mfc_r,
1108 &exynos4_device_pd[PD_MFC],
372 1109
373 /* NURI Devices */ 1110 /* NURI Devices */
374 &nuri_gpio_keys, 1111 &nuri_gpio_keys,
375 &nuri_lcd_device, 1112 &nuri_lcd_device,
376 &nuri_backlight_device, 1113 &nuri_backlight_device,
1114 &max8903_fixed_reg_dev,
1115 &nuri_max8903_device,
377}; 1116};
378 1117
379static void __init nuri_map_io(void) 1118static void __init nuri_map_io(void)
@@ -383,21 +1122,32 @@ static void __init nuri_map_io(void)
383 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); 1122 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
384} 1123}
385 1124
1125static void __init nuri_reserve(void)
1126{
1127 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
1128}
1129
386static void __init nuri_machine_init(void) 1130static void __init nuri_machine_init(void)
387{ 1131{
388 nuri_sdhci_init(); 1132 nuri_sdhci_init();
389 nuri_tsp_init(); 1133 nuri_tsp_init();
1134 nuri_power_init();
390 1135
391 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); 1136 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
392 s3c_i2c3_set_platdata(&i2c3_data); 1137 s3c_i2c3_set_platdata(&i2c3_data);
393 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); 1138 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
1139 s3c_i2c5_set_platdata(NULL);
1140 i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
394 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); 1141 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
1142 i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
1143 i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
395 1144
396 nuri_ehci_init(); 1145 nuri_ehci_init();
397 clk_xusbxti.rate = 24000000; 1146 clk_xusbxti.rate = 24000000;
398 1147
399 /* Last */ 1148 /* Last */
400 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); 1149 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
1150 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
401} 1151}
402 1152
403MACHINE_START(NURI, "NURI") 1153MACHINE_START(NURI, "NURI")
@@ -407,4 +1157,5 @@ MACHINE_START(NURI, "NURI")
407 .map_io = nuri_map_io, 1157 .map_io = nuri_map_io,
408 .init_machine = nuri_machine_init, 1158 .init_machine = nuri_machine_init,
409 .timer = &exynos4_timer, 1159 .timer = &exynos4_timer,
1160 .reserve = &nuri_reserve,
410MACHINE_END 1161MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index e645f7a955f0..a7c65e05c1eb 100644
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -9,24 +9,33 @@
9*/ 9*/
10 10
11#include <linux/serial_core.h> 11#include <linux/serial_core.h>
12#include <linux/delay.h>
12#include <linux/gpio.h> 13#include <linux/gpio.h>
14#include <linux/lcd.h>
13#include <linux/mmc/host.h> 15#include <linux/mmc/host.h>
14#include <linux/platform_device.h> 16#include <linux/platform_device.h>
15#include <linux/smsc911x.h> 17#include <linux/smsc911x.h>
16#include <linux/io.h> 18#include <linux/io.h>
17#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/pwm_backlight.h>
18 21
19#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
20#include <asm/mach-types.h> 23#include <asm/mach-types.h>
21 24
25#include <video/platform_lcd.h>
26
22#include <plat/regs-serial.h> 27#include <plat/regs-serial.h>
23#include <plat/regs-srom.h> 28#include <plat/regs-srom.h>
29#include <plat/regs-fb-v4.h>
24#include <plat/exynos4.h> 30#include <plat/exynos4.h>
25#include <plat/cpu.h> 31#include <plat/cpu.h>
26#include <plat/devs.h> 32#include <plat/devs.h>
33#include <plat/fb.h>
27#include <plat/sdhci.h> 34#include <plat/sdhci.h>
28#include <plat/iic.h> 35#include <plat/iic.h>
29#include <plat/pd.h> 36#include <plat/pd.h>
37#include <plat/gpio-cfg.h>
38#include <plat/backlight.h>
30 39
31#include <mach/map.h> 40#include <mach/map.h>
32 41
@@ -111,6 +120,67 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 120 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112}; 121};
113 122
123static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
124 unsigned int power)
125{
126 if (power) {
127#if !defined(CONFIG_BACKLIGHT_PWM)
128 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
129 gpio_free(EXYNOS4_GPD0(1));
130#endif
131 /* fire nRESET on power up */
132 gpio_request(EXYNOS4_GPX0(6), "GPX0");
133
134 gpio_direction_output(EXYNOS4_GPX0(6), 1);
135 mdelay(100);
136
137 gpio_set_value(EXYNOS4_GPX0(6), 0);
138 mdelay(10);
139
140 gpio_set_value(EXYNOS4_GPX0(6), 1);
141 mdelay(10);
142
143 gpio_free(EXYNOS4_GPX0(6));
144 } else {
145#if !defined(CONFIG_BACKLIGHT_PWM)
146 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
147 gpio_free(EXYNOS4_GPD0(1));
148#endif
149 }
150}
151
152static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
153 .set_power = lcd_lte480wv_set_power,
154};
155
156static struct platform_device smdkc210_lcd_lte480wv = {
157 .name = "platform-lcd",
158 .dev.parent = &s5p_device_fimd0.dev,
159 .dev.platform_data = &smdkc210_lcd_lte480wv_data,
160};
161
162static struct s3c_fb_pd_win smdkc210_fb_win0 = {
163 .win_mode = {
164 .left_margin = 13,
165 .right_margin = 8,
166 .upper_margin = 7,
167 .lower_margin = 5,
168 .hsync_len = 3,
169 .vsync_len = 1,
170 .xres = 800,
171 .yres = 480,
172 },
173 .max_bpp = 32,
174 .default_bpp = 24,
175};
176
177static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
178 .win[0] = &smdkc210_fb_win0,
179 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
180 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
181 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
182};
183
114static struct resource smdkc210_smsc911x_resources[] = { 184static struct resource smdkc210_smsc911x_resources[] = {
115 [0] = { 185 [0] = {
116 .start = EXYNOS4_PA_SROM_BANK(1), 186 .start = EXYNOS4_PA_SROM_BANK(1),
@@ -165,6 +235,8 @@ static struct platform_device *smdkc210_devices[] __initdata = {
165 &exynos4_device_pd[PD_GPS], 235 &exynos4_device_pd[PD_GPS],
166 &exynos4_device_sysmmu, 236 &exynos4_device_sysmmu,
167 &samsung_asoc_dma, 237 &samsung_asoc_dma,
238 &s5p_device_fimd0,
239 &smdkc210_lcd_lte480wv,
168 &smdkc210_smsc911x, 240 &smdkc210_smsc911x,
169}; 241};
170 242
@@ -191,6 +263,17 @@ static void __init smdkc210_smsc911x_init(void)
191 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); 263 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
192} 264}
193 265
266/* LCD Backlight data */
267static struct samsung_bl_gpio_info smdkc210_bl_gpio_info = {
268 .no = EXYNOS4_GPD0(1),
269 .func = S3C_GPIO_SFN(2),
270};
271
272static struct platform_pwm_backlight_data smdkc210_bl_data = {
273 .pwm_id = 1,
274 .pwm_period_ns = 1000,
275};
276
194static void __init smdkc210_map_io(void) 277static void __init smdkc210_map_io(void)
195{ 278{
196 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 279 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -210,6 +293,9 @@ static void __init smdkc210_machine_init(void)
210 s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata); 293 s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
211 s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); 294 s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
212 295
296 samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data);
297 s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
298
213 platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); 299 platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
214} 300}
215 301
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index edd814110da8..ea4149556860 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -16,6 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/input.h> 18#include <linux/input.h>
19#include <linux/pwm_backlight.h>
19 20
20#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
21#include <asm/mach-types.h> 22#include <asm/mach-types.h>
@@ -29,6 +30,8 @@
29#include <plat/sdhci.h> 30#include <plat/sdhci.h>
30#include <plat/iic.h> 31#include <plat/iic.h>
31#include <plat/pd.h> 32#include <plat/pd.h>
33#include <plat/gpio-cfg.h>
34#include <plat/backlight.h>
32 35
33#include <mach/map.h> 36#include <mach/map.h>
34 37
@@ -181,9 +184,12 @@ static struct platform_device *smdkv310_devices[] __initdata = {
181 &exynos4_device_pd[PD_CAM], 184 &exynos4_device_pd[PD_CAM],
182 &exynos4_device_pd[PD_TV], 185 &exynos4_device_pd[PD_TV],
183 &exynos4_device_pd[PD_GPS], 186 &exynos4_device_pd[PD_GPS],
187 &exynos4_device_spdif,
184 &exynos4_device_sysmmu, 188 &exynos4_device_sysmmu,
185 &samsung_asoc_dma, 189 &samsung_asoc_dma,
190 &samsung_asoc_idma,
186 &smdkv310_smsc911x, 191 &smdkv310_smsc911x,
192 &exynos4_device_ahci,
187}; 193};
188 194
189static void __init smdkv310_smsc911x_init(void) 195static void __init smdkv310_smsc911x_init(void)
@@ -209,6 +215,17 @@ static void __init smdkv310_smsc911x_init(void)
209 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); 215 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
210} 216}
211 217
218/* LCD Backlight data */
219static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
220 .no = EXYNOS4_GPD0(1),
221 .func = S3C_GPIO_SFN(2),
222};
223
224static struct platform_pwm_backlight_data smdkv310_bl_data = {
225 .pwm_id = 1,
226 .pwm_period_ns = 1000,
227};
228
212static void __init smdkv310_map_io(void) 229static void __init smdkv310_map_io(void)
213{ 230{
214 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 231 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -230,6 +247,8 @@ static void __init smdkv310_machine_init(void)
230 247
231 samsung_keypad_set_platdata(&smdkv310_keypad_data); 248 samsung_keypad_set_platdata(&smdkv310_keypad_data);
232 249
250 samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
251
233 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); 252 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
234} 253}
235 254
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index 97d329fff2cf..0e280d12301e 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -18,6 +18,9 @@
18#include <linux/regulator/fixed.h> 18#include <linux/regulator/fixed.h>
19#include <linux/regulator/max8952.h> 19#include <linux/regulator/max8952.h>
20#include <linux/mmc/host.h> 20#include <linux/mmc/host.h>
21#include <linux/i2c-gpio.h>
22#include <linux/i2c/mcs.h>
23#include <linux/i2c/atmel_mxt_ts.h>
21 24
22#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
23#include <asm/mach-types.h> 26#include <asm/mach-types.h>
@@ -27,7 +30,10 @@
27#include <plat/cpu.h> 30#include <plat/cpu.h>
28#include <plat/devs.h> 31#include <plat/devs.h>
29#include <plat/iic.h> 32#include <plat/iic.h>
33#include <plat/gpio-cfg.h>
34#include <plat/mfc.h>
30#include <plat/sdhci.h> 35#include <plat/sdhci.h>
36#include <plat/pd.h>
31 37
32#include <mach/map.h> 38#include <mach/map.h>
33 39
@@ -477,6 +483,96 @@ static struct i2c_board_info i2c5_devs[] __initdata = {
477 }, 483 },
478}; 484};
479 485
486/* I2C3 (TSP) */
487static struct mxt_platform_data qt602240_platform_data = {
488 .x_line = 19,
489 .y_line = 11,
490 .x_size = 800,
491 .y_size = 480,
492 .blen = 0x11,
493 .threshold = 0x28,
494 .voltage = 2800000, /* 2.8V */
495 .orient = MXT_DIAGONAL,
496};
497
498static struct i2c_board_info i2c3_devs[] __initdata = {
499 {
500 I2C_BOARD_INFO("qt602240_ts", 0x4a),
501 .platform_data = &qt602240_platform_data,
502 },
503};
504
505static void __init universal_tsp_init(void)
506{
507 int gpio;
508
509 /* TSP_LDO_ON: XMDMADDR_11 */
510 gpio = EXYNOS4_GPE2(3);
511 gpio_request(gpio, "TSP_LDO_ON");
512 gpio_direction_output(gpio, 1);
513 gpio_export(gpio, 0);
514
515 /* TSP_INT: XMDMADDR_7 */
516 gpio = EXYNOS4_GPE1(7);
517 gpio_request(gpio, "TSP_INT");
518
519 s5p_register_gpio_interrupt(gpio);
520 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
521 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
522 i2c3_devs[0].irq = gpio_to_irq(gpio);
523}
524
525
526/* GPIO I2C 12 (3 Touchkey) */
527static uint32_t touchkey_keymap[] = {
528 /* MCS_KEY_MAP(value, keycode) */
529 MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
530 MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
531};
532
533static struct mcs_platform_data touchkey_data = {
534 .keymap = touchkey_keymap,
535 .keymap_size = ARRAY_SIZE(touchkey_keymap),
536 .key_maxval = 2,
537};
538
539/* GPIO I2C 3_TOUCH 2.8V */
540#define I2C_GPIO_BUS_12 12
541static struct i2c_gpio_platform_data i2c_gpio12_data = {
542 .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
543 .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
544};
545
546static struct platform_device i2c_gpio12 = {
547 .name = "i2c-gpio",
548 .id = I2C_GPIO_BUS_12,
549 .dev = {
550 .platform_data = &i2c_gpio12_data,
551 },
552};
553
554static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
555 {
556 I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
557 .platform_data = &touchkey_data,
558 },
559};
560
561static void __init universal_touchkey_init(void)
562{
563 int gpio;
564
565 gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
566 gpio_request(gpio, "3_TOUCH_INT");
567 s5p_register_gpio_interrupt(gpio);
568 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
569 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
570
571 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
572 gpio_request(gpio, "3_TOUCH_EN");
573 gpio_direction_output(gpio, 1);
574}
575
480/* GPIO KEYS */ 576/* GPIO KEYS */
481static struct gpio_keys_button universal_gpio_keys_tables[] = { 577static struct gpio_keys_button universal_gpio_keys_tables[] = {
482 { 578 {
@@ -608,15 +704,25 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
608 704
609static struct platform_device *universal_devices[] __initdata = { 705static struct platform_device *universal_devices[] __initdata = {
610 /* Samsung Platform Devices */ 706 /* Samsung Platform Devices */
707 &s5p_device_fimc0,
708 &s5p_device_fimc1,
709 &s5p_device_fimc2,
710 &s5p_device_fimc3,
611 &mmc0_fixed_voltage, 711 &mmc0_fixed_voltage,
612 &s3c_device_hsmmc0, 712 &s3c_device_hsmmc0,
613 &s3c_device_hsmmc2, 713 &s3c_device_hsmmc2,
614 &s3c_device_hsmmc3, 714 &s3c_device_hsmmc3,
715 &s3c_device_i2c3,
615 &s3c_device_i2c5, 716 &s3c_device_i2c5,
616 717
617 /* Universal Devices */ 718 /* Universal Devices */
719 &i2c_gpio12,
618 &universal_gpio_keys, 720 &universal_gpio_keys,
619 &s5p_device_onenand, 721 &s5p_device_onenand,
722 &s5p_device_mfc,
723 &s5p_device_mfc_l,
724 &s5p_device_mfc_r,
725 &exynos4_device_pd[PD_MFC],
620}; 726};
621 727
622static void __init universal_map_io(void) 728static void __init universal_map_io(void)
@@ -626,6 +732,11 @@ static void __init universal_map_io(void)
626 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); 732 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
627} 733}
628 734
735static void __init universal_reserve(void)
736{
737 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
738}
739
629static void __init universal_machine_init(void) 740static void __init universal_machine_init(void)
630{ 741{
631 universal_sdhci_init(); 742 universal_sdhci_init();
@@ -633,11 +744,20 @@ static void __init universal_machine_init(void)
633 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); 744 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
634 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); 745 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
635 746
747 universal_tsp_init();
748 s3c_i2c3_set_platdata(NULL);
749 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
750
636 s3c_i2c5_set_platdata(NULL); 751 s3c_i2c5_set_platdata(NULL);
637 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); 752 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
638 753
754 universal_touchkey_init();
755 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
756 ARRAY_SIZE(i2c_gpio12_devs));
757
639 /* Last */ 758 /* Last */
640 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); 759 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
760 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
641} 761}
642 762
643MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") 763MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
@@ -647,4 +767,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
647 .map_io = universal_map_io, 767 .map_io = universal_map_io,
648 .init_machine = universal_machine_init, 768 .init_machine = universal_machine_init,
649 .timer = &exynos4_timer, 769 .timer = &exynos4_timer,
770 .reserve = &universal_reserve,
650MACHINE_END 771MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 14ac10b7ec02..1ae059b7ad7b 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -383,8 +383,8 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
383 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); 383 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
384 } else { 384 } else {
385 mct_tick1_event_irq.dev_id = &mct_tick[cpu]; 385 mct_tick1_event_irq.dev_id = &mct_tick[cpu];
386 irq_set_affinity(IRQ_MCT1, cpumask_of(1));
387 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); 386 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
387 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
388 } 388 }
389} 389}
390 390
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index b68d5bdf04cf..7c2282c6ba81 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -28,9 +28,12 @@
28 28
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h>
31 32
32extern void exynos4_secondary_startup(void); 33extern void exynos4_secondary_startup(void);
33 34
35#define CPU1_BOOT_REG S5P_VA_SYSRAM
36
34/* 37/*
35 * control for which core is the next to come out of the secondary 38 * control for which core is the next to come out of the secondary
36 * boot "holding pen" 39 * boot "holding pen"
@@ -58,6 +61,31 @@ static void __iomem *scu_base_addr(void)
58 61
59static DEFINE_SPINLOCK(boot_lock); 62static DEFINE_SPINLOCK(boot_lock);
60 63
64static void __cpuinit exynos4_gic_secondary_init(void)
65{
66 void __iomem *dist_base = S5P_VA_GIC_DIST +
67 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
68 void __iomem *cpu_base = S5P_VA_GIC_CPU +
69 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
70 int i;
71
72 /*
73 * Deal with the banked PPI and SGI interrupts - disable all
74 * PPI interrupts, ensure all SGI interrupts are enabled.
75 */
76 __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
77 __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
78
79 /*
80 * Set priority on PPI and SGI interrupts
81 */
82 for (i = 0; i < 32; i += 4)
83 __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
84
85 __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
86 __raw_writel(1, cpu_base + GIC_CPU_CTRL);
87}
88
61void __cpuinit platform_secondary_init(unsigned int cpu) 89void __cpuinit platform_secondary_init(unsigned int cpu)
62{ 90{
63 /* 91 /*
@@ -65,7 +93,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
65 * core (e.g. timer irq), then they will not have been enabled 93 * core (e.g. timer irq), then they will not have been enabled
66 * for us: do so 94 * for us: do so
67 */ 95 */
68 gic_secondary_init(0); 96 exynos4_gic_secondary_init();
69 97
70 /* 98 /*
71 * let the primary processor know we're out of the 99 * let the primary processor know we're out of the
@@ -100,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
100 */ 128 */
101 write_pen_release(cpu); 129 write_pen_release(cpu);
102 130
131 if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
132 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
133 S5P_ARM_CORE1_CONFIGURATION);
134
135 timeout = 10;
136
137 /* wait max 10 ms until cpu1 is on */
138 while ((__raw_readl(S5P_ARM_CORE1_STATUS)
139 & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
140 if (timeout-- == 0)
141 break;
142
143 mdelay(1);
144 }
145
146 if (timeout == 0) {
147 printk(KERN_ERR "cpu1 power enable failed");
148 spin_unlock(&boot_lock);
149 return -ETIMEDOUT;
150 }
151 }
103 /* 152 /*
104 * Send the secondary CPU a soft interrupt, thereby causing 153 * Send the secondary CPU a soft interrupt, thereby causing
105 * the boot monitor to read the system wide flags register, 154 * the boot monitor to read the system wide flags register,
106 * and branch to the address found there. 155 * and branch to the address found there.
107 */ 156 */
108 gic_raise_softirq(cpumask_of(cpu), 1);
109 157
110 timeout = jiffies + (1 * HZ); 158 timeout = jiffies + (1 * HZ);
111 while (time_before(jiffies, timeout)) { 159 while (time_before(jiffies, timeout)) {
112 smp_rmb(); 160 smp_rmb();
161
162 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
163 CPU1_BOOT_REG);
164 gic_raise_softirq(cpumask_of(cpu), 1);
165
113 if (pen_release == -1) 166 if (pen_release == -1)
114 break; 167 break;
115 168
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 533c28f758ca..bc6ca9482de1 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -18,92 +18,23 @@
18#include <linux/suspend.h> 18#include <linux/suspend.h>
19#include <linux/syscore_ops.h> 19#include <linux/syscore_ops.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/err.h>
22#include <linux/clk.h>
21 23
22#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
23#include <asm/hardware/cache-l2x0.h> 25#include <asm/hardware/cache-l2x0.h>
24 26
25#include <plat/cpu.h> 27#include <plat/cpu.h>
26#include <plat/pm.h> 28#include <plat/pm.h>
29#include <plat/pll.h>
30#include <plat/regs-srom.h>
27 31
28#include <mach/regs-irq.h> 32#include <mach/regs-irq.h>
29#include <mach/regs-gpio.h> 33#include <mach/regs-gpio.h>
30#include <mach/regs-clock.h> 34#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h> 35#include <mach/regs-pmu.h>
32#include <mach/pm-core.h> 36#include <mach/pm-core.h>
33 37#include <mach/pmu.h>
34static struct sleep_save exynos4_sleep[] = {
35 { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
36 { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
37 { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
38 { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
39 { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
40 { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
41 { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
42 { .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
43 { .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
44 { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
45 { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
46 { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
47 { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
48 { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
49 { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
50 { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
51 { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
52 { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
53 { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
54 { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
55 { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
56 { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
57 { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
58 { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
59 { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
60 { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
61 { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
62 { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
63 { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
64 { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
65 { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
66 { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
67 { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
68 { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
69 { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
70 { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
71 { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
72 { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
73 { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
74 { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
75 { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
76 { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
77 { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
78 { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
79 { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
80 { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
81 { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
82 { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
83 { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
84 { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
85 { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
86 { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
87 { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
88 { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
89 { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
90 { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
91 { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
92 { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
93 { .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
94 { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
95 { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
96 { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
97 { .reg = S5P_CAM_LOWPWR , .val = 0x0, },
98 { .reg = S5P_TV_LOWPWR , .val = 0x0, },
99 { .reg = S5P_MFC_LOWPWR , .val = 0x0, },
100 { .reg = S5P_G3D_LOWPWR , .val = 0x0, },
101 { .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
102 { .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
103 { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
104 { .reg = S5P_GPS_LOWPWR , .val = 0x0, },
105 { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
106};
107 38
108static struct sleep_save exynos4_set_clksrc[] = { 39static struct sleep_save exynos4_set_clksrc[] = {
109 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, 40 { .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
@@ -118,20 +49,28 @@ static struct sleep_save exynos4_set_clksrc[] = {
118 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, 49 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
119}; 50};
120 51
52static struct sleep_save exynos4_epll_save[] = {
53 SAVE_ITEM(S5P_EPLL_CON0),
54 SAVE_ITEM(S5P_EPLL_CON1),
55};
56
57static struct sleep_save exynos4_vpll_save[] = {
58 SAVE_ITEM(S5P_VPLL_CON0),
59 SAVE_ITEM(S5P_VPLL_CON1),
60};
61
121static struct sleep_save exynos4_core_save[] = { 62static struct sleep_save exynos4_core_save[] = {
122 /* CMU side */ 63 /* CMU side */
123 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 64 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
124 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 65 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
125 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), 66 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
126 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), 67 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
127 SAVE_ITEM(S5P_EPLL_CON0),
128 SAVE_ITEM(S5P_EPLL_CON1),
129 SAVE_ITEM(S5P_VPLL_CON0),
130 SAVE_ITEM(S5P_VPLL_CON1),
131 SAVE_ITEM(S5P_CLKSRC_TOP0), 68 SAVE_ITEM(S5P_CLKSRC_TOP0),
132 SAVE_ITEM(S5P_CLKSRC_TOP1), 69 SAVE_ITEM(S5P_CLKSRC_TOP1),
133 SAVE_ITEM(S5P_CLKSRC_CAM), 70 SAVE_ITEM(S5P_CLKSRC_CAM),
71 SAVE_ITEM(S5P_CLKSRC_TV),
134 SAVE_ITEM(S5P_CLKSRC_MFC), 72 SAVE_ITEM(S5P_CLKSRC_MFC),
73 SAVE_ITEM(S5P_CLKSRC_G3D),
135 SAVE_ITEM(S5P_CLKSRC_IMAGE), 74 SAVE_ITEM(S5P_CLKSRC_IMAGE),
136 SAVE_ITEM(S5P_CLKSRC_LCD0), 75 SAVE_ITEM(S5P_CLKSRC_LCD0),
137 SAVE_ITEM(S5P_CLKSRC_LCD1), 76 SAVE_ITEM(S5P_CLKSRC_LCD1),
@@ -158,6 +97,7 @@ static struct sleep_save exynos4_core_save[] = {
158 SAVE_ITEM(S5P_CLKDIV_PERIL4), 97 SAVE_ITEM(S5P_CLKDIV_PERIL4),
159 SAVE_ITEM(S5P_CLKDIV_PERIL5), 98 SAVE_ITEM(S5P_CLKDIV_PERIL5),
160 SAVE_ITEM(S5P_CLKDIV_TOP), 99 SAVE_ITEM(S5P_CLKDIV_TOP),
100 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
161 SAVE_ITEM(S5P_CLKSRC_MASK_CAM), 101 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
162 SAVE_ITEM(S5P_CLKSRC_MASK_TV), 102 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
163 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), 103 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
@@ -166,6 +106,7 @@ static struct sleep_save exynos4_core_save[] = {
166 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), 106 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
167 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), 107 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
168 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), 108 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
109 SAVE_ITEM(S5P_CLKDIV2_RATIO),
169 SAVE_ITEM(S5P_CLKGATE_SCLKCAM), 110 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
170 SAVE_ITEM(S5P_CLKGATE_IP_CAM), 111 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
171 SAVE_ITEM(S5P_CLKGATE_IP_TV), 112 SAVE_ITEM(S5P_CLKGATE_IP_TV),
@@ -186,8 +127,10 @@ static struct sleep_save exynos4_core_save[] = {
186 SAVE_ITEM(S5P_CLKGATE_IP_DMC), 127 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
187 SAVE_ITEM(S5P_CLKSRC_CPU), 128 SAVE_ITEM(S5P_CLKSRC_CPU),
188 SAVE_ITEM(S5P_CLKDIV_CPU), 129 SAVE_ITEM(S5P_CLKDIV_CPU),
130 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
189 SAVE_ITEM(S5P_CLKGATE_SCLKCPU), 131 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
190 SAVE_ITEM(S5P_CLKGATE_IP_CPU), 132 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
133
191 /* GIC side */ 134 /* GIC side */
192 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), 135 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
193 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), 136 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -270,6 +213,13 @@ static struct sleep_save exynos4_core_save[] = {
270 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), 213 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
271 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080), 214 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
272 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090), 215 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
216
217 /* SROM side */
218 SAVE_ITEM(S5P_SROM_BW),
219 SAVE_ITEM(S5P_SROM_BC0),
220 SAVE_ITEM(S5P_SROM_BC1),
221 SAVE_ITEM(S5P_SROM_BC2),
222 SAVE_ITEM(S5P_SROM_BC3),
273}; 223};
274 224
275static struct sleep_save exynos4_l2cc_save[] = { 225static struct sleep_save exynos4_l2cc_save[] = {
@@ -280,37 +230,11 @@ static struct sleep_save exynos4_l2cc_save[] = {
280 SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), 230 SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
281}; 231};
282 232
233/* For Cortex-A9 Diagnostic and Power control register */
234static unsigned int save_arm_register[2];
235
283static int exynos4_cpu_suspend(unsigned long arg) 236static int exynos4_cpu_suspend(unsigned long arg)
284{ 237{
285 unsigned long tmp;
286 unsigned long mask = 0xFFFFFFFF;
287
288 /* Setting Central Sequence Register for power down mode */
289
290 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
291 tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
292 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
293
294 /* Setting Central Sequence option Register */
295
296 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
297 tmp &= ~(S5P_USE_MASK);
298 tmp |= S5P_USE_STANDBY_WFI0;
299 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
300
301 /* Clear all interrupt pending to avoid early wakeup */
302
303 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
304 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
305 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
306
307 /* Disable all interrupt */
308
309 __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
310 __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
311 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
312 __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
313
314 outer_flush_all(); 238 outer_flush_all();
315 239
316 /* issue the standby signal into the pm unit. */ 240 /* issue the standby signal into the pm unit. */
@@ -326,12 +250,14 @@ static void exynos4_pm_prepare(void)
326 250
327 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); 251 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
328 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); 252 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
253 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
254 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
329 255
330 tmp = __raw_readl(S5P_INFORM1); 256 tmp = __raw_readl(S5P_INFORM1);
331 257
332 /* Set value of power down register for sleep mode */ 258 /* Set value of power down register for sleep mode */
333 259
334 s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep)); 260 exynos4_sys_powerdown_conf(SYS_SLEEP);
335 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); 261 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
336 262
337 /* ensure at least INFORM0 has the resume address */ 263 /* ensure at least INFORM0 has the resume address */
@@ -373,12 +299,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
373 flush_cache_all(); 299 flush_cache_all();
374} 300}
375 301
302static unsigned long pll_base_rate;
303
304static void exynos4_restore_pll(void)
305{
306 unsigned long pll_con, locktime, lockcnt;
307 unsigned long pll_in_rate;
308 unsigned int p_div, epll_wait = 0, vpll_wait = 0;
309
310 if (pll_base_rate == 0)
311 return;
312
313 pll_in_rate = pll_base_rate;
314
315 /* EPLL */
316 pll_con = exynos4_epll_save[0].val;
317
318 if (pll_con & (1 << 31)) {
319 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
320 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
321
322 pll_in_rate /= 1000000;
323
324 locktime = (3000 / pll_in_rate) * p_div;
325 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
326
327 __raw_writel(lockcnt, S5P_EPLL_LOCK);
328
329 s3c_pm_do_restore_core(exynos4_epll_save,
330 ARRAY_SIZE(exynos4_epll_save));
331 epll_wait = 1;
332 }
333
334 pll_in_rate = pll_base_rate;
335
336 /* VPLL */
337 pll_con = exynos4_vpll_save[0].val;
338
339 if (pll_con & (1 << 31)) {
340 pll_in_rate /= 1000000;
341 /* 750us */
342 locktime = 750;
343 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
344
345 __raw_writel(lockcnt, S5P_VPLL_LOCK);
346
347 s3c_pm_do_restore_core(exynos4_vpll_save,
348 ARRAY_SIZE(exynos4_vpll_save));
349 vpll_wait = 1;
350 }
351
352 /* Wait PLL locking */
353
354 do {
355 if (epll_wait) {
356 pll_con = __raw_readl(S5P_EPLL_CON0);
357 if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
358 epll_wait = 0;
359 }
360
361 if (vpll_wait) {
362 pll_con = __raw_readl(S5P_VPLL_CON0);
363 if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
364 vpll_wait = 0;
365 }
366 } while (epll_wait || vpll_wait);
367}
368
376static struct sysdev_driver exynos4_pm_driver = { 369static struct sysdev_driver exynos4_pm_driver = {
377 .add = exynos4_pm_add, 370 .add = exynos4_pm_add,
378}; 371};
379 372
380static __init int exynos4_pm_drvinit(void) 373static __init int exynos4_pm_drvinit(void)
381{ 374{
375 struct clk *pll_base;
382 unsigned int tmp; 376 unsigned int tmp;
383 377
384 s3c_pm_init(); 378 s3c_pm_init();
@@ -389,12 +383,69 @@ static __init int exynos4_pm_drvinit(void)
389 tmp |= ((0xFF << 8) | (0x1F << 1)); 383 tmp |= ((0xFF << 8) | (0x1F << 1));
390 __raw_writel(tmp, S5P_WAKEUP_MASK); 384 __raw_writel(tmp, S5P_WAKEUP_MASK);
391 385
386 pll_base = clk_get(NULL, "xtal");
387
388 if (!IS_ERR(pll_base)) {
389 pll_base_rate = clk_get_rate(pll_base);
390 clk_put(pll_base);
391 }
392
392 return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); 393 return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
393} 394}
394arch_initcall(exynos4_pm_drvinit); 395arch_initcall(exynos4_pm_drvinit);
395 396
397static int exynos4_pm_suspend(void)
398{
399 unsigned long tmp;
400
401 /* Setting Central Sequence Register for power down mode */
402
403 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
404 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
405 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
406
407 /* Save Power control register */
408 asm ("mrc p15, 0, %0, c15, c0, 0"
409 : "=r" (tmp) : : "cc");
410 save_arm_register[0] = tmp;
411
412 /* Save Diagnostic register */
413 asm ("mrc p15, 0, %0, c15, c0, 1"
414 : "=r" (tmp) : : "cc");
415 save_arm_register[1] = tmp;
416
417 return 0;
418}
419
396static void exynos4_pm_resume(void) 420static void exynos4_pm_resume(void)
397{ 421{
422 unsigned long tmp;
423
424 /*
425 * If PMU failed while entering sleep mode, WFI will be
426 * ignored by PMU and then exiting cpu_do_idle().
427 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
428 * in this situation.
429 */
430 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
431 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
432 tmp |= S5P_CENTRAL_LOWPWR_CFG;
433 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
434 /* No need to perform below restore code */
435 goto early_wakeup;
436 }
437 /* Restore Power control register */
438 tmp = save_arm_register[0];
439 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
440 : : "r" (tmp)
441 : "cc");
442
443 /* Restore Diagnostic register */
444 tmp = save_arm_register[1];
445 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
446 : : "r" (tmp)
447 : "cc");
448
398 /* For release retention */ 449 /* For release retention */
399 450
400 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); 451 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -407,6 +458,8 @@ static void exynos4_pm_resume(void)
407 458
408 s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); 459 s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
409 460
461 exynos4_restore_pll();
462
410 exynos4_scu_enable(S5P_VA_SCU); 463 exynos4_scu_enable(S5P_VA_SCU);
411 464
412#ifdef CONFIG_CACHE_L2X0 465#ifdef CONFIG_CACHE_L2X0
@@ -415,9 +468,13 @@ static void exynos4_pm_resume(void)
415 /* enable L2X0*/ 468 /* enable L2X0*/
416 writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); 469 writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
417#endif 470#endif
471
472early_wakeup:
473 return;
418} 474}
419 475
420static struct syscore_ops exynos4_pm_syscore_ops = { 476static struct syscore_ops exynos4_pm_syscore_ops = {
477 .suspend = exynos4_pm_suspend,
421 .resume = exynos4_pm_resume, 478 .resume = exynos4_pm_resume,
422}; 479};
423 480
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
new file mode 100644
index 000000000000..7ea9eb2a20d2
--- /dev/null
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -0,0 +1,175 @@
1/* linux/arch/arm/mach-exynos4/pmu.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4210 - CPU PMU(Power Management Unit) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/io.h>
14#include <linux/kernel.h>
15
16#include <mach/regs-clock.h>
17#include <mach/pmu.h>
18
19static void __iomem *sys_powerdown_reg[] = {
20 S5P_ARM_CORE0_LOWPWR,
21 S5P_DIS_IRQ_CORE0,
22 S5P_DIS_IRQ_CENTRAL0,
23 S5P_ARM_CORE1_LOWPWR,
24 S5P_DIS_IRQ_CORE1,
25 S5P_DIS_IRQ_CENTRAL1,
26 S5P_ARM_COMMON_LOWPWR,
27 S5P_L2_0_LOWPWR,
28 S5P_L2_1_LOWPWR,
29 S5P_CMU_ACLKSTOP_LOWPWR,
30 S5P_CMU_SCLKSTOP_LOWPWR,
31 S5P_CMU_RESET_LOWPWR,
32 S5P_APLL_SYSCLK_LOWPWR,
33 S5P_MPLL_SYSCLK_LOWPWR,
34 S5P_VPLL_SYSCLK_LOWPWR,
35 S5P_EPLL_SYSCLK_LOWPWR,
36 S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
37 S5P_CMU_RESET_GPSALIVE_LOWPWR,
38 S5P_CMU_CLKSTOP_CAM_LOWPWR,
39 S5P_CMU_CLKSTOP_TV_LOWPWR,
40 S5P_CMU_CLKSTOP_MFC_LOWPWR,
41 S5P_CMU_CLKSTOP_G3D_LOWPWR,
42 S5P_CMU_CLKSTOP_LCD0_LOWPWR,
43 S5P_CMU_CLKSTOP_LCD1_LOWPWR,
44 S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
45 S5P_CMU_CLKSTOP_GPS_LOWPWR,
46 S5P_CMU_RESET_CAM_LOWPWR,
47 S5P_CMU_RESET_TV_LOWPWR,
48 S5P_CMU_RESET_MFC_LOWPWR,
49 S5P_CMU_RESET_G3D_LOWPWR,
50 S5P_CMU_RESET_LCD0_LOWPWR,
51 S5P_CMU_RESET_LCD1_LOWPWR,
52 S5P_CMU_RESET_MAUDIO_LOWPWR,
53 S5P_CMU_RESET_GPS_LOWPWR,
54 S5P_TOP_BUS_LOWPWR,
55 S5P_TOP_RETENTION_LOWPWR,
56 S5P_TOP_PWR_LOWPWR,
57 S5P_LOGIC_RESET_LOWPWR,
58 S5P_ONENAND_MEM_LOWPWR,
59 S5P_MODIMIF_MEM_LOWPWR,
60 S5P_G2D_ACP_MEM_LOWPWR,
61 S5P_USBOTG_MEM_LOWPWR,
62 S5P_HSMMC_MEM_LOWPWR,
63 S5P_CSSYS_MEM_LOWPWR,
64 S5P_SECSS_MEM_LOWPWR,
65 S5P_PCIE_MEM_LOWPWR,
66 S5P_SATA_MEM_LOWPWR,
67 S5P_PAD_RETENTION_DRAM_LOWPWR,
68 S5P_PAD_RETENTION_MAUDIO_LOWPWR,
69 S5P_PAD_RETENTION_GPIO_LOWPWR,
70 S5P_PAD_RETENTION_UART_LOWPWR,
71 S5P_PAD_RETENTION_MMCA_LOWPWR,
72 S5P_PAD_RETENTION_MMCB_LOWPWR,
73 S5P_PAD_RETENTION_EBIA_LOWPWR,
74 S5P_PAD_RETENTION_EBIB_LOWPWR,
75 S5P_PAD_RETENTION_ISOLATION_LOWPWR,
76 S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
77 S5P_XUSBXTI_LOWPWR,
78 S5P_XXTI_LOWPWR,
79 S5P_EXT_REGULATOR_LOWPWR,
80 S5P_GPIO_MODE_LOWPWR,
81 S5P_GPIO_MODE_MAUDIO_LOWPWR,
82 S5P_CAM_LOWPWR,
83 S5P_TV_LOWPWR,
84 S5P_MFC_LOWPWR,
85 S5P_G3D_LOWPWR,
86 S5P_LCD0_LOWPWR,
87 S5P_LCD1_LOWPWR,
88 S5P_MAUDIO_LOWPWR,
89 S5P_GPS_LOWPWR,
90 S5P_GPS_ALIVE_LOWPWR,
91};
92
93static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
94 /* { AFTR, LPA, SLEEP }*/
95 { 0, 0, 2 }, /* ARM_CORE0 */
96 { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
97 { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
98 { 0, 0, 2 }, /* ARM_CORE1 */
99 { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
100 { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
101 { 0, 0, 2 }, /* ARM_COMMON */
102 { 2, 2, 3 }, /* ARM_CPU_L2_0 */
103 { 2, 2, 3 }, /* ARM_CPU_L2_1 */
104 { 1, 0, 0 }, /* CMU_ACLKSTOP */
105 { 1, 0, 0 }, /* CMU_SCLKSTOP */
106 { 1, 1, 0 }, /* CMU_RESET */
107 { 1, 0, 0 }, /* APLL_SYSCLK */
108 { 1, 0, 0 }, /* MPLL_SYSCLK */
109 { 1, 0, 0 }, /* VPLL_SYSCLK */
110 { 1, 1, 0 }, /* EPLL_SYSCLK */
111 { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
112 { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
113 { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
114 { 1, 1, 0 }, /* CMU_CLKSTOP_TV */
115 { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
116 { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
117 { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
118 { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
119 { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
120 { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
121 { 1, 1, 0 }, /* CMU_RESET_CAM */
122 { 1, 1, 0 }, /* CMU_RESET_TV */
123 { 1, 1, 0 }, /* CMU_RESET_MFC */
124 { 1, 1, 0 }, /* CMU_RESET_G3D */
125 { 1, 1, 0 }, /* CMU_RESET_LCD0 */
126 { 1, 1, 0 }, /* CMU_RESET_LCD1 */
127 { 1, 1, 0 }, /* CMU_RESET_MAUDIO */
128 { 1, 1, 0 }, /* CMU_RESET_GPS */
129 { 3, 0, 0 }, /* TOP_BUS */
130 { 1, 0, 1 }, /* TOP_RETENTION */
131 { 3, 0, 3 }, /* TOP_PWR */
132 { 1, 1, 0 }, /* LOGIC_RESET */
133 { 3, 0, 0 }, /* ONENAND_MEM */
134 { 3, 0, 0 }, /* MODIMIF_MEM */
135 { 3, 0, 0 }, /* G2D_ACP_MEM */
136 { 3, 0, 0 }, /* USBOTG_MEM */
137 { 3, 0, 0 }, /* HSMMC_MEM */
138 { 3, 0, 0 }, /* CSSYS_MEM */
139 { 3, 0, 0 }, /* SECSS_MEM */
140 { 3, 0, 0 }, /* PCIE_MEM */
141 { 3, 0, 0 }, /* SATA_MEM */
142 { 1, 0, 0 }, /* PAD_RETENTION_DRAM */
143 { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
144 { 1, 0, 0 }, /* PAD_RETENTION_GPIO */
145 { 1, 0, 0 }, /* PAD_RETENTION_UART */
146 { 1, 0, 0 }, /* PAD_RETENTION_MMCA */
147 { 1, 0, 0 }, /* PAD_RETENTION_MMCB */
148 { 1, 0, 0 }, /* PAD_RETENTION_EBIA */
149 { 1, 0, 0 }, /* PAD_RETENTION_EBIB */
150 { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
151 { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
152 { 1, 1, 0 }, /* XUSBXTI */
153 { 1, 1, 0 }, /* XXTI */
154 { 1, 1, 0 }, /* EXT_REGULATOR */
155 { 1, 0, 0 }, /* GPIO_MODE */
156 { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
157 { 7, 0, 0 }, /* CAM */
158 { 7, 0, 0 }, /* TV */
159 { 7, 0, 0 }, /* MFC */
160 { 7, 0, 0 }, /* G3D */
161 { 7, 0, 0 }, /* LCD0 */
162 { 7, 0, 0 }, /* LCD1 */
163 { 7, 7, 0 }, /* MAUDIO */
164 { 7, 0, 0 }, /* GPS */
165 { 7, 0, 0 }, /* GPS_ALIVE */
166};
167
168void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
169{
170 unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
171
172 for (; count > 0; count--)
173 __raw_writel(sys_powerdown_val[count - 1][mode],
174 sys_powerdown_reg[count - 1]);
175}
diff --git a/arch/arm/mach-exynos4/setup-fimd0.c b/arch/arm/mach-exynos4/setup-fimd0.c
new file mode 100644
index 000000000000..07a6dbeecdd0
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-fimd0.c
@@ -0,0 +1,43 @@
1/* linux/arch/arm/mach-exynos4/setup-fimd0.c
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Base Exynos4 FIMD 0 configuration
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/fb.h>
14#include <linux/gpio.h>
15
16#include <plat/gpio-cfg.h>
17#include <plat/regs-fb-v4.h>
18
19#include <mach/map.h>
20
21void exynos4_fimd0_gpio_setup_24bpp(void)
22{
23 unsigned int reg;
24
25 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
26 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
27 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
28 s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
29
30 /*
31 * Set DISPLAY_CONTROL register for Display path selection.
32 *
33 * DISPLAY_CONTROL[1:0]
34 * ---------------------
35 * 00 | MIE
36 * 01 | MDINE
37 * 10 | FIMD : selected
38 * 11 | FIMD
39 */
40 reg = __raw_readl(S3C_VA_SYS + 0x0210);
41 reg |= (1 << 1);
42 __raw_writel(reg, S3C_VA_SYS + 0x0210);
43}
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
deleted file mode 100644
index ebb8f38d5405..000000000000
--- a/arch/arm/mach-exynos4/time.c
+++ /dev/null
@@ -1,301 +0,0 @@
1/* linux/arch/arm/mach-exynos4/time.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 (and compatible) HRT support
7 * PWM 2/4 is used for this feature
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/clockchips.h>
20#include <linux/platform_device.h>
21
22#include <asm/smp_twd.h>
23
24#include <mach/map.h>
25#include <plat/regs-timer.h>
26#include <asm/mach/time.h>
27
28static unsigned long clock_count_per_tick;
29
30static struct clk *tin2;
31static struct clk *tin4;
32static struct clk *tdiv2;
33static struct clk *tdiv4;
34static struct clk *timerclk;
35
36static void exynos4_pwm_stop(unsigned int pwm_id)
37{
38 unsigned long tcon;
39
40 tcon = __raw_readl(S3C2410_TCON);
41
42 switch (pwm_id) {
43 case 2:
44 tcon &= ~S3C2410_TCON_T2START;
45 break;
46 case 4:
47 tcon &= ~S3C2410_TCON_T4START;
48 break;
49 default:
50 break;
51 }
52 __raw_writel(tcon, S3C2410_TCON);
53}
54
55static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
56{
57 unsigned long tcon;
58
59 tcon = __raw_readl(S3C2410_TCON);
60
61 /* timers reload after counting zero, so reduce the count by 1 */
62 tcnt--;
63
64 /* ensure timer is stopped... */
65 switch (pwm_id) {
66 case 2:
67 tcon &= ~(0xf<<12);
68 tcon |= S3C2410_TCON_T2MANUALUPD;
69
70 __raw_writel(tcnt, S3C2410_TCNTB(2));
71 __raw_writel(tcnt, S3C2410_TCMPB(2));
72 __raw_writel(tcon, S3C2410_TCON);
73
74 break;
75 case 4:
76 tcon &= ~(7<<20);
77 tcon |= S3C2410_TCON_T4MANUALUPD;
78
79 __raw_writel(tcnt, S3C2410_TCNTB(4));
80 __raw_writel(tcnt, S3C2410_TCMPB(4));
81 __raw_writel(tcon, S3C2410_TCON);
82
83 break;
84 default:
85 break;
86 }
87}
88
89static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
90{
91 unsigned long tcon;
92
93 tcon = __raw_readl(S3C2410_TCON);
94
95 switch (pwm_id) {
96 case 2:
97 tcon |= S3C2410_TCON_T2START;
98 tcon &= ~S3C2410_TCON_T2MANUALUPD;
99
100 if (periodic)
101 tcon |= S3C2410_TCON_T2RELOAD;
102 else
103 tcon &= ~S3C2410_TCON_T2RELOAD;
104 break;
105 case 4:
106 tcon |= S3C2410_TCON_T4START;
107 tcon &= ~S3C2410_TCON_T4MANUALUPD;
108
109 if (periodic)
110 tcon |= S3C2410_TCON_T4RELOAD;
111 else
112 tcon &= ~S3C2410_TCON_T4RELOAD;
113 break;
114 default:
115 break;
116 }
117 __raw_writel(tcon, S3C2410_TCON);
118}
119
120static int exynos4_pwm_set_next_event(unsigned long cycles,
121 struct clock_event_device *evt)
122{
123 exynos4_pwm_init(2, cycles);
124 exynos4_pwm_start(2, 0);
125 return 0;
126}
127
128static void exynos4_pwm_set_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt)
130{
131 exynos4_pwm_stop(2);
132
133 switch (mode) {
134 case CLOCK_EVT_MODE_PERIODIC:
135 exynos4_pwm_init(2, clock_count_per_tick);
136 exynos4_pwm_start(2, 1);
137 break;
138 case CLOCK_EVT_MODE_ONESHOT:
139 break;
140 case CLOCK_EVT_MODE_UNUSED:
141 case CLOCK_EVT_MODE_SHUTDOWN:
142 case CLOCK_EVT_MODE_RESUME:
143 break;
144 }
145}
146
147static struct clock_event_device pwm_event_device = {
148 .name = "pwm_timer2",
149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
150 .rating = 200,
151 .shift = 32,
152 .set_next_event = exynos4_pwm_set_next_event,
153 .set_mode = exynos4_pwm_set_mode,
154};
155
156irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
157{
158 struct clock_event_device *evt = &pwm_event_device;
159
160 evt->event_handler(evt);
161
162 return IRQ_HANDLED;
163}
164
165static struct irqaction exynos4_clock_event_irq = {
166 .name = "pwm_timer2_irq",
167 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
168 .handler = exynos4_clock_event_isr,
169};
170
171static void __init exynos4_clockevent_init(void)
172{
173 unsigned long pclk;
174 unsigned long clock_rate;
175 struct clk *tscaler;
176
177 pclk = clk_get_rate(timerclk);
178
179 /* configure clock tick */
180
181 tscaler = clk_get_parent(tdiv2);
182
183 clk_set_rate(tscaler, pclk / 2);
184 clk_set_rate(tdiv2, pclk / 2);
185 clk_set_parent(tin2, tdiv2);
186
187 clock_rate = clk_get_rate(tin2);
188
189 clock_count_per_tick = clock_rate / HZ;
190
191 pwm_event_device.mult =
192 div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
193 pwm_event_device.max_delta_ns =
194 clockevent_delta2ns(-1, &pwm_event_device);
195 pwm_event_device.min_delta_ns =
196 clockevent_delta2ns(1, &pwm_event_device);
197
198 pwm_event_device.cpumask = cpumask_of(0);
199 clockevents_register_device(&pwm_event_device);
200
201 setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
202}
203
204static cycle_t exynos4_pwm4_read(struct clocksource *cs)
205{
206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
207}
208
209#ifdef CONFIG_PM
210static void exynos4_pwm4_resume(struct clocksource *cs)
211{
212 unsigned long pclk;
213
214 pclk = clk_get_rate(timerclk);
215
216 clk_set_rate(tdiv4, pclk / 2);
217 clk_set_parent(tin4, tdiv4);
218
219 exynos4_pwm_init(4, ~0);
220 exynos4_pwm_start(4, 1);
221}
222#endif
223
224struct clocksource pwm_clocksource = {
225 .name = "pwm_timer4",
226 .rating = 250,
227 .read = exynos4_pwm4_read,
228 .mask = CLOCKSOURCE_MASK(32),
229 .flags = CLOCK_SOURCE_IS_CONTINUOUS ,
230#ifdef CONFIG_PM
231 .resume = exynos4_pwm4_resume,
232#endif
233};
234
235static void __init exynos4_clocksource_init(void)
236{
237 unsigned long pclk;
238 unsigned long clock_rate;
239
240 pclk = clk_get_rate(timerclk);
241
242 clk_set_rate(tdiv4, pclk / 2);
243 clk_set_parent(tin4, tdiv4);
244
245 clock_rate = clk_get_rate(tin4);
246
247 exynos4_pwm_init(4, ~0);
248 exynos4_pwm_start(4, 1);
249
250 if (clocksource_register_hz(&pwm_clocksource, clock_rate))
251 panic("%s: can't register clocksource\n", pwm_clocksource.name);
252}
253
254static void __init exynos4_timer_resources(void)
255{
256 struct platform_device tmpdev;
257
258 tmpdev.dev.bus = &platform_bus_type;
259
260 timerclk = clk_get(NULL, "timers");
261 if (IS_ERR(timerclk))
262 panic("failed to get timers clock for system timer");
263
264 clk_enable(timerclk);
265
266 tmpdev.id = 2;
267 tin2 = clk_get(&tmpdev.dev, "pwm-tin");
268 if (IS_ERR(tin2))
269 panic("failed to get pwm-tin2 clock for system timer");
270
271 tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
272 if (IS_ERR(tdiv2))
273 panic("failed to get pwm-tdiv2 clock for system timer");
274 clk_enable(tin2);
275
276 tmpdev.id = 4;
277 tin4 = clk_get(&tmpdev.dev, "pwm-tin");
278 if (IS_ERR(tin4))
279 panic("failed to get pwm-tin4 clock for system timer");
280
281 tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
282 if (IS_ERR(tdiv4))
283 panic("failed to get pwm-tdiv4 clock for system timer");
284
285 clk_enable(tin4);
286}
287
288static void __init exynos4_timer_init(void)
289{
290#ifdef CONFIG_LOCAL_TIMERS
291 twd_base = S5P_VA_TWD;
292#endif
293
294 exynos4_timer_resources();
295 exynos4_clockevent_init();
296 exynos4_clocksource_init();
297}
298
299struct sys_timer exynos4_timer = {
300 .init = exynos4_timer_init,
301};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-06 18:31:17 -0500