1 files changed, 165 insertions, 108 deletions

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 533c28f758ca..bc6ca9482de1 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -18,92 +18,23 @@
 #include <linux/suspend.h>
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/pll.h>
+#include <plat/regs-srom.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pm-core.h>
-
-static struct sleep_save exynos4_sleep[] = {
-        { .reg = S5P_ARM_CORE0_LOWPWR                   , .val = 0x2, },
-        { .reg = S5P_DIS_IRQ_CORE0                      , .val = 0x0, },
-        { .reg = S5P_DIS_IRQ_CENTRAL0                   , .val = 0x0, },
-        { .reg = S5P_ARM_CORE1_LOWPWR                   , .val = 0x2, },
-        { .reg = S5P_DIS_IRQ_CORE1                      , .val = 0x0, },
-        { .reg = S5P_DIS_IRQ_CENTRAL1                   , .val = 0x0, },
-        { .reg = S5P_ARM_COMMON_LOWPWR                  , .val = 0x2, },
-        { .reg = S5P_L2_0_LOWPWR                        , .val = 0x3, },
-        { .reg = S5P_L2_1_LOWPWR                        , .val = 0x3, },
-        { .reg = S5P_CMU_ACLKSTOP_LOWPWR                , .val = 0x0, },
-        { .reg = S5P_CMU_SCLKSTOP_LOWPWR                , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_APLL_SYSCLK_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_MPLL_SYSCLK_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_VPLL_SYSCLK_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_EPLL_SYSCLK_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR       , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR             , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR              , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR             , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR             , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR            , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR            , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR             , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_CAM_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_TV_LOWPWR                , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_MFC_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_G3D_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_LCD0_LOWPWR              , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_LCD1_LOWPWR              , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR            , .val = 0x0, },
-        { .reg = S5P_CMU_RESET_GPS_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_TOP_BUS_LOWPWR                     , .val = 0x0, },
-        { .reg = S5P_TOP_RETENTION_LOWPWR               , .val = 0x1, },
-        { .reg = S5P_TOP_PWR_LOWPWR                     , .val = 0x3, },
-        { .reg = S5P_LOGIC_RESET_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_ONENAND_MEM_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_MODIMIF_MEM_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_G2D_ACP_MEM_LOWPWR                 , .val = 0x0, },
-        { .reg = S5P_USBOTG_MEM_LOWPWR                  , .val = 0x0, },
-        { .reg = S5P_HSMMC_MEM_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_CSSYS_MEM_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_SECSS_MEM_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_PCIE_MEM_LOWPWR                    , .val = 0x0, },
-        { .reg = S5P_SATA_MEM_LOWPWR                    , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR        , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_UART_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR          , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR     , .val = 0x0, },
-        { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR       , .val = 0x0, },
-        { .reg = S5P_XUSBXTI_LOWPWR                     , .val = 0x0, },
-        { .reg = S5P_XXTI_LOWPWR                        , .val = 0x0, },
-        { .reg = S5P_EXT_REGULATOR_LOWPWR               , .val = 0x0, },
-        { .reg = S5P_GPIO_MODE_LOWPWR                   , .val = 0x0, },
-        { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR            , .val = 0x0, },
-        { .reg = S5P_CAM_LOWPWR                         , .val = 0x0, },
-        { .reg = S5P_TV_LOWPWR                          , .val = 0x0, },
-        { .reg = S5P_MFC_LOWPWR                         , .val = 0x0, },
-        { .reg = S5P_G3D_LOWPWR                         , .val = 0x0, },
-        { .reg = S5P_LCD0_LOWPWR                        , .val = 0x0, },
-        { .reg = S5P_LCD1_LOWPWR                        , .val = 0x0, },
-        { .reg = S5P_MAUDIO_LOWPWR                      , .val = 0x0, },
-        { .reg = S5P_GPS_LOWPWR                         , .val = 0x0, },
-        { .reg = S5P_GPS_ALIVE_LOWPWR                   , .val = 0x0, },
-};
+#include <mach/pmu.h>
 
 static struct sleep_save exynos4_set_clksrc[] = {
         { .reg = S5P_CLKSRC_MASK_TOP                    , .val = 0x00000001, },
@@ -118,20 +49,28 @@ static struct sleep_save exynos4_set_clksrc[] = {
         { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
 };
 
+static struct sleep_save exynos4_epll_save[] = {
+        SAVE_ITEM(S5P_EPLL_CON0),
+        SAVE_ITEM(S5P_EPLL_CON1),
+};
+
+static struct sleep_save exynos4_vpll_save[] = {
+        SAVE_ITEM(S5P_VPLL_CON0),
+        SAVE_ITEM(S5P_VPLL_CON1),
+};
+
 static struct sleep_save exynos4_core_save[] = {
         /* CMU side */
         SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
         SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
         SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
         SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(S5P_EPLL_CON0),
-        SAVE_ITEM(S5P_EPLL_CON1),
-        SAVE_ITEM(S5P_VPLL_CON0),
-        SAVE_ITEM(S5P_VPLL_CON1),
         SAVE_ITEM(S5P_CLKSRC_TOP0),
         SAVE_ITEM(S5P_CLKSRC_TOP1),
         SAVE_ITEM(S5P_CLKSRC_CAM),
+        SAVE_ITEM(S5P_CLKSRC_TV),
         SAVE_ITEM(S5P_CLKSRC_MFC),
+        SAVE_ITEM(S5P_CLKSRC_G3D),
         SAVE_ITEM(S5P_CLKSRC_IMAGE),
         SAVE_ITEM(S5P_CLKSRC_LCD0),
         SAVE_ITEM(S5P_CLKSRC_LCD1),
@@ -158,6 +97,7 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_CLKDIV_PERIL4),
         SAVE_ITEM(S5P_CLKDIV_PERIL5),
         SAVE_ITEM(S5P_CLKDIV_TOP),
+        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
         SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
         SAVE_ITEM(S5P_CLKSRC_MASK_TV),
         SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
@@ -166,6 +106,7 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV2_RATIO),
         SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
         SAVE_ITEM(S5P_CLKGATE_IP_CAM),
         SAVE_ITEM(S5P_CLKGATE_IP_TV),
@@ -186,8 +127,10 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_CLKGATE_IP_DMC),
         SAVE_ITEM(S5P_CLKSRC_CPU),
         SAVE_ITEM(S5P_CLKDIV_CPU),
+        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
         SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
         SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+
         /* GIC side */
         SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
         SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -270,6 +213,13 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
         SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
         SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
+
+        /* SROM side */
+        SAVE_ITEM(S5P_SROM_BW),
+        SAVE_ITEM(S5P_SROM_BC0),
+        SAVE_ITEM(S5P_SROM_BC1),
+        SAVE_ITEM(S5P_SROM_BC2),
+        SAVE_ITEM(S5P_SROM_BC3),
 };
 
 static struct sleep_save exynos4_l2cc_save[] = {
@@ -280,37 +230,11 @@ static struct sleep_save exynos4_l2cc_save[] = {
         SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
 };
 
+/* For Cortex-A9 Diagnostic and Power control register */
+static unsigned int save_arm_register[2];
+
 static int exynos4_cpu_suspend(unsigned long arg)
 {
-        unsigned long tmp;
-        unsigned long mask = 0xFFFFFFFF;
-
-        /* Setting Central Sequence Register for power down mode */
-
-        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-        tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
-        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
-        /* Setting Central Sequence option Register */
-
-        tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
-        tmp &= ~(S5P_USE_MASK);
-        tmp |= S5P_USE_STANDBY_WFI0;
-        __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-
-        /* Clear all interrupt pending to avoid early wakeup */
-
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
-
-        /* Disable all interrupt */
-
-        __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
-        __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
-        __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
-
         outer_flush_all();
 
         /* issue the standby signal into the pm unit. */
@@ -326,12 +250,14 @@ static void exynos4_pm_prepare(void)
 
         s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
         s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+        s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+        s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 
         tmp = __raw_readl(S5P_INFORM1);
 
         /* Set value of power down register for sleep mode */
 
-        s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
+        exynos4_sys_powerdown_conf(SYS_SLEEP);
         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 
         /* ensure at least INFORM0 has the resume address */
@@ -373,12 +299,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
         flush_cache_all();
 }
 
+static unsigned long pll_base_rate;
+
+static void exynos4_restore_pll(void)
+{
+        unsigned long pll_con, locktime, lockcnt;
+        unsigned long pll_in_rate;
+        unsigned int p_div, epll_wait = 0, vpll_wait = 0;
+
+        if (pll_base_rate == 0)
+                return;
+
+        pll_in_rate = pll_base_rate;
+
+        /* EPLL */
+        pll_con = exynos4_epll_save[0].val;
+
+        if (pll_con & (1 << 31)) {
+                pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
+                p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
+
+                pll_in_rate /= 1000000;
+
+                locktime = (3000 / pll_in_rate) * p_div;
+                lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+                __raw_writel(lockcnt, S5P_EPLL_LOCK);
+
+                s3c_pm_do_restore_core(exynos4_epll_save,
+                                        ARRAY_SIZE(exynos4_epll_save));
+                epll_wait = 1;
+        }
+
+        pll_in_rate = pll_base_rate;
+
+        /* VPLL */
+        pll_con = exynos4_vpll_save[0].val;
+
+        if (pll_con & (1 << 31)) {
+                pll_in_rate /= 1000000;
+                /* 750us */
+                locktime = 750;
+                lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+                __raw_writel(lockcnt, S5P_VPLL_LOCK);
+
+                s3c_pm_do_restore_core(exynos4_vpll_save,
+                                        ARRAY_SIZE(exynos4_vpll_save));
+                vpll_wait = 1;
+        }
+
+        /* Wait PLL locking */
+
+        do {
+                if (epll_wait) {
+                        pll_con = __raw_readl(S5P_EPLL_CON0);
+                        if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+                                epll_wait = 0;
+                }
+
+                if (vpll_wait) {
+                        pll_con = __raw_readl(S5P_VPLL_CON0);
+                        if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+                                vpll_wait = 0;
+                }
+        } while (epll_wait || vpll_wait);
+}
+
 static struct sysdev_driver exynos4_pm_driver = {
         .add            = exynos4_pm_add,
 };
 
 static __init int exynos4_pm_drvinit(void)
 {
+        struct clk *pll_base;
         unsigned int tmp;
 
         s3c_pm_init();
@@ -389,12 +383,69 @@ static __init int exynos4_pm_drvinit(void)
         tmp |= ((0xFF << 8) | (0x1F << 1));
         __raw_writel(tmp, S5P_WAKEUP_MASK);
 
+        pll_base = clk_get(NULL, "xtal");
+
+        if (!IS_ERR(pll_base)) {
+                pll_base_rate = clk_get_rate(pll_base);
+                clk_put(pll_base);
+        }
+
         return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
 }
 arch_initcall(exynos4_pm_drvinit);
 
+static int exynos4_pm_suspend(void)
+{
+        unsigned long tmp;
+
+        /* Setting Central Sequence Register for power down mode */
+
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
+        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+        /* Save Power control register */
+        asm ("mrc p15, 0, %0, c15, c0, 0"
+             : "=r" (tmp) : : "cc");
+        save_arm_register[0] = tmp;
+
+        /* Save Diagnostic register */
+        asm ("mrc p15, 0, %0, c15, c0, 1"
+             : "=r" (tmp) : : "cc");
+        save_arm_register[1] = tmp;
+
+        return 0;
+}
+
 static void exynos4_pm_resume(void)
 {
+        unsigned long tmp;
+
+        /*
+         * If PMU failed while entering sleep mode, WFI will be
+         * ignored by PMU and then exiting cpu_do_idle().
+         * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+         * in this situation.
+         */
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+                tmp |= S5P_CENTRAL_LOWPWR_CFG;
+                __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+                /* No need to perform below restore code */
+                goto early_wakeup;
+        }
+        /* Restore Power control register */
+        tmp = save_arm_register[0];
+        asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+                      : : "r" (tmp)
+                      : "cc");
+
+        /* Restore Diagnostic register */
+        tmp = save_arm_register[1];
+        asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+                      : : "r" (tmp)
+                      : "cc");
+
         /* For release retention */
 
         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -407,6 +458,8 @@ static void exynos4_pm_resume(void)
 
         s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
 
+        exynos4_restore_pll();
+
         exynos4_scu_enable(S5P_VA_SCU);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -415,9 +468,13 @@ static void exynos4_pm_resume(void)
         /* enable L2X0*/
         writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
 #endif
+
+early_wakeup:
+        return;
 }
 
 static struct syscore_ops exynos4_pm_syscore_ops = {
+        .suspend        = exynos4_pm_suspend,
         .resume         = exynos4_pm_resume,
 };