1 files changed, 95 insertions, 70 deletions

diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 582b874aab0e..f191608b28d6 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -20,19 +20,31 @@
 #include <linux/delay.h>
 #include <linux/percpu.h>
 
+#include <asm/hardware/gic.h>
+
+#include <plat/cpu.h>
+
 #include <mach/map.h>
+#include <mach/irqs.h>
 #include <mach/regs-mct.h>
 #include <asm/mach/time.h>
 
+enum {
+        MCT_INT_SPI,
+        MCT_INT_PPI
+};
+
 static unsigned long clk_cnt_per_tick;
 static unsigned long clk_rate;
+static unsigned int mct_int_type;
 
 struct mct_clock_event_device {
         struct clock_event_device *evt;
         void __iomem *base;
+        char name[10];
 };
 
-struct mct_clock_event_device mct_tick[2];
+struct mct_clock_event_device mct_tick[NR_CPUS];
 
 static void exynos4_mct_write(unsigned int value, void *addr)
 {
@@ -42,57 +54,53 @@ static void exynos4_mct_write(unsigned int value, void *addr)
 
         __raw_writel(value, addr);
 
-        switch ((u32) addr) {
-        case (u32) EXYNOS4_MCT_G_TCON:
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
-                mask = 1 << 16;         /* G_TCON write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_COMP0_L:
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
-                mask = 1 << 0;          /* G_COMP0_L write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_COMP0_U:
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
-                mask = 1 << 1;          /* G_COMP0_U write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
-                mask = 1 << 2;          /* G_COMP0_ADD_INCR write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_CNT_L:
-                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                mask = 1 << 0;          /* G_CNT_L write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_CNT_U:
-                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                mask = 1 << 1;          /* G_CNT_U write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
-                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 3;          /* L0_TCON write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
-                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 3;          /* L1_TCON write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
-                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 0;          /* L0_TCNTB write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
-                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 0;          /* L1_TCNTB write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
-                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 1;          /* L0_ICNTB write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
-                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 1;          /* L1_ICNTB write status */
-                break;
-        default:
-                return;
+        if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
+                u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
+                switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
+                case (u32) MCT_L_TCON_OFFSET:
+                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 3;          /* L_TCON write status */
+                        break;
+                case (u32) MCT_L_ICNTB_OFFSET:
+                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 1;          /* L_ICNTB write status */
+                        break;
+                case (u32) MCT_L_TCNTB_OFFSET:
+                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 0;          /* L_TCNTB write status */
+                        break;
+                default:
+                        return;
+                }
+        } else {
+                switch ((u32) addr) {
+                case (u32) EXYNOS4_MCT_G_TCON:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 16;         /* G_TCON write status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_COMP0_L:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 0;          /* G_COMP0_L write status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_COMP0_U:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 1;          /* G_COMP0_U write status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_CNT_L:
+                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                        mask = 1 << 0;          /* G_CNT_L write status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_CNT_U:
+                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                        mask = 1 << 1;          /* G_CNT_U write status */
+                        break;
+                default:
+                        return;
+                }
         }
 
         /* Wait maximum 1 ms until written values are applied */
@@ -321,9 +329,8 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
         }
 }
 
-static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 {
-        struct mct_clock_event_device *mevt = dev_id;
         struct clock_event_device *evt = mevt->evt;
 
         /*
@@ -335,7 +342,20 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
                 exynos4_mct_tick_stop(mevt);
 
         /* Clear the MCT tick interrupt */
-        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+        if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+                exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+                return 1;
+        } else {
+                return 0;
+        }
+}
+
+static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+{
+        struct mct_clock_event_device *mevt = dev_id;
+        struct clock_event_device *evt = mevt->evt;
+
+        exynos4_mct_tick_clear(mevt);
 
         evt->event_handler(evt);
 
@@ -360,14 +380,10 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 
         mct_tick[cpu].evt = evt;
 
-        if (cpu == 0) {
-                mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
-                evt->name = "mct_tick0";
-        } else {
-                mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
-                evt->name = "mct_tick1";
-        }
+        mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu);
+        sprintf(mct_tick[cpu].name, "mct_tick%d", cpu);
 
+        evt->name = mct_tick[cpu].name;
         evt->cpumask = cpumask_of(cpu);
         evt->set_next_event = exynos4_tick_set_next_event;
         evt->set_mode = exynos4_tick_set_mode;
@@ -384,15 +400,19 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 
         exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
 
-        if (cpu == 0) {
-                mct_tick0_event_irq.dev_id = &mct_tick[cpu];
-                evt->irq = IRQ_MCT_L0;
-                setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+        if (mct_int_type == MCT_INT_SPI) {
+                if (cpu == 0) {
+                        mct_tick0_event_irq.dev_id = &mct_tick[cpu];
+                        evt->irq = IRQ_MCT_L0;
+                        setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+                } else {
+                        mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+                        evt->irq = IRQ_MCT_L1;
+                        setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+                        irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+                }
         } else {
-                mct_tick1_event_irq.dev_id = &mct_tick[cpu];
-                evt->irq = IRQ_MCT_L1;
-                setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
-                irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+                gic_enable_ppi(IRQ_MCT_LOCALTIMER);
         }
 }
 
@@ -422,6 +442,11 @@ static void __init exynos4_timer_resources(void)
 
 static void __init exynos4_timer_init(void)
 {
+        if (soc_is_exynos4210())
+                mct_int_type = MCT_INT_SPI;
+        else
+                mct_int_type = MCT_INT_PPI;
+
         exynos4_timer_resources();
         exynos4_clocksource_init();
         exynos4_clockevent_init();