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-rw-r--r--arch/arm/mach-exynos4/cpu.c215
1 files changed, 215 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
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1/* linux/arch/arm/mach-exynos4/cpu.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/sched.h>
12#include <linux/sysdev.h>
13
14#include <asm/mach/map.h>
15#include <asm/mach/irq.h>
16
17#include <asm/proc-fns.h>
18#include <asm/hardware/cache-l2x0.h>
19
20#include <plat/cpu.h>
21#include <plat/clock.h>
22#include <plat/exynos4.h>
23#include <plat/sdhci.h>
24#include <plat/devs.h>
25#include <plat/fimc-core.h>
26
27#include <mach/regs-irq.h>
28
29extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
30 unsigned int irq_start);
31extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
32
33/* Initial IO mappings */
34static struct map_desc exynos4_iodesc[] __initdata = {
35 {
36 .virtual = (unsigned long)S5P_VA_SYSTIMER,
37 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
38 .length = SZ_4K,
39 .type = MT_DEVICE,
40 }, {
41 .virtual = (unsigned long)S5P_VA_SYSRAM,
42 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
43 .length = SZ_4K,
44 .type = MT_DEVICE,
45 }, {
46 .virtual = (unsigned long)S5P_VA_CMU,
47 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
48 .length = SZ_128K,
49 .type = MT_DEVICE,
50 }, {
51 .virtual = (unsigned long)S5P_VA_PMU,
52 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
53 .length = SZ_64K,
54 .type = MT_DEVICE,
55 }, {
56 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
57 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
58 .length = SZ_4K,
59 .type = MT_DEVICE,
60 }, {
61 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
62 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
63 .length = SZ_8K,
64 .type = MT_DEVICE,
65 }, {
66 .virtual = (unsigned long)S5P_VA_L2CC,
67 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
68 .length = SZ_4K,
69 .type = MT_DEVICE,
70 }, {
71 .virtual = (unsigned long)S5P_VA_GPIO1,
72 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
73 .length = SZ_4K,
74 .type = MT_DEVICE,
75 }, {
76 .virtual = (unsigned long)S5P_VA_GPIO2,
77 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
78 .length = SZ_4K,
79 .type = MT_DEVICE,
80 }, {
81 .virtual = (unsigned long)S5P_VA_GPIO3,
82 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
83 .length = SZ_256,
84 .type = MT_DEVICE,
85 }, {
86 .virtual = (unsigned long)S5P_VA_DMC0,
87 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
88 .length = SZ_4K,
89 .type = MT_DEVICE,
90 }, {
91 .virtual = (unsigned long)S3C_VA_UART,
92 .pfn = __phys_to_pfn(S3C_PA_UART),
93 .length = SZ_512K,
94 .type = MT_DEVICE,
95 }, {
96 .virtual = (unsigned long)S5P_VA_SROMC,
97 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
98 .length = SZ_4K,
99 .type = MT_DEVICE,
100 },
101};
102
103static void exynos4_idle(void)
104{
105 if (!need_resched())
106 cpu_do_idle();
107
108 local_irq_enable();
109}
110
111/*
112 * exynos4_map_io
113 *
114 * register the standard cpu IO areas
115 */
116void __init exynos4_map_io(void)
117{
118 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
119
120 /* initialize device information early */
121 exynos4_default_sdhci0();
122 exynos4_default_sdhci1();
123 exynos4_default_sdhci2();
124 exynos4_default_sdhci3();
125
126 s3c_fimc_setname(0, "exynos4-fimc");
127 s3c_fimc_setname(1, "exynos4-fimc");
128 s3c_fimc_setname(2, "exynos4-fimc");
129 s3c_fimc_setname(3, "exynos4-fimc");
130}
131
132void __init exynos4_init_clocks(int xtal)
133{
134 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
135
136 s3c24xx_register_baseclocks(xtal);
137 s5p_register_clocks(xtal);
138 exynos4_register_clocks();
139 exynos4_setup_clocks();
140}
141
142void __init exynos4_init_irq(void)
143{
144 int irq;
145
146 gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
147
148 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
149
150 /*
151 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
152 * connected to the interrupt combiner. These irqs
153 * should be initialized to support cascade interrupt.
154 */
155 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
156 continue;
157
158 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
159 COMBINER_IRQ(irq, 0));
160 combiner_cascade_irq(irq, IRQ_SPI(irq));
161 }
162
163 /* The parameters of s5p_init_irq() are for VIC init.
164 * Theses parameters should be NULL and 0 because EXYNOS4
165 * uses GIC instead of VIC.
166 */
167 s5p_init_irq(NULL, 0);
168}
169
170struct sysdev_class exynos4_sysclass = {
171 .name = "exynos4-core",
172};
173
174static struct sys_device exynos4_sysdev = {
175 .cls = &exynos4_sysclass,
176};
177
178static int __init exynos4_core_init(void)
179{
180 return sysdev_class_register(&exynos4_sysclass);
181}
182
183core_initcall(exynos4_core_init);
184
185#ifdef CONFIG_CACHE_L2X0
186static int __init exynos4_l2x0_cache_init(void)
187{
188 /* TAG, Data Latency Control: 2cycle */
189 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
190 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
191
192 /* L2X0 Prefetch Control */
193 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
194
195 /* L2X0 Power Control */
196 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
197 S5P_VA_L2CC + L2X0_POWER_CTRL);
198
199 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
200
201 return 0;
202}
203
204early_initcall(exynos4_l2x0_cache_init);
205#endif
206
207int __init exynos4_init(void)
208{
209 printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
210
211 /* set idle function */
212 pm_idle = exynos4_idle;
213
214 return sysdev_register(&exynos4_sysdev);
215}
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