diff options
Diffstat (limited to 'arch/arm/mach-exynos/setup-spi.c')
-rw-r--r-- | arch/arm/mach-exynos/setup-spi.c | 33 |
1 files changed, 3 insertions, 30 deletions
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c index 833ff40ee0e8..4999829d1c6e 100644 --- a/arch/arm/mach-exynos/setup-spi.c +++ b/arch/arm/mach-exynos/setup-spi.c | |||
@@ -9,21 +9,10 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/gpio.h> | 11 | #include <linux/gpio.h> |
12 | #include <linux/platform_device.h> | ||
13 | |||
14 | #include <plat/gpio-cfg.h> | 12 | #include <plat/gpio-cfg.h> |
15 | #include <plat/s3c64xx-spi.h> | ||
16 | 13 | ||
17 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | 14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 |
18 | struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { | 15 | int s3c64xx_spi0_cfg_gpio(void) |
19 | .fifo_lvl_mask = 0x1ff, | ||
20 | .rx_lvl_offset = 15, | ||
21 | .high_speed = 1, | ||
22 | .clk_from_cmu = true, | ||
23 | .tx_st_done = 25, | ||
24 | }; | ||
25 | |||
26 | int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | ||
27 | { | 16 | { |
28 | s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); | 17 | s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); |
29 | s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); | 18 | s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); |
@@ -34,15 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | |||
34 | #endif | 23 | #endif |
35 | 24 | ||
36 | #ifdef CONFIG_S3C64XX_DEV_SPI1 | 25 | #ifdef CONFIG_S3C64XX_DEV_SPI1 |
37 | struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { | 26 | int s3c64xx_spi1_cfg_gpio(void) |
38 | .fifo_lvl_mask = 0x7f, | ||
39 | .rx_lvl_offset = 15, | ||
40 | .high_speed = 1, | ||
41 | .clk_from_cmu = true, | ||
42 | .tx_st_done = 25, | ||
43 | }; | ||
44 | |||
45 | int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) | ||
46 | { | 27 | { |
47 | s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); | 28 | s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); |
48 | s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); | 29 | s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); |
@@ -53,15 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) | |||
53 | #endif | 34 | #endif |
54 | 35 | ||
55 | #ifdef CONFIG_S3C64XX_DEV_SPI2 | 36 | #ifdef CONFIG_S3C64XX_DEV_SPI2 |
56 | struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { | 37 | int s3c64xx_spi2_cfg_gpio(void) |
57 | .fifo_lvl_mask = 0x7f, | ||
58 | .rx_lvl_offset = 15, | ||
59 | .high_speed = 1, | ||
60 | .clk_from_cmu = true, | ||
61 | .tx_st_done = 25, | ||
62 | }; | ||
63 | |||
64 | int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) | ||
65 | { | 38 | { |
66 | s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); | 39 | s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); |
67 | s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); | 40 | s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); |