1 files changed, 358 insertions, 0 deletions

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4e9b4440e2bd..b5f4406fc1b5 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -19,9 +19,24 @@
 #define S5P_CENTRAL_SEQ_OPTION                  0x0208
 
 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
+#define S5P_USE_STANDBY_WFI1                    (1 << 17)
+#define S5P_USE_STANDBY_WFI2                    (1 << 19)
+#define S5P_USE_STANDBY_WFI3                    (1 << 20)
 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
+#define S5P_USE_STANDBY_WFE1                    (1 << 25)
+#define S5P_USE_STANDBY_WFE2                    (1 << 27)
+#define S5P_USE_STANDBY_WFE3                    (1 << 28)
+
+#define S5P_USE_STANDBY_WFI_ALL \
+        (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \
+         S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \
+         S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \
+         S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3)
+
 #define S5P_USE_DELAYED_RESET_ASSERTION         BIT(12)
 
+#define EXYNOS_CORE_PO_RESET(n)                 ((1 << 4) << n)
+#define EXYNOS_WAKEUP_FROM_LOWPWR               (1 << 28)
 #define EXYNOS_SWRESET                          0x0400
 #define EXYNOS5440_SWRESET                      0x00C4
 
@@ -36,6 +51,7 @@
 #define S5P_INFORM7                             0x081C
 #define S5P_PMU_SPARE3                          0x090C
 
+#define EXYNOS_IROM_DATA2                       0x0988
 #define S5P_ARM_CORE0_LOWPWR                    0x1000
 #define S5P_DIS_IRQ_CORE0                       0x1004
 #define S5P_DIS_IRQ_CENTRAL0                    0x1008
@@ -118,6 +134,31 @@
 #define EXYNOS_COMMON_OPTION(_nr)               \
                         (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
 
+#define EXYNOS_CORE_LOCAL_PWR_EN                0x3
+
+#define EXYNOS_ARM_COMMON_STATUS                0x2504
+#define EXYNOS_COMMON_OPTION(_nr)               \
+                        (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
+
+#define EXYNOS_ARM_L2_CONFIGURATION             0x2600
+#define EXYNOS_L2_CONFIGURATION(_nr)            \
+                        (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80))
+#define EXYNOS_L2_STATUS(_nr)                   \
+                        (EXYNOS_L2_CONFIGURATION(_nr) + 0x4)
+#define EXYNOS_L2_OPTION(_nr)                   \
+                        (EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
+#define EXYNOS_L2_COMMON_PWR_EN                 0x3
+
+#define EXYNOS_ARM_CORE_X_STATUS_OFFSET         0x4
+
+#define EXYNOS5_APLL_SYSCLK_CONFIGURATION       0x2A00
+#define EXYNOS5_APLL_SYSCLK_STATUS              0x2A04
+
+#define EXYNOS5_ARM_L2_OPTION                   0x2608
+#define EXYNOS5_USE_RETENTION                   BIT(4)
+
+#define EXYNOS5_L2RSTDISABLE_VALUE              BIT(3)
+
 #define S5P_PAD_RET_MAUDIO_OPTION               0x3028
 #define S5P_PAD_RET_GPIO_OPTION                 0x3108
 #define S5P_PAD_RET_UART_OPTION                 0x3128
@@ -126,7 +167,19 @@
 #define S5P_PAD_RET_EBIA_OPTION                 0x3188
 #define S5P_PAD_RET_EBIB_OPTION                 0x31A8
 
+#define S5P_PS_HOLD_CONTROL                     0x330C
+#define S5P_PS_HOLD_EN                          (1 << 31)
+#define S5P_PS_HOLD_OUTPUT_HIGH                 (3 << 8)
+
+#define S5P_CAM_OPTION                          0x3C08
+#define S5P_MFC_OPTION                          0x3C48
+#define S5P_G3D_OPTION                          0x3C68
+#define S5P_LCD0_OPTION                         0x3C88
+#define S5P_LCD1_OPTION                         0x3CA8
+#define S5P_ISP_OPTION                          S5P_LCD1_OPTION
+
 #define S5P_CORE_LOCAL_PWR_EN                   0x3
+#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG          (0x3 << 8)
 
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR     0x1154
@@ -185,11 +238,116 @@
 #define S5P_DIS_IRQ_CORE3                       0x1034
 #define S5P_DIS_IRQ_CENTRAL3                    0x1038
 
+/* Only for EXYNOS3XXX */
+#define EXYNOS3_ARM_CORE0_SYS_PWR_REG                   0x1000
+#define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG     0x1004
+#define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG   0x1008
+#define EXYNOS3_ARM_CORE1_SYS_PWR_REG                   0x1010
+#define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG     0x1014
+#define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG   0x1018
+#define EXYNOS3_ISP_ARM_SYS_PWR_REG                     0x1050
+#define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG       0x1054
+#define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG     0x1058
+#define EXYNOS3_ARM_COMMON_SYS_PWR_REG                  0x1080
+#define EXYNOS3_ARM_L2_SYS_PWR_REG                      0x10C0
+#define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG                0x1100
+#define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG                0x1104
+#define EXYNOS3_CMU_RESET_SYS_PWR_REG                   0x110C
+#define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG        0x1110
+#define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG        0x1114
+#define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG           0x111C
+#define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG                 0x1120
+#define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG                 0x1124
+#define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG                 0x1128
+#define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG                 0x112C
+#define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG             0x1130
+#define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG             0x1134
+#define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG             0x1138
+#define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG             0x1140
+#define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG             0x1148
+#define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG             0x114C
+#define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG            0x1150
+#define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG             0x1154
+#define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG          0x1158
+#define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG               0x1160
+#define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG               0x1168
+#define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG               0x116C
+#define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG              0x1170
+#define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG               0x1174
+#define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG            0x1178
+#define EXYNOS3_TOP_BUS_SYS_PWR_REG                     0x1180
+#define EXYNOS3_TOP_RETENTION_SYS_PWR_REG               0x1184
+#define EXYNOS3_TOP_PWR_SYS_PWR_REG                     0x1188
+#define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG             0x1190
+#define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG       0x1194
+#define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG             0x1198
+#define EXYNOS3_LOGIC_RESET_SYS_PWR_REG                 0x11A0
+#define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG                 0x11A4
+#define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG         0x11B0
+#define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG         0x11B4
+#define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG          0x1200
+#define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG        0x1204
+#define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG           0x1208
+#define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG          0x1218
+#define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG          0x1220
+#define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG          0x1224
+#define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG          0x1228
+#define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG          0x122C
+#define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG          0x1230
+#define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG          0x1234
+#define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG          0x1238
+#define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG               0x1240
+#define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG                 0x1260
+#define EXYNOS3_XUSBXTI_SYS_PWR_REG                     0x1280
+#define EXYNOS3_XXTI_SYS_PWR_REG                        0x1284
+#define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG               0x12C0
+#define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG       0x12C4
+#define EXYNOS3_GPIO_MODE_SYS_PWR_REG                   0x1300
+#define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG            0x1340
+#define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG               0x1344
+#define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG           0x1348
+#define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG       0x1350
+#define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG   0x1354
+#define EXYNOS3_CAM_SYS_PWR_REG                         0x1380
+#define EXYNOS3_MFC_SYS_PWR_REG                         0x1388
+#define EXYNOS3_G3D_SYS_PWR_REG                         0x138C
+#define EXYNOS3_LCD0_SYS_PWR_REG                        0x1390
+#define EXYNOS3_ISP_SYS_PWR_REG                         0x1394
+#define EXYNOS3_MAUDIO_SYS_PWR_REG                      0x1398
+#define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG              0x13B0
+#define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG               0x13B4
+#define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG              0x13B8
+#define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG          0x13C0
+#define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG                 0x13C4
+#define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG                 0x13C8
+
+#define EXYNOS3_ARM_CORE0_OPTION                        0x2008
+#define EXYNOS3_ARM_CORE_OPTION(_nr)    \
+                        (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80))
+
+#define EXYNOS3_ARM_COMMON_OPTION                       0x2408
+#define EXYNOS3_TOP_PWR_OPTION                          0x2C48
+#define EXYNOS3_CORE_TOP_PWR_OPTION                     0x2CA8
+#define EXYNOS3_XUSBXTI_DURATION                        0x341C
+#define EXYNOS3_XXTI_DURATION                           0x343C
+#define EXYNOS3_EXT_REGULATOR_DURATION                  0x361C
+#define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION          0x363C
+#define XUSBXTI_DURATION                                0x00000BB8
+#define XXTI_DURATION                                   XUSBXTI_DURATION
+#define EXT_REGULATOR_DURATION                          0x00001D4C
+#define EXT_REGULATOR_COREBLK_DURATION                  EXT_REGULATOR_DURATION
+
+/* for XXX_OPTION */
+#define EXYNOS3_OPTION_USE_SC_COUNTER                   (1 << 0)
+#define EXYNOS3_OPTION_USE_SC_FEEDBACK                  (1 << 1)
+#define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN   (1 << 7)
+
 /* For EXYNOS5 */
 
 #define EXYNOS5_AUTO_WDTRESET_DISABLE                           0x0408
 #define EXYNOS5_MASK_WDTRESET_REQUEST                           0x040C
 
+#define EXYNOS5_USE_RETENTION                   BIT(4)
 #define EXYNOS5_SYS_WDTRESET                                    (1 << 20)
 
 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG                           0x1000
@@ -329,4 +487,204 @@ static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
                  + MPIDR_AFFINITY_LEVEL(mpidr, 0));
 }
 
+/* Only for EXYNOS5420 */
+#define EXYNOS5420_ISP_ARM_OPTION                               0x2488
+#define EXYNOS5420_L2RSTDISABLE_VALUE                           BIT(3)
+
+#define EXYNOS5420_LPI_MASK                                     0x0004
+#define EXYNOS5420_LPI_MASK1                                    0x0008
+#define EXYNOS5420_UFS                                          BIT(8)
+#define EXYNOS5420_ATB_KFC                                      BIT(13)
+#define EXYNOS5420_ATB_ISP_ARM                                  BIT(19)
+#define EXYNOS5420_EMULATION                                    BIT(31)
+#define ATB_ISP_ARM                                             BIT(12)
+#define ATB_KFC                                                 BIT(13)
+#define ATB_NOC                                                 BIT(14)
+
+#define EXYNOS5420_ARM_INTR_SPREAD_ENABLE                       0x0100
+#define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI               0x0104
+#define EXYNOS5420_UP_SCHEDULER                                 0x0120
+#define SPREAD_ENABLE                                           0xF
+#define SPREAD_USE_STANDWFI                                     0xF
+
+#define EXYNOS5420_BB_CON1                                      0x0784
+#define EXYNOS5420_BB_SEL_EN                                    BIT(31)
+#define EXYNOS5420_BB_PMOS_EN                                   BIT(7)
+#define EXYNOS5420_BB_1300X                                     0XF
+
+#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG                        0x1020
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG          0x1024
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG        0x1028
+#define EXYNOS5420_ARM_CORE3_SYS_PWR_REG                        0x1030
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG          0x1034
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG        0x1038
+#define EXYNOS5420_KFC_CORE0_SYS_PWR_REG                        0x1040
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG          0x1044
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG        0x1048
+#define EXYNOS5420_KFC_CORE1_SYS_PWR_REG                        0x1050
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG          0x1054
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG        0x1058
+#define EXYNOS5420_KFC_CORE2_SYS_PWR_REG                        0x1060
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG          0x1064
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG        0x1068
+#define EXYNOS5420_KFC_CORE3_SYS_PWR_REG                        0x1070
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG          0x1074
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG        0x1078
+#define EXYNOS5420_ISP_ARM_SYS_PWR_REG                          0x1090
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG            0x1094
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG          0x1098
+#define EXYNOS5420_ARM_COMMON_SYS_PWR_REG                       0x10A0
+#define EXYNOS5420_KFC_COMMON_SYS_PWR_REG                       0x10B0
+#define EXYNOS5420_KFC_L2_SYS_PWR_REG                           0x10D0
+#define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG                      0x1158
+#define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG                      0x115C
+#define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG                      0x1160
+#define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG                      0x1174
+#define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG                      0x1178
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG                       0x11B8
+#define EXYNOS5420_INTROM_MEM_SYS_PWR_REG                       0x11BC
+#define EXYNOS5420_ONENANDXL_MEM_SYS_PWR                        0x11C0
+#define EXYNOS5420_USBDEV_MEM_SYS_PWR                           0x11CC
+#define EXYNOS5420_USBDEV1_MEM_SYS_PWR                          0x11D0
+#define EXYNOS5420_SDMMC_MEM_SYS_PWR                            0x11D4
+#define EXYNOS5420_CSSYS_MEM_SYS_PWR                            0x11D8
+#define EXYNOS5420_SECSS_MEM_SYS_PWR                            0x11DC
+#define EXYNOS5420_ROTATOR_MEM_SYS_PWR                          0x11E0
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR                           0x11E4
+#define EXYNOS5420_INTROM_MEM_SYS_PWR                           0x11E8
+#define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG               0x1208
+#define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG               0x1210
+#define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG               0x1214
+#define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG               0x1218
+#define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG               0x121C
+#define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG               0x1220
+#define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG                0x1224
+#define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG               0x1228
+#define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG               0x122C
+#define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG                0x1230
+#define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG       0x1234
+#define EXYNOS5420_DISP1_SYS_PWR_REG                            0x1410
+#define EXYNOS5420_MAU_SYS_PWR_REG                              0x1414
+#define EXYNOS5420_G2D_SYS_PWR_REG                              0x1418
+#define EXYNOS5420_MSC_SYS_PWR_REG                              0x141C
+#define EXYNOS5420_FSYS_SYS_PWR_REG                             0x1420
+#define EXYNOS5420_FSYS2_SYS_PWR_REG                            0x1424
+#define EXYNOS5420_PSGEN_SYS_PWR_REG                            0x1428
+#define EXYNOS5420_PERIC_SYS_PWR_REG                            0x142C
+#define EXYNOS5420_WCORE_SYS_PWR_REG                            0x1430
+#define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG                0x1490
+#define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG                  0x1494
+#define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG                  0x1498
+#define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG                  0x149C
+#define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG                 0x14A0
+#define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG                0x14A4
+#define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG                0x14A8
+#define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG                0x14AC
+#define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG                0x14B0
+#define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG                0x14BC
+#define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG                 0x14D0
+#define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG                   0x14D4
+#define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG                   0x14D8
+#define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG                   0x14DC
+#define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG                  0x14E0
+#define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG                 0x14E4
+#define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG                 0x14E8
+#define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG                 0x14EC
+#define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG                 0x14F0
+#define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG         0x14F4
+#define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG                  0x1570
+#define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG                  0x1574
+#define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG                  0x1578
+#define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG                  0x157C
+#define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG                  0x1590
+#define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG                    0x1594
+#define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG                    0x1598
+#define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG                    0x159C
+#define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG                   0x15A0
+#define EXYNOS5420_SFR_AXI_CGDIS1                               0x15E4
+#define EXYNOS_ARM_CORE2_CONFIGURATION                          0x2100
+#define EXYNOS5420_ARM_CORE2_OPTION                             0x2108
+#define EXYNOS_ARM_CORE3_CONFIGURATION                          0x2180
+#define EXYNOS5420_ARM_CORE3_OPTION                             0x2188
+#define EXYNOS5420_ARM_COMMON_STATUS                            0x2504
+#define EXYNOS5420_ARM_COMMON_OPTION                            0x2508
+#define EXYNOS5420_KFC_COMMON_STATUS                            0x2584
+#define EXYNOS5420_KFC_COMMON_OPTION                            0x2588
+#define EXYNOS5420_LOGIC_RESET_DURATION3                        0x2D1C
+
+#define EXYNOS5420_PAD_RET_GPIO_OPTION                          0x30C8
+#define EXYNOS5420_PAD_RET_UART_OPTION                          0x30E8
+#define EXYNOS5420_PAD_RET_MMCA_OPTION                          0x3108
+#define EXYNOS5420_PAD_RET_MMCB_OPTION                          0x3128
+#define EXYNOS5420_PAD_RET_MMCC_OPTION                          0x3148
+#define EXYNOS5420_PAD_RET_HSI_OPTION                           0x3168
+#define EXYNOS5420_PAD_RET_SPI_OPTION                           0x31C8
+#define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION                  0x31E8
+#define EXYNOS_PAD_RET_DRAM_OPTION                              0x3008
+#define EXYNOS_PAD_RET_MAUDIO_OPTION                            0x3028
+#define EXYNOS_PAD_RET_JTAG_OPTION                              0x3048
+#define EXYNOS_PAD_RET_GPIO_OPTION                              0x3108
+#define EXYNOS_PAD_RET_UART_OPTION                              0x3128
+#define EXYNOS_PAD_RET_MMCA_OPTION                              0x3148
+#define EXYNOS_PAD_RET_MMCB_OPTION                              0x3168
+#define EXYNOS_PAD_RET_EBIA_OPTION                              0x3188
+#define EXYNOS_PAD_RET_EBIB_OPTION                              0x31A8
+
+#define EXYNOS_PS_HOLD_CONTROL                                  0x330C
+
+/* For SYS_PWR_REG */
+#define EXYNOS_SYS_PWR_CFG                                      BIT(0)
+
+#define EXYNOS5420_MFC_CONFIGURATION                            0x4060
+#define EXYNOS5420_MFC_STATUS                                   0x4064
+#define EXYNOS5420_MFC_OPTION                                   0x4068
+#define EXYNOS5420_G3D_CONFIGURATION                            0x4080
+#define EXYNOS5420_G3D_STATUS                                   0x4084
+#define EXYNOS5420_G3D_OPTION                                   0x4088
+#define EXYNOS5420_DISP0_CONFIGURATION                          0x40A0
+#define EXYNOS5420_DISP0_STATUS                                 0x40A4
+#define EXYNOS5420_DISP0_OPTION                                 0x40A8
+#define EXYNOS5420_DISP1_CONFIGURATION                          0x40C0
+#define EXYNOS5420_DISP1_STATUS                                 0x40C4
+#define EXYNOS5420_DISP1_OPTION                                 0x40C8
+#define EXYNOS5420_MAU_CONFIGURATION                            0x40E0
+#define EXYNOS5420_MAU_STATUS                                   0x40E4
+#define EXYNOS5420_MAU_OPTION                                   0x40E8
+#define EXYNOS5420_FSYS2_OPTION                                 0x4168
+#define EXYNOS5420_PSGEN_OPTION                                 0x4188
+
+/* For EXYNOS_CENTRAL_SEQ_OPTION */
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0                        BIT(16)
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1                        BUT(17)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0                        BIT(24)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1                        BIT(25)
+
+#define EXYNOS5420_ARM_USE_STANDBY_WFI0                         BIT(4)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI1                         BIT(5)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI2                         BIT(6)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI3                         BIT(7)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI0                         BIT(8)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI1                         BIT(9)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI2                         BIT(10)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI3                         BIT(11)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE0                         BIT(16)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE1                         BIT(17)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE2                         BIT(18)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE3                         BIT(19)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE0                         BIT(20)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE1                         BIT(21)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE2                         BIT(22)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE3                         BIT(23)
+
+#define DUR_WAIT_RESET                          0xF
+
+#define EXYNOS5420_USE_STANDBY_WFI_ALL  (EXYNOS5420_ARM_USE_STANDBY_WFI0    \
+                                         | EXYNOS5420_ARM_USE_STANDBY_WFI1  \
+                                         | EXYNOS5420_ARM_USE_STANDBY_WFI2  \
+                                         | EXYNOS5420_ARM_USE_STANDBY_WFI3  \
+                                         | EXYNOS5420_KFC_USE_STANDBY_WFI0  \
+                                         | EXYNOS5420_KFC_USE_STANDBY_WFI1  \
+                                         | EXYNOS5420_KFC_USE_STANDBY_WFI2  \
+                                         | EXYNOS5420_KFC_USE_STANDBY_WFI3)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */